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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 01/48] rust: pl011: fix repr(C) for PL011Class
Date: Fri, 24 Jan 2025 10:43:55 +0100
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 994c2fc0593..65a1234b9ff 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -123,6 +123,7 @@ pub struct PL011State {
=20
qom_isa!(PL011State : SysBusDevice, DeviceState, Object);
=20
+#[repr(C)]
pub struct PL011Class {
parent_class: <SysBusDevice as ObjectType>::Class,
/// The byte string that identifies the device.
--=20
2.48.1
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The code of gen_Jcc is very similar to gen_LOOP* and gen_JCXZ, but this
is hidden by gen_jcc.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-2-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 8 --------
target/i386/tcg/emit.c.inc | 5 ++++-
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index dbc9d637c4b..3b68441a561 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1847,14 +1847,6 @@ static void gen_conditional_jump_labels(DisasContext=
*s, target_long diff,
gen_jmp_rel(s, s->dflag, diff, 0);
}
=20
-static void gen_jcc(DisasContext *s, int b, int diff)
-{
- TCGLabel *l1 =3D gen_new_label();
-
- gen_jcc1(s, b, l1);
- gen_conditional_jump_labels(s, diff, NULL, l1);
-}
-
static void gen_cmovcc1(DisasContext *s, int b, TCGv dest, TCGv src)
{
CCPrepare cc =3D gen_prepare_cc(s, b, NULL);
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index c4cc5f48d83..a193d32ca76 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -2297,8 +2297,11 @@ static void gen_IRET(DisasContext *s, X86DecodedInsn=
*decode)
=20
static void gen_Jcc(DisasContext *s, X86DecodedInsn *decode)
{
+ TCGLabel *taken =3D gen_new_label();
+
gen_bnd_jmp(s);
- gen_jcc(s, decode->b & 0xf, decode->immediate);
+ gen_jcc1(s, decode->b & 0xf, taken);
+ gen_conditional_jump_labels(s, decode->immediate, NULL, taken);
}
=20
static void gen_JCXZ(DisasContext *s, X86DecodedInsn *decode)
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 03/48] target/i386: remove trailing 1 from gen_{j, cmov,
set}cc1
Date: Fri, 24 Jan 2025 10:43:57 +0100
Message-ID: <20250124094442.13207-4-pbonzini@redhat.com>
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This is not needed anymore now that gen_jcc has been eliminated
(merged into the similarly-named gen_Jcc, where the uppercase letter
gives away that it is an emission function).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-3-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 14 +++++++-------
target/i386/tcg/emit.c.inc | 10 +++++-----
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 3b68441a561..a2101b5615e 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1148,7 +1148,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int =
b, TCGv reg)
return cc;
}
=20
-static void gen_setcc1(DisasContext *s, int b, TCGv reg)
+static void gen_setcc(DisasContext *s, int b, TCGv reg)
{
CCPrepare cc =3D gen_prepare_cc(s, b, reg);
=20
@@ -1170,12 +1170,12 @@ static void gen_setcc1(DisasContext *s, int b, TCGv=
reg)
=20
static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg)
{
- gen_setcc1(s, JCC_B << 1, reg);
+ gen_setcc(s, JCC_B << 1, reg);
}
=20
/* generate a conditional jump to label 'l1' according to jump opcode
value 'b'. In the fast case, T0 is guaranteed not to be used. */
-static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1)
+static inline void gen_jcc_noeob(DisasContext *s, int b, TCGLabel *l1)
{
CCPrepare cc =3D gen_prepare_cc(s, b, NULL);
=20
@@ -1190,7 +1190,7 @@ static inline void gen_jcc1_noeob(DisasContext *s, in=
t b, TCGLabel *l1)
value 'b'. In the fast case, T0 is guaranteed not to be used.
One or both of the branches will call gen_jmp_rel, so ensure
cc_op is clean. */
-static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1)
+static inline void gen_jcc(DisasContext *s, int b, TCGLabel *l1)
{
CCPrepare cc =3D gen_prepare_cc(s, b, NULL);
=20
@@ -1337,7 +1337,7 @@ static void gen_repz_nz(DisasContext *s, MemOp ot,
l2 =3D gen_jz_ecx_string(s);
fn(s, ot);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
- gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2);
+ gen_jcc(s, (JCC_Z << 1) | (nz ^ 1), l2);
if (s->repz_opt) {
gen_op_jz_ecx(s, l2);
}
@@ -1847,7 +1847,7 @@ static void gen_conditional_jump_labels(DisasContext =
*s, target_long diff,
gen_jmp_rel(s, s->dflag, diff, 0);
}
=20
-static void gen_cmovcc1(DisasContext *s, int b, TCGv dest, TCGv src)
+static void gen_cmovcc(DisasContext *s, int b, TCGv dest, TCGv src)
{
CCPrepare cc =3D gen_prepare_cc(s, b, NULL);
=20
@@ -2856,7 +2856,7 @@ static void gen_x87(DisasContext *s, X86DecodedInsn *=
decode)
}
op1 =3D fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 =3D gen_new_label();
- gen_jcc1_noeob(s, op1, l1);
+ gen_jcc_noeob(s, op1, l1);
gen_helper_fmov_ST0_STN(tcg_env,
tcg_constant_i32(opreg));
gen_set_label(l1);
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index a193d32ca76..861f0fb70f3 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1634,7 +1634,7 @@ static void gen_CMC(DisasContext *s, X86DecodedInsn *=
decode)
=20
static void gen_CMOVcc(DisasContext *s, X86DecodedInsn *decode)
{
- gen_cmovcc1(s, decode->b & 0xf, s->T0, s->T1);
+ gen_cmovcc(s, decode->b & 0xf, s->T0, s->T1);
}
=20
static void gen_CMPccXADD(DisasContext *s, X86DecodedInsn *decode)
@@ -2300,7 +2300,7 @@ static void gen_Jcc(DisasContext *s, X86DecodedInsn *=
decode)
TCGLabel *taken =3D gen_new_label();
=20
gen_bnd_jmp(s);
- gen_jcc1(s, decode->b & 0xf, taken);
+ gen_jcc(s, decode->b & 0xf, taken);
gen_conditional_jump_labels(s, decode->immediate, NULL, taken);
}
=20
@@ -2451,7 +2451,7 @@ static void gen_LOOPE(DisasContext *s, X86DecodedInsn=
*decode)
gen_update_cc_op(s);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
gen_op_jz_ecx(s, not_taken);
- gen_jcc1(s, (JCC_Z << 1), taken); /* jz taken */
+ gen_jcc(s, (JCC_Z << 1), taken); /* jz taken */
gen_conditional_jump_labels(s, decode->immediate, not_taken, taken);
}
=20
@@ -2463,7 +2463,7 @@ static void gen_LOOPNE(DisasContext *s, X86DecodedIns=
n *decode)
gen_update_cc_op(s);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
gen_op_jz_ecx(s, not_taken);
- gen_jcc1(s, (JCC_Z << 1) | 1, taken); /* jnz taken */
+ gen_jcc(s, (JCC_Z << 1) | 1, taken); /* jnz taken */
gen_conditional_jump_labels(s, decode->immediate, not_taken, taken);
}
=20
@@ -3888,7 +3888,7 @@ static void gen_SCAS(DisasContext *s, X86DecodedInsn =
*decode)
=20
static void gen_SETcc(DisasContext *s, X86DecodedInsn *decode)
{
- gen_setcc1(s, decode->b & 0xf, s->T0);
+ gen_setcc(s, decode->b & 0xf, s->T0);
}
=20
static void gen_SFENCE(DisasContext *s, X86DecodedInsn *decode)
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 04/48] target/i386: unify REP and REPZ/REPNZ generation
Date: Fri, 24 Jan 2025 10:43:58 +0100
Message-ID: <20250124094442.13207-5-pbonzini@redhat.com>
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It only differs in a single call to gen_jcc, so use a "bool" argument
to distinguish the two cases; do not duplicate code.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-4-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 39 +++++++++++++++++++------------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index a2101b5615e..877b5846114 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1310,14 +1310,18 @@ static void gen_outs(DisasContext *s, MemOp ot)
gen_bpt_io(s, s->tmp2_i32, ot);
}
=20
-/* Generate jumps to current or next instruction */
-static void gen_repz(DisasContext *s, MemOp ot,
- void (*fn)(DisasContext *s, MemOp ot))
+static void do_gen_rep(DisasContext *s, MemOp ot,
+ void (*fn)(DisasContext *s, MemOp ot),
+ bool is_repz_nz)
{
TCGLabel *l2;
l2 =3D gen_jz_ecx_string(s);
fn(s, ot);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
+ if (is_repz_nz) {
+ int nz =3D (s->prefix & PREFIX_REPNZ) ? 1 : 0;
+ gen_jcc(s, (JCC_Z << 1) | (nz ^ 1), l2);
+ }
/*
* A loop would cause two single step exceptions if ECX =3D 1
* before rep string_insn
@@ -1325,28 +1329,25 @@ static void gen_repz(DisasContext *s, MemOp ot,
if (s->repz_opt) {
gen_op_jz_ecx(s, l2);
}
+ /*
+ * For CMPS/SCAS there is no need to set CC_OP_DYNAMIC: only one itera=
tion
+ * is done at a time, so the translation block ends unconditionally af=
ter
+ * this instruction and there is no control flow junction.
+ */
gen_jmp_rel_csize(s, -cur_insn_len(s), 0);
}
=20
+static void gen_repz(DisasContext *s, MemOp ot,
+ void (*fn)(DisasContext *s, MemOp ot))
+
+{
+ do_gen_rep(s, ot, fn, false);
+}
+
static void gen_repz_nz(DisasContext *s, MemOp ot,
void (*fn)(DisasContext *s, MemOp ot))
{
- TCGLabel *l2;
- int nz =3D (s->prefix & PREFIX_REPNZ) ? 1 : 0;
-
- l2 =3D gen_jz_ecx_string(s);
- fn(s, ot);
- gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
- gen_jcc(s, (JCC_Z << 1) | (nz ^ 1), l2);
- if (s->repz_opt) {
- gen_op_jz_ecx(s, l2);
- }
- /*
- * Only one iteration is done at a time, so the translation
- * block ends unconditionally after this instruction and there
- * is no control flow junction - no need to set CC_OP_DYNAMIC.
- */
- gen_jmp_rel_csize(s, -cur_insn_len(s), 0);
+ do_gen_rep(s, ot, fn, true);
}
=20
static void gen_helper_fp_arith_ST0_FT0(int op)
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 05/48] target/i386: unify choice between single and repeated
string instructions
Date: Fri, 24 Jan 2025 10:43:59 +0100
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The same "if" is present in all generator functions for string instructions.
Push it inside gen_repz() and gen_repz_nz() instead.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Link: https://lore.kernel.org/r/20241215090613.89588-5-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 12 +++++++++--
target/i386/tcg/emit.c.inc | 42 +++++++------------------------------
2 files changed, 17 insertions(+), 37 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 877b5846114..3e46be8d78d 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1341,13 +1341,21 @@ static void gen_repz(DisasContext *s, MemOp ot,
void (*fn)(DisasContext *s, MemOp ot))
=20
{
- do_gen_rep(s, ot, fn, false);
+ if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
+ do_gen_rep(s, ot, fn, false);
+ } else {
+ fn(s, ot);
+ }
}
=20
static void gen_repz_nz(DisasContext *s, MemOp ot,
void (*fn)(DisasContext *s, MemOp ot))
{
- do_gen_rep(s, ot, fn, true);
+ if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
+ do_gen_rep(s, ot, fn, true);
+ } else {
+ fn(s, ot);
+ }
}
=20
static void gen_helper_fp_arith_ST0_FT0(int op)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 861f0fb70f3..3a28b0cb31b 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1743,11 +1743,7 @@ static void gen_CMPccXADD(DisasContext *s, X86Decode=
dInsn *decode)
static void gen_CMPS(DisasContext *s, X86DecodedInsn *decode)
{
MemOp ot =3D decode->op[2].ot;
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- gen_repz_nz(s, ot, gen_cmps);
- } else {
- gen_cmps(s, ot);
- }
+ gen_repz_nz(s, ot, gen_cmps);
}
=20
static void gen_CMPXCHG(DisasContext *s, X86DecodedInsn *decode)
@@ -2238,11 +2234,7 @@ static void gen_INS(DisasContext *s, X86DecodedInsn =
*decode)
}
=20
translator_io_start(&s->base);
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- gen_repz(s, ot, gen_ins);
- } else {
- gen_ins(s, ot);
- }
+ gen_repz(s, ot, gen_ins);
}
=20
static void gen_INSERTQ_i(DisasContext *s, X86DecodedInsn *decode)
@@ -2426,11 +2418,7 @@ static void gen_LGS(DisasContext *s, X86DecodedInsn =
*decode)
static void gen_LODS(DisasContext *s, X86DecodedInsn *decode)
{
MemOp ot =3D decode->op[1].ot;
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- gen_repz(s, ot, gen_lods);
- } else {
- gen_lods(s, ot);
- }
+ gen_repz(s, ot, gen_lods);
}
=20
static void gen_LOOP(DisasContext *s, X86DecodedInsn *decode)
@@ -2628,11 +2616,7 @@ static void gen_MOVq_dq(DisasContext *s, X86DecodedI=
nsn *decode)
static void gen_MOVS(DisasContext *s, X86DecodedInsn *decode)
{
MemOp ot =3D decode->op[2].ot;
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- gen_repz(s, ot, gen_movs);
- } else {
- gen_movs(s, ot);
- }
+ gen_repz(s, ot, gen_movs);
}
=20
static void gen_MUL(DisasContext *s, X86DecodedInsn *decode)
@@ -2794,11 +2778,7 @@ static void gen_OUTS(DisasContext *s, X86DecodedInsn=
*decode)
}
=20
translator_io_start(&s->base);
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- gen_repz(s, ot, gen_outs);
- } else {
- gen_outs(s, ot);
- }
+ gen_repz(s, ot, gen_outs);
}
=20
static void gen_PALIGNR(DisasContext *s, X86DecodedInsn *decode)
@@ -3879,11 +3859,7 @@ static void gen_SBB(DisasContext *s, X86DecodedInsn =
*decode)
static void gen_SCAS(DisasContext *s, X86DecodedInsn *decode)
{
MemOp ot =3D decode->op[2].ot;
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- gen_repz_nz(s, ot, gen_scas);
- } else {
- gen_scas(s, ot);
- }
+ gen_repz_nz(s, ot, gen_scas);
}
=20
static void gen_SETcc(DisasContext *s, X86DecodedInsn *decode)
@@ -4089,11 +4065,7 @@ static void gen_STMXCSR(DisasContext *s, X86DecodedI=
nsn *decode)
static void gen_STOS(DisasContext *s, X86DecodedInsn *decode)
{
MemOp ot =3D decode->op[1].ot;
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- gen_repz(s, ot, gen_stos);
- } else {
- gen_stos(s, ot);
- }
+ gen_repz(s, ot, gen_stos);
}
=20
static void gen_SUB(DisasContext *s, X86DecodedInsn *decode)
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 06/48] target/i386: reorganize ops emitted by do_gen_rep,
drop repz_opt
Date: Fri, 24 Jan 2025 10:44:00 +0100
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The condition for optimizing repeat instruction is more or less the
opposite of what you imagine: almost always the string instruction
was _not_ optimized and optimizing the loop relied on goto_tb.
This is obviously not great for performance, due to the cost of the
exit-to-main-loop check, but also wrong. In fact, after expanding
dc->jmp_opt and simplifying "!!x" to "x", the condition for looping used
to be:
((cflags & CF_NO_GOTO_TB) ||
(flags & (HF_RF_MASK | HF_TF_MASK | HF_INHIBIT_IRQ_MASK))) && !(cflags =
& CF_USE_ICOUNT)
In other words, setting aside RF (it requires special handling for REP
instructions and it was completely missing), repeat instruction were
being optimized if TF or inhibit IRQ flags were set. This is certainly
wrong for TF, because string instructions trap after every execution,
and probably for interrupt shadow too.
Get rid of repz_opt completely. The next patches will reintroduce the
optimization, applying it in the common case instead of the unlikely
and wrong one.
While at it, place the CX/ECX/RCX=3D0 case is at the end of the function,
which saves a label and is clearer when reading the generated ops.
For clarity, mark the cc_op explicitly as DYNAMIC even if at the end
of the translation block; the cc_op can come from either the previous
instruction or the string instruction, and currently we rely on
a gen_update_cc_op() that is hidden in the bowels of gen_jcc() to
spill cc_op and mark it clean.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-6-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 60 ++++++++-----------------------------
1 file changed, 13 insertions(+), 47 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 3e46be8d78d..ee536234398 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -113,7 +113,6 @@ typedef struct DisasContext {
#endif
bool vex_w; /* used by AVX even on 32-bit processors */
bool jmp_opt; /* use direct block chaining for direct jumps */
- bool repz_opt; /* optimize jumps within repz instructions */
bool cc_op_dirty;
=20
CCOp cc_op; /* current CC operation */
@@ -1206,23 +1205,6 @@ static inline void gen_jcc(DisasContext *s, int b, T=
CGLabel *l1)
}
}
=20
-/* XXX: does not work with gdbstub "ice" single step - not a
- serious problem. The caller can jump to the returned label
- to stop the REP but, if the flags have changed, it has to call
- gen_update_cc_op before doing so. */
-static TCGLabel *gen_jz_ecx_string(DisasContext *s)
-{
- TCGLabel *l1 =3D gen_new_label();
- TCGLabel *l2 =3D gen_new_label();
-
- gen_update_cc_op(s);
- gen_op_jnz_ecx(s, l1);
- gen_set_label(l2);
- gen_jmp_rel_csize(s, 0, 1);
- gen_set_label(l1);
- return l2;
-}
-
static void gen_stos(DisasContext *s, MemOp ot)
{
gen_string_movl_A0_EDI(s);
@@ -1314,27 +1296,25 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
void (*fn)(DisasContext *s, MemOp ot),
bool is_repz_nz)
{
- TCGLabel *l2;
- l2 =3D gen_jz_ecx_string(s);
+ TCGLabel *done =3D gen_new_label();
+
+ gen_update_cc_op(s);
+ gen_op_jz_ecx(s, done);
+
fn(s, ot);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
if (is_repz_nz) {
int nz =3D (s->prefix & PREFIX_REPNZ) ? 1 : 0;
- gen_jcc(s, (JCC_Z << 1) | (nz ^ 1), l2);
+ gen_jcc(s, (JCC_Z << 1) | (nz ^ 1), done);
}
- /*
- * A loop would cause two single step exceptions if ECX =3D 1
- * before rep string_insn
- */
- if (s->repz_opt) {
- gen_op_jz_ecx(s, l2);
- }
- /*
- * For CMPS/SCAS there is no need to set CC_OP_DYNAMIC: only one itera=
tion
- * is done at a time, so the translation block ends unconditionally af=
ter
- * this instruction and there is no control flow junction.
- */
+
+ /* Go to the main loop but reenter the same instruction. */
gen_jmp_rel_csize(s, -cur_insn_len(s), 0);
+
+ /* CX/ECX/RCX is zero, or REPZ/REPNZ broke the repetition. */
+ gen_set_label(done);
+ set_cc_op(s, CC_OP_DYNAMIC);
+ gen_jmp_rel_csize(s, 0, 1);
}
=20
static void gen_repz(DisasContext *s, MemOp ot,
@@ -3665,20 +3645,6 @@ static void i386_tr_init_disas_context(DisasContextB=
ase *dcbase, CPUState *cpu)
dc->cpuid_xsave_features =3D env->features[FEAT_XSAVE];
dc->jmp_opt =3D !((cflags & CF_NO_GOTO_TB) ||
(flags & (HF_RF_MASK | HF_TF_MASK | HF_INHIBIT_IRQ_MAS=
K)));
- /*
- * If jmp_opt, we want to handle each string instruction individually.
- * For icount also disable repz optimization so that each iteration
- * is accounted separately.
- *
- * FIXME: this is messy; it makes REP string instructions a lot less
- * efficient than they should be and it gets in the way of correct
- * handling of RF (interrupts or traps arriving after any iteration
- * of a repeated string instruction but the last should set RF to 1).
- * Perhaps it would be more efficient if REP string instructions were
- * always at the beginning of the TB, or even their own TB? That
- * would even allow accounting up to 64k iterations at once for icount.
- */
- dc->repz_opt =3D !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
=20
dc->T0 =3D tcg_temp_new();
dc->T1 =3D tcg_temp_new();
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 07/48] target/i386: tcg: move gen_set/reset_* earlier in the
file
Date: Fri, 24 Jan 2025 10:44:01 +0100
Message-ID: <20250124094442.13207-8-pbonzini@redhat.com>
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Allow using them in the code that translates REP/REPZ, without
forward declarations.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-7-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 80 ++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index ee536234398..6347de446a4 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -725,6 +725,46 @@ static inline void gen_op_jnz_ecx(DisasContext *s, TCG=
Label *label1)
gen_op_j_ecx(s, TCG_COND_NE, label1);
}
=20
+static void gen_set_hflag(DisasContext *s, uint32_t mask)
+{
+ if ((s->flags & mask) =3D=3D 0) {
+ TCGv_i32 t =3D tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags));
+ tcg_gen_ori_i32(t, t, mask);
+ tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags));
+ s->flags |=3D mask;
+ }
+}
+
+static void gen_reset_hflag(DisasContext *s, uint32_t mask)
+{
+ if (s->flags & mask) {
+ TCGv_i32 t =3D tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags));
+ tcg_gen_andi_i32(t, t, ~mask);
+ tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags));
+ s->flags &=3D ~mask;
+ }
+}
+
+static void gen_set_eflags(DisasContext *s, target_ulong mask)
+{
+ TCGv t =3D tcg_temp_new();
+
+ tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags));
+ tcg_gen_ori_tl(t, t, mask);
+ tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags));
+}
+
+static void gen_reset_eflags(DisasContext *s, target_ulong mask)
+{
+ TCGv t =3D tcg_temp_new();
+
+ tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags));
+ tcg_gen_andi_tl(t, t, ~mask);
+ tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags));
+}
+
static void gen_helper_in_func(MemOp ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
@@ -2084,46 +2124,6 @@ static void gen_interrupt(DisasContext *s, uint8_t i=
ntno)
s->base.is_jmp =3D DISAS_NORETURN;
}
=20
-static void gen_set_hflag(DisasContext *s, uint32_t mask)
-{
- if ((s->flags & mask) =3D=3D 0) {
- TCGv_i32 t =3D tcg_temp_new_i32();
- tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags));
- tcg_gen_ori_i32(t, t, mask);
- tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags));
- s->flags |=3D mask;
- }
-}
-
-static void gen_reset_hflag(DisasContext *s, uint32_t mask)
-{
- if (s->flags & mask) {
- TCGv_i32 t =3D tcg_temp_new_i32();
- tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags));
- tcg_gen_andi_i32(t, t, ~mask);
- tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags));
- s->flags &=3D ~mask;
- }
-}
-
-static void gen_set_eflags(DisasContext *s, target_ulong mask)
-{
- TCGv t =3D tcg_temp_new();
-
- tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags));
- tcg_gen_ori_tl(t, t, mask);
- tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags));
-}
-
-static void gen_reset_eflags(DisasContext *s, target_ulong mask)
-{
- TCGv t =3D tcg_temp_new();
-
- tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags));
- tcg_gen_andi_tl(t, t, ~mask);
- tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags));
-}
-
/* Clear BND registers during legacy branches. */
static void gen_bnd_jmp(DisasContext *s)
{
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 08/48] target/i386: fix RF handling for string instructions
Date: Fri, 24 Jan 2025 10:44:02 +0100
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RF must be set on traps and interrupts from a string instruction,
except if they occur after the last iteration. Ensure it is set
before giving the main loop a chance to execute.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-8-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 6347de446a4..141295742ae 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1337,6 +1337,14 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
bool is_repz_nz)
{
TCGLabel *done =3D gen_new_label();
+ bool had_rf =3D s->flags & HF_RF_MASK;
+
+ /*
+ * Even if EFLAGS.RF was set on entry (such as if we're on the second =
or
+ * later iteration and an exception or interrupt happened), force gen_=
eob()
+ * not to clear the flag. We do that ourselves after the last iterati=
on.
+ */
+ s->flags &=3D ~HF_RF_MASK;
=20
gen_update_cc_op(s);
gen_op_jz_ecx(s, done);
@@ -1348,12 +1356,24 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
gen_jcc(s, (JCC_Z << 1) | (nz ^ 1), done);
}
=20
+ /*
+ * Traps or interrupts set RF_MASK if they happen after any iteration
+ * but the last. Set it here before giving the main loop a chance to
+ * execute. (For faults, seg_helper.c sets the flag as usual).
+ */
+ if (!had_rf) {
+ gen_set_eflags(s, RF_MASK);
+ }
+
/* Go to the main loop but reenter the same instruction. */
gen_jmp_rel_csize(s, -cur_insn_len(s), 0);
=20
/* CX/ECX/RCX is zero, or REPZ/REPNZ broke the repetition. */
gen_set_label(done);
set_cc_op(s, CC_OP_DYNAMIC);
+ if (had_rf) {
+ gen_reset_eflags(s, RF_MASK);
+ }
gen_jmp_rel_csize(s, 0, 1);
}
=20
@@ -2158,7 +2178,7 @@ gen_eob(DisasContext *s, int mode)
gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
}
=20
- if (s->base.tb->flags & HF_RF_MASK) {
+ if (s->flags & HF_RF_MASK) {
gen_reset_eflags(s, RF_MASK);
}
if (mode =3D=3D DISAS_EOB_RECHECK_TF) {
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 09/48] target/i386: make cc_op handling more explicit for
repeated string instructions.
Date: Fri, 24 Jan 2025 10:44:03 +0100
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Since the cost of gen_update_cc_op() must be paid anyway, it's easier
to place them manually and not rely on spilling that is buried under
multiple levels of function calls. While at it, clarify the circumstances
in which the gen_update_cc_op() is needed, and why it is not for REPxx
SCAS and REPxx CMPS.
And since cc_op will have been spilled at the point of a fault, just
make the whole insn CC_OP_DYNAMIC. Once repz_opt is reintroduced,
a fault could happen either before or after the first execution of
CMPS/SCAS, and CC_OP_DYNAMIC sidesteps the complicated matter of what
x86_restore_state_to_opc would do.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Link: https://lore.kernel.org/r/20241215090613.89588-9-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 141295742ae..8bc91c3de31 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1234,8 +1234,9 @@ static inline void gen_jcc(DisasContext *s, int b, TC=
GLabel *l1)
CCPrepare cc =3D gen_prepare_cc(s, b, NULL);
=20
/*
- * Note that this must be _after_ gen_prepare_cc, because it
- * can change the cc_op from CC_OP_DYNAMIC to CC_OP_EFLAGS!
+ * Note that this must be _after_ gen_prepare_cc, because it can change
+ * the cc_op to CC_OP_EFLAGS (because it's CC_OP_DYNAMIC or because
+ * it's cheaper to just compute the flags)!
*/
gen_update_cc_op(s);
if (cc.use_reg2) {
@@ -1346,14 +1347,31 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
*/
s->flags &=3D ~HF_RF_MASK;
=20
+ /*
+ * For CMPS/SCAS, the CC_OP after a memory fault could come from either
+ * the previous instruction or the string instruction; but because we
+ * arrange to keep CC_OP up to date all the time, just mark the whole
+ * insn as CC_OP_DYNAMIC.
+ *
+ * It's not a problem to do this even for instructions that do not
+ * modify the flags, so do it unconditionally.
+ */
gen_update_cc_op(s);
+ tcg_set_insn_start_param(s->base.insn_start, 1, CC_OP_DYNAMIC);
+
+ /* Any iteration at all? */
gen_op_jz_ecx(s, done);
=20
fn(s, ot);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
+ gen_update_cc_op(s);
+
+ /* Leave if REP condition fails. */
if (is_repz_nz) {
int nz =3D (s->prefix & PREFIX_REPNZ) ? 1 : 0;
- gen_jcc(s, (JCC_Z << 1) | (nz ^ 1), done);
+ gen_jcc_noeob(s, (JCC_Z << 1) | (nz ^ 1), done);
+ /* gen_prepare_eflags_z never changes cc_op. */
+ assert(!s->cc_op_dirty);
}
=20
/*
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 10/48] target/i386: do not use gen_op_jz_ecx for repeated
string operations
Date: Fri, 24 Jan 2025 10:44:04 +0100
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Explicitly generate a TSTEQ branch (which is optimized to NE x,0 if possibl=
e).
This does not make much sense yet, but later we will add more checks and so=
me
will use a temporary to check on the decremented value of CX/ECX/RCX; it wi=
ll
be clearer for all checks to share the same logic using TSTEQ(reg, cx_mask).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-10-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 8bc91c3de31..7a3caf8b996 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1338,6 +1338,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
bool is_repz_nz)
{
TCGLabel *done =3D gen_new_label();
+ target_ulong cx_mask =3D MAKE_64BIT_MASK(0, 8 << s->aflag);
bool had_rf =3D s->flags & HF_RF_MASK;
=20
/*
@@ -1360,7 +1361,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
tcg_set_insn_start_param(s->base.insn_start, 1, CC_OP_DYNAMIC);
=20
/* Any iteration at all? */
- gen_op_jz_ecx(s, done);
+ tcg_gen_brcondi_tl(TCG_COND_TSTEQ, cpu_regs[R_ECX], cx_mask, done);
=20
fn(s, ot);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 11/48] target/i386: optimize CX handling in repeated string
operations
Date: Fri, 24 Jan 2025 10:44:05 +0100
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In a repeated string operation, CX/ECX will be decremented until it
is 0 but never underflow. Use this observation to avoid a deposit or
zero-extend operation if the address size of the operation is smaller
than MO_TL.
As in the previous patch, the patch is structured to include some
preparatory work for subsequent changes. In particular, introducing
cx_next prepares for when ECX will be decremented *before* calling
fn(s, ot), and therefore cannot yet be written back to cpu_regs.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-11-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 7a3caf8b996..0a8f3c89514 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1339,6 +1339,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
{
TCGLabel *done =3D gen_new_label();
target_ulong cx_mask =3D MAKE_64BIT_MASK(0, 8 << s->aflag);
+ TCGv cx_next =3D tcg_temp_new();
bool had_rf =3D s->flags & HF_RF_MASK;
=20
/*
@@ -1364,7 +1365,19 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
tcg_gen_brcondi_tl(TCG_COND_TSTEQ, cpu_regs[R_ECX], cx_mask, done);
=20
fn(s, ot);
- gen_op_add_reg_im(s, s->aflag, R_ECX, -1);
+
+ tcg_gen_subi_tl(cx_next, cpu_regs[R_ECX], 1);
+
+ /*
+ * Write back cx_next to CX/ECX/RCX. There can be no carry, so zero
+ * extend if needed but do not do expensive deposit operations.
+ */
+#ifdef TARGET_X86_64
+ if (s->aflag =3D=3D MO_32) {
+ tcg_gen_ext32u_tl(cx_next, cx_next);
+ }
+#endif
+ tcg_gen_mov_tl(cpu_regs[R_ECX], cx_next);
gen_update_cc_op(s);
=20
/* Leave if REP condition fails. */
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 12/48] target/i386: execute multiple REP/REPZ iterations
without leaving TB
Date: Fri, 24 Jan 2025 10:44:06 +0100
Message-ID: <20250124094442.13207-13-pbonzini@redhat.com>
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Use a TCG loop so that it is not necessary to go through the setup steps
of REP and through the I/O check on every iteration. Interestingly, this
is not a particularly effective optimization on its own, though it avoids
the cost of correct RF emulation that was added in the previous patch.
The main benefit lies in allowing the hoisting of loop invariants outside
the loop, which will happen separately.
The loop exits when the low 16 bits of CX/ECX/RCX are zero (so generally
speaking the string operation runs in 65536 iteration batches) to give
the main loop an opportunity to pick up interrupts.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-12-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 55 +++++++++++++++++++++++++++++++++----
1 file changed, 49 insertions(+), 6 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 0a8f3c89514..991baf5d829 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -1333,13 +1333,28 @@ static void gen_outs(DisasContext *s, MemOp ot)
gen_bpt_io(s, s->tmp2_i32, ot);
}
=20
+#define REP_MAX 65535
+
static void do_gen_rep(DisasContext *s, MemOp ot,
void (*fn)(DisasContext *s, MemOp ot),
bool is_repz_nz)
{
+ TCGLabel *last =3D gen_new_label();
+ TCGLabel *loop =3D gen_new_label();
TCGLabel *done =3D gen_new_label();
+
target_ulong cx_mask =3D MAKE_64BIT_MASK(0, 8 << s->aflag);
TCGv cx_next =3D tcg_temp_new();
+
+ /*
+ * Check if we must translate a single iteration only. Normally, HF_R=
F_MASK
+ * would also limit translation blocks to one instruction, so that gen=
_eob
+ * can reset the flag; here however RF is set throughout the repetitio=
n, so
+ * we can plow through until CX/ECX/RCX is zero.
+ */
+ bool can_loop =3D
+ (!(tb_cflags(s->base.tb) & (CF_USE_ICOUNT | CF_SINGLE_STEP))
+ && !(s->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
bool had_rf =3D s->flags & HF_RF_MASK;
=20
/*
@@ -1364,19 +1379,29 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
/* Any iteration at all? */
tcg_gen_brcondi_tl(TCG_COND_TSTEQ, cpu_regs[R_ECX], cx_mask, done);
=20
- fn(s, ot);
-
- tcg_gen_subi_tl(cx_next, cpu_regs[R_ECX], 1);
-
/*
- * Write back cx_next to CX/ECX/RCX. There can be no carry, so zero
- * extend if needed but do not do expensive deposit operations.
+ * From now on we operate on the value of CX/ECX/RCX that will be writ=
ten
+ * back, which is stored in cx_next. There can be no carry, so we can=
zero
+ * extend here if needed and not do any expensive deposit operations l=
ater.
*/
+ tcg_gen_subi_tl(cx_next, cpu_regs[R_ECX], 1);
#ifdef TARGET_X86_64
if (s->aflag =3D=3D MO_32) {
tcg_gen_ext32u_tl(cx_next, cx_next);
+ cx_mask =3D ~0;
}
#endif
+
+ /*
+ * The last iteration is handled outside the loop, so that cx_next
+ * can never underflow.
+ */
+ if (can_loop) {
+ tcg_gen_brcondi_tl(TCG_COND_TSTEQ, cx_next, cx_mask, last);
+ }
+
+ gen_set_label(loop);
+ fn(s, ot);
tcg_gen_mov_tl(cpu_regs[R_ECX], cx_next);
gen_update_cc_op(s);
=20
@@ -1388,6 +1413,12 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
assert(!s->cc_op_dirty);
}
=20
+ if (can_loop) {
+ tcg_gen_subi_tl(cx_next, cx_next, 1);
+ tcg_gen_brcondi_tl(TCG_COND_TSTNE, cx_next, REP_MAX, loop);
+ tcg_gen_brcondi_tl(TCG_COND_TSTEQ, cx_next, cx_mask, last);
+ }
+
/*
* Traps or interrupts set RF_MASK if they happen after any iteration
* but the last. Set it here before giving the main loop a chance to
@@ -1400,6 +1431,18 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
/* Go to the main loop but reenter the same instruction. */
gen_jmp_rel_csize(s, -cur_insn_len(s), 0);
=20
+ if (can_loop) {
+ /*
+ * The last iteration needs no conditional jump, even if is_repz_n=
z,
+ * because the repeats are ending anyway.
+ */
+ gen_set_label(last);
+ set_cc_op(s, CC_OP_DYNAMIC);
+ fn(s, ot);
+ tcg_gen_mov_tl(cpu_regs[R_ECX], cx_next);
+ gen_update_cc_op(s);
+ }
+
/* CX/ECX/RCX is zero, or REPZ/REPNZ broke the repetition. */
gen_set_label(done);
set_cc_op(s, CC_OP_DYNAMIC);
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 13/48] target/i386: pull computation of string update value out
of loop
Date: Fri, 24 Jan 2025 10:44:07 +0100
Message-ID: <20250124094442.13207-14-pbonzini@redhat.com>
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This is a common operation that is executed many times in rep
movs or rep stos loops. It can improve performance by several
percentage points.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Link: https://lore.kernel.org/r/20241215090613.89588-13-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 54 ++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 991baf5d829..9f4d3ebbd95 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -832,16 +832,13 @@ static bool gen_check_io(DisasContext *s, MemOp ot, T=
CGv_i32 port,
#endif
}
=20
-static void gen_movs(DisasContext *s, MemOp ot)
+static void gen_movs(DisasContext *s, MemOp ot, TCGv dshift)
{
- TCGv dshift;
-
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, s->T0, s->A0);
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, s->T0, s->A0);
=20
- dshift =3D gen_compute_Dshift(s, ot);
gen_op_add_reg(s, s->aflag, R_ESI, dshift);
gen_op_add_reg(s, s->aflag, R_EDI, dshift);
}
@@ -1246,22 +1243,22 @@ static inline void gen_jcc(DisasContext *s, int b, =
TCGLabel *l1)
}
}
=20
-static void gen_stos(DisasContext *s, MemOp ot)
+static void gen_stos(DisasContext *s, MemOp ot, TCGv dshift)
{
gen_string_movl_A0_EDI(s);
gen_op_st_v(s, ot, s->T0, s->A0);
- gen_op_add_reg(s, s->aflag, R_EDI, gen_compute_Dshift(s, ot));
+ gen_op_add_reg(s, s->aflag, R_EDI, dshift);
}
=20
-static void gen_lods(DisasContext *s, MemOp ot)
+static void gen_lods(DisasContext *s, MemOp ot, TCGv dshift)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, s->T0, s->A0);
gen_op_mov_reg_v(s, ot, R_EAX, s->T0);
- gen_op_add_reg(s, s->aflag, R_ESI, gen_compute_Dshift(s, ot));
+ gen_op_add_reg(s, s->aflag, R_ESI, dshift);
}
=20
-static void gen_scas(DisasContext *s, MemOp ot)
+static void gen_scas(DisasContext *s, MemOp ot, TCGv dshift)
{
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, s->T1, s->A0);
@@ -1270,13 +1267,11 @@ static void gen_scas(DisasContext *s, MemOp ot)
tcg_gen_sub_tl(cpu_cc_dst, s->T0, s->T1);
set_cc_op(s, CC_OP_SUBB + ot);
=20
- gen_op_add_reg(s, s->aflag, R_EDI, gen_compute_Dshift(s, ot));
+ gen_op_add_reg(s, s->aflag, R_EDI, dshift);
}
=20
-static void gen_cmps(DisasContext *s, MemOp ot)
+static void gen_cmps(DisasContext *s, MemOp ot, TCGv dshift)
{
- TCGv dshift;
-
gen_string_movl_A0_EDI(s);
gen_op_ld_v(s, ot, s->T1, s->A0);
gen_string_movl_A0_ESI(s);
@@ -1286,7 +1281,6 @@ static void gen_cmps(DisasContext *s, MemOp ot)
tcg_gen_sub_tl(cpu_cc_dst, s->T0, s->T1);
set_cc_op(s, CC_OP_SUBB + ot);
=20
- dshift =3D gen_compute_Dshift(s, ot);
gen_op_add_reg(s, s->aflag, R_ESI, dshift);
gen_op_add_reg(s, s->aflag, R_EDI, dshift);
}
@@ -1305,7 +1299,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po=
rt, int ot)
}
}
=20
-static void gen_ins(DisasContext *s, MemOp ot)
+static void gen_ins(DisasContext *s, MemOp ot, TCGv dshift)
{
gen_string_movl_A0_EDI(s);
/* Note: we must do this dummy write first to be restartable in
@@ -1316,11 +1310,11 @@ static void gen_ins(DisasContext *s, MemOp ot)
tcg_gen_andi_i32(s->tmp2_i32, s->tmp2_i32, 0xffff);
gen_helper_in_func(ot, s->T0, s->tmp2_i32);
gen_op_st_v(s, ot, s->T0, s->A0);
- gen_op_add_reg(s, s->aflag, R_EDI, gen_compute_Dshift(s, ot));
+ gen_op_add_reg(s, s->aflag, R_EDI, dshift);
gen_bpt_io(s, s->tmp2_i32, ot);
}
=20
-static void gen_outs(DisasContext *s, MemOp ot)
+static void gen_outs(DisasContext *s, MemOp ot, TCGv dshift)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, s->T0, s->A0);
@@ -1329,14 +1323,14 @@ static void gen_outs(DisasContext *s, MemOp ot)
tcg_gen_andi_i32(s->tmp2_i32, s->tmp2_i32, 0xffff);
tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T0);
gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32);
- gen_op_add_reg(s, s->aflag, R_ESI, gen_compute_Dshift(s, ot));
+ gen_op_add_reg(s, s->aflag, R_ESI, dshift);
gen_bpt_io(s, s->tmp2_i32, ot);
}
=20
#define REP_MAX 65535
=20
-static void do_gen_rep(DisasContext *s, MemOp ot,
- void (*fn)(DisasContext *s, MemOp ot),
+static void do_gen_rep(DisasContext *s, MemOp ot, TCGv dshift,
+ void (*fn)(DisasContext *s, MemOp ot, TCGv dshift),
bool is_repz_nz)
{
TCGLabel *last =3D gen_new_label();
@@ -1401,7 +1395,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
}
=20
gen_set_label(loop);
- fn(s, ot);
+ fn(s, ot, dshift);
tcg_gen_mov_tl(cpu_regs[R_ECX], cx_next);
gen_update_cc_op(s);
=20
@@ -1438,7 +1432,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
*/
gen_set_label(last);
set_cc_op(s, CC_OP_DYNAMIC);
- fn(s, ot);
+ fn(s, ot, dshift);
tcg_gen_mov_tl(cpu_regs[R_ECX], cx_next);
gen_update_cc_op(s);
}
@@ -1453,23 +1447,27 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
}
=20
static void gen_repz(DisasContext *s, MemOp ot,
- void (*fn)(DisasContext *s, MemOp ot))
+ void (*fn)(DisasContext *s, MemOp ot, TCGv dshift))
=20
{
+ TCGv dshift =3D gen_compute_Dshift(s, ot);
+
if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- do_gen_rep(s, ot, fn, false);
+ do_gen_rep(s, ot, dshift, fn, false);
} else {
- fn(s, ot);
+ fn(s, ot, dshift);
}
}
=20
static void gen_repz_nz(DisasContext *s, MemOp ot,
- void (*fn)(DisasContext *s, MemOp ot))
+ void (*fn)(DisasContext *s, MemOp ot, TCGv dshift))
{
+ TCGv dshift =3D gen_compute_Dshift(s, ot);
+
if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- do_gen_rep(s, ot, fn, true);
+ do_gen_rep(s, ot, dshift, fn, true);
} else {
- fn(s, ot);
+ fn(s, ot, dshift);
}
}
=20
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 14/48] target/i386: extract common bits of gen_repz/gen_repz_nz
Date: Fri, 24 Jan 2025 10:44:08 +0100
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Now that everything has been cleaned up, look at DF and prefixes
in a single function, and call that one from gen_repz and gen_repz_nz.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 34 ++++++++++++++--------------------
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9f4d3ebbd95..9b2fde5eb28 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -688,14 +688,6 @@ static inline void gen_string_movl_A0_EDI(DisasContext=
*s)
gen_lea_v_seg(s, cpu_regs[R_EDI], R_ES, -1);
}
=20
-static inline TCGv gen_compute_Dshift(DisasContext *s, MemOp ot)
-{
- TCGv dshift =3D tcg_temp_new();
- tcg_gen_ld32s_tl(dshift, tcg_env, offsetof(CPUX86State, df));
- tcg_gen_shli_tl(dshift, dshift, ot);
- return dshift;
-};
-
static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign)
{
if (size =3D=3D MO_TL) {
@@ -1446,29 +1438,31 @@ static void do_gen_rep(DisasContext *s, MemOp ot, T=
CGv dshift,
gen_jmp_rel_csize(s, 0, 1);
}
=20
-static void gen_repz(DisasContext *s, MemOp ot,
- void (*fn)(DisasContext *s, MemOp ot, TCGv dshift))
-
+static void do_gen_string(DisasContext *s, MemOp ot,
+ void (*fn)(DisasContext *s, MemOp ot, TCGv dshif=
t),
+ bool is_repz_nz)
{
- TCGv dshift =3D gen_compute_Dshift(s, ot);
+ TCGv dshift =3D tcg_temp_new();
+ tcg_gen_ld32s_tl(dshift, tcg_env, offsetof(CPUX86State, df));
+ tcg_gen_shli_tl(dshift, dshift, ot);
=20
if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- do_gen_rep(s, ot, dshift, fn, false);
+ do_gen_rep(s, ot, dshift, fn, is_repz_nz);
} else {
fn(s, ot, dshift);
}
}
=20
+static void gen_repz(DisasContext *s, MemOp ot,
+ void (*fn)(DisasContext *s, MemOp ot, TCGv dshift))
+{
+ do_gen_string(s, ot, fn, false);
+}
+
static void gen_repz_nz(DisasContext *s, MemOp ot,
void (*fn)(DisasContext *s, MemOp ot, TCGv dshift))
{
- TCGv dshift =3D gen_compute_Dshift(s, ot);
-
- if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
- do_gen_rep(s, ot, dshift, fn, true);
- } else {
- fn(s, ot, dshift);
- }
+ do_gen_string(s, ot, fn, true);
}
=20
static void gen_helper_fp_arith_ST0_FT0(int op)
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 15/48] target/i386: avoid using s->tmp0 for add to implicit
registers
Date: Fri, 24 Jan 2025 10:44:09 +0100
Message-ID: <20250124094442.13207-16-pbonzini@redhat.com>
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For updates to implicit registers (RCX in LOOP instructions, RSI or RDI
in string instructions, or the stack pointer) do the add directly using
the registers (with no temporary) if 32-bit or 64-bit, or use a temporary
created for the occasion if 16-bit. This is more efficient and removes
move instructions for the MO_TL case.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-14-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 23 +++++++++++++++--------
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9b2fde5eb28..a8935f487aa 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -505,17 +505,24 @@ static inline void gen_op_jmp_v(DisasContext *s, TCGv=
dest)
s->pc_save =3D -1;
}
=20
+static inline void gen_op_add_reg(DisasContext *s, MemOp size, int reg, TC=
Gv val)
+{
+ /* Using cpu_regs[reg] does not work for xH registers. */
+ assert(size >=3D MO_16);
+ if (size =3D=3D MO_16) {
+ TCGv temp =3D tcg_temp_new();
+ tcg_gen_add_tl(temp, cpu_regs[reg], val);
+ gen_op_mov_reg_v(s, size, reg, temp);
+ } else {
+ tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], val);
+ tcg_gen_ext_tl(cpu_regs[reg], cpu_regs[reg], size);
+ }
+}
+
static inline
void gen_op_add_reg_im(DisasContext *s, MemOp size, int reg, int32_t val)
{
- tcg_gen_addi_tl(s->tmp0, cpu_regs[reg], val);
- gen_op_mov_reg_v(s, size, reg, s->tmp0);
-}
-
-static inline void gen_op_add_reg(DisasContext *s, MemOp size, int reg, TC=
Gv val)
-{
- tcg_gen_add_tl(s->tmp0, cpu_regs[reg], val);
- gen_op_mov_reg_v(s, size, reg, s->tmp0);
+ gen_op_add_reg(s, size, reg, tcg_constant_tl(val));
}
=20
static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Tao Su <tao1.su@linux.intel.com>
Subject: [PULL 16/48] target/i386: Introduce SierraForest-v2 model
Date: Fri, 24 Jan 2025 10:44:10 +0100
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From: Tao Su <tao1.su@linux.intel.com>
Update SierraForest CPU model to add LAM, 4 bits indicating certain bits
of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl,
bhi-ctrl) and the missing features(ss, tsc-adjust, cldemote, movdiri,
movdir64b)
Also add GDS-NO and RFDS-NO to indicate the related vulnerabilities are
mitigated in stepping 3.
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121020650.1899618-2-tao1.su@linux.inte=
l.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1b9c11022c4..6db8d6c9bab 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4549,6 +4549,25 @@ static const X86CPUDefinition builtin_x86_defs[] =3D=
{
.model_id =3D "Intel Xeon Processor (SierraForest)",
.versions =3D (X86CPUVersionDefinition[]) {
{ .version =3D 1 },
+ {
+ .version =3D 2,
+ .props =3D (PropValue[]) {
+ { "ss", "on" },
+ { "tsc-adjust", "on" },
+ { "cldemote", "on" },
+ { "movdiri", "on" },
+ { "movdir64b", "on" },
+ { "gds-no", "on" },
+ { "rfds-no", "on" },
+ { "lam", "on" },
+ { "intel-psfd", "on"},
+ { "ipred-ctrl", "on"},
+ { "rrsba-ctrl", "on"},
+ { "bhi-ctrl", "on"},
+ { "stepping", "3" },
+ { /* end of list */ }
+ }
+ },
{ /* end of list */ },
},
},
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Tao Su <tao1.su@linux.intel.com>
Subject: [PULL 17/48] target/i386: Export BHI_NO bit to guests
Date: Fri, 24 Jan 2025 10:44:11 +0100
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From: Tao Su <tao1.su@linux.intel.com>
Branch History Injection (BHI) is a CPU side-channel vulnerability, where
an attacker may manipulate branch history before transitioning from user
to supervisor mode or from VMX non-root/guest to root mode. CPUs that set
BHI_NO bit in MSR IA32_ARCH_CAPABILITIES to indicate no additional
mitigation is required to prevent BHI.
Make BHI_NO bit available to guests.
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121020650.1899618-3-tao1.su@linux.inte=
l.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6db8d6c9bab..33fb27a6119 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1364,7 +1364,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D {
"taa-no", NULL, NULL, NULL,
NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
NULL, "fb-clear", NULL, NULL,
- NULL, NULL, NULL, NULL,
+ "bhi-no", NULL, NULL, NULL,
"pbrsb-no", NULL, "gds-no", "rfds-no",
"rfds-clear", NULL, NULL, NULL,
},
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Tao Su <tao1.su@linux.intel.com>
Subject: [PULL 18/48] target/i386: Add new CPU model ClearwaterForest
Date: Fri, 24 Jan 2025 10:44:12 +0100
Message-ID: <20250124094442.13207-19-pbonzini@redhat.com>
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From: Tao Su <tao1.su@linux.intel.com>
According to table 1-2 in Intel Architecture Instruction Set Extensions
and Future Features (rev 056) [1], ClearwaterForest has the following new
features which have already been virtualized:
- AVX-VNNI-INT16 CPUID.(EAX=3D7,ECX=3D1):EDX[bit 10]
- SHA512 CPUID.(EAX=3D7,ECX=3D1):EAX[bit 0]
- SM3 CPUID.(EAX=3D7,ECX=3D1):EAX[bit 1]
- SM4 CPUID.(EAX=3D7,ECX=3D1):EAX[bit 2]
Add above features to new CPU model ClearwaterForest. Comparing with
SierraForest, ClearwaterForest bare-metal contains all features of
SierraForest-v2 CPU model and adds:
- PREFETCHI CPUID.(EAX=3D7,ECX=3D1):EDX[bit 14]
- DDPD_U CPUID.(EAX=3D7,ECX=3D2):EDX[bit 3]
- BHI_NO IA32_ARCH_CAPABILITIES[bit 20]
Add above and all features of SierraForest-v2 CPU model to new CPU model
ClearwaterForest.
[1] https://cdrdv2.intel.com/v1/dl/getContent/671368
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121020650.1899618-4-tao1.su@linux.inte=
l.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.h | 33 +++++++++---
target/i386/cpu.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 162 insertions(+), 6 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b26e25ba15e..c67b42d34fc 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -951,6 +951,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cp=
u, FeatureWord w);
/* Speculative Store Bypass Disable */
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
=20
+/* SHA512 Instruction */
+#define CPUID_7_1_EAX_SHA512 (1U << 0)
+/* SM3 Instruction */
+#define CPUID_7_1_EAX_SM3 (1U << 1)
+/* SM4 Instruction */
+#define CPUID_7_1_EAX_SM4 (1U << 2)
/* AVX VNNI Instruction */
#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
/* AVX512 BFloat16 Instruction */
@@ -963,6 +969,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cp=
u, FeatureWord w);
#define CPUID_7_1_EAX_FSRS (1U << 11)
/* Fast Short REP CMPS/SCAS */
#define CPUID_7_1_EAX_FSRC (1U << 12)
+/* Flexible return and event delivery (FRED) */
+#define CPUID_7_1_EAX_FRED (1U << 17)
+/* Load into IA32_KERNEL_GS_BASE (LKGS) */
+#define CPUID_7_1_EAX_LKGS (1U << 18)
+/* Non-Serializing Write to Model Specific Register (WRMSRNS) */
+#define CPUID_7_1_EAX_WRMSRNS (1U << 19)
/* Support Tile Computational Operations on FP16 Numbers */
#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
/* Support for VPMADD52[H,L]UQ */
@@ -976,17 +988,23 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c=
pu, FeatureWord w);
#define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
/* AMX COMPLEX Instructions */
#define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
+/* AVX-VNNI-INT16 Instructions */
+#define CPUID_7_1_EDX_AVX_VNNI_INT16 (1U << 10)
/* PREFETCHIT0/1 Instructions */
#define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
/* Support for Advanced Vector Extensions 10 */
#define CPUID_7_1_EDX_AVX10 (1U << 19)
-/* Flexible return and event delivery (FRED) */
-#define CPUID_7_1_EAX_FRED (1U << 17)
-/* Load into IA32_KERNEL_GS_BASE (LKGS) */
-#define CPUID_7_1_EAX_LKGS (1U << 18)
-/* Non-Serializing Write to Model Specific Register (WRMSRNS) */
-#define CPUID_7_1_EAX_WRMSRNS (1U << 19)
=20
+/* Indicate bit 7 of the IA32_SPEC_CTRL MSR is supported */
+#define CPUID_7_2_EDX_PSFD (1U << 0)
+/* Indicate bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported */
+#define CPUID_7_2_EDX_IPRED_CTRL (1U << 1)
+/* Indicate bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported */
+#define CPUID_7_2_EDX_RRSBA_CTRL (1U << 2)
+/* Indicate bit 8 of the IA32_SPEC_CTRL MSR is supported */
+#define CPUID_7_2_EDX_DDPD_U (1U << 3)
+/* Indicate bit 10 of the IA32_SPEC_CTRL MSR is supported */
+#define CPUID_7_2_EDX_BHI_CTRL (1U << 4)
/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
=20
@@ -1144,7 +1162,10 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *=
cpu, FeatureWord w);
#define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
#define MSR_ARCH_CAP_PSDP_NO (1U << 15)
#define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
+#define MSR_ARCH_CAP_BHI_NO (1U << 20)
#define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
+#define MSR_ARCH_CAP_GDS_NO (1U << 26)
+#define MSR_ARCH_CAP_RFDS_NO (1U << 27)
=20
#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
=20
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 33fb27a6119..b5dd60d2812 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4571,6 +4571,141 @@ static const X86CPUDefinition builtin_x86_defs[] =
=3D {
{ /* end of list */ },
},
},
+ {
+ .name =3D "ClearwaterForest",
+ .level =3D 0x23,
+ .xlevel =3D 0x80000008,
+ .vendor =3D CPUID_VENDOR_INTEL,
+ .family =3D 6,
+ .model =3D 221,
+ .stepping =3D 0,
+ /*
+ * please keep the ascending order so that we can have a clear vie=
w of
+ * bit position of each feature.
+ */
+ .features[FEAT_1_EDX] =3D
+ CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FX=
SR |
+ CPUID_SSE | CPUID_SSE2 | CPUID_SS,
+ .features[FEAT_1_ECX] =3D
+ CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SS=
E41 |
+ CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+ CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AE=
S |
+ CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_R=
DRAND,
+ .features[FEAT_8000_0001_EDX] =3D
+ CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
+ CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
+ .features[FEAT_8000_0001_ECX] =3D
+ CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_8000_0008_EBX] =3D
+ CPUID_8000_0008_EBX_WBNOINVD,
+ .features[FEAT_7_0_EBX] =3D
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST |
+ CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI=
D |
+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
+ CPUID_7_0_EBX_SHA_NI,
+ .features[FEAT_7_0_ECX] =3D
+ CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI |
+ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
+ CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT |
+ CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI |
+ CPUID_7_0_ECX_MOVDIR64B,
+ .features[FEAT_7_0_EDX] =3D
+ CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
+ CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
+ CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+ .features[FEAT_ARCH_CAPABILITIES] =3D
+ MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
+ MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
+ MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO |
+ MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO |
+ MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO |
+ MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO,
+ .features[FEAT_XSAVE] =3D
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
+ .features[FEAT_6_EAX] =3D
+ CPUID_6_EAX_ARAT,
+ .features[FEAT_7_1_EAX] =3D
+ CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 |
+ CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD |
+ CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA |
+ CPUID_7_1_EAX_LAM,
+ .features[FEAT_7_1_EDX] =3D
+ CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT |
+ CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI,
+ .features[FEAT_7_2_EDX] =3D
+ CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL |
+ CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U |
+ CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO,
+ .features[FEAT_VMX_BASIC] =3D
+ MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+ .features[FEAT_VMX_ENTRY_CTLS] =3D
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+ VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+ .features[FEAT_VMX_EPT_VPID_CAPS] =3D
+ MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 |
+ MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+ MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CON=
TEXT |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
+ MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+ .features[FEAT_VMX_EXIT_CTLS] =3D
+ VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+ VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T=
IMER,
+ .features[FEAT_VMX_MISC] =3D
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+ MSR_VMX_MISC_VMWRITE_VMEXIT,
+ .features[FEAT_VMX_PINBASED_CTLS] =3D
+ VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+ VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIME=
R |
+ VMX_PIN_BASED_POSTED_INTR,
+ .features[FEAT_VMX_PROCBASED_CTLS] =3D
+ VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITI=
NG |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITI=
NG |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
+ VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING=
|
+ VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG=
|
+ VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
+ VMX_CPU_BASED_PAUSE_EXITING |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+ .features[FEAT_VMX_SECONDARY_CTLS] =3D
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+ VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+ VMX_SECONDARY_EXEC_RDTSCP |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXI=
TING |
+ VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING |
+ VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_V=
MCS |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_=
PML |
+ VMX_SECONDARY_EXEC_XSAVES,
+ .features[FEAT_VMX_VMFUNC] =3D
+ MSR_VMX_VMFUNC_EPT_SWITCHING,
+ .model_id =3D "Intel Xeon Processor (ClearwaterForest)",
+ .versions =3D (X86CPUVersionDefinition[]) {
+ { .version =3D 1 },
+ { /* end of list */ },
+ },
+ },
{
.name =3D "Denverton",
.level =3D 21,
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Tao Su <tao1.su@linux.intel.com>
Subject: [PULL 19/48] docs: Add GNR, SRF and CWF CPU models
Date: Fri, 24 Jan 2025 10:44:13 +0100
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From: Tao Su <tao1.su@linux.intel.com>
Update GraniteRapids, SierraForest and ClearwaterForest CPU models in
section "Preferred CPU models for Intel x86 hosts".
Also introduce bhi-no, gds-no and rfds-no in doc.
Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121020650.1899618-5-tao1.su@linux.inte=
l.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
docs/system/cpu-models-x86.rst.inc | 50 +++++++++++++++++++++++++++---
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x8=
6.rst.inc
index ba27b5683fb..6a770ca8351 100644
--- a/docs/system/cpu-models-x86.rst.inc
+++ b/docs/system/cpu-models-x86.rst.inc
@@ -71,6 +71,16 @@ mixture of host CPU models between machines, if live mig=
ration
compatibility is required, use the newest CPU model that is compatible
across all desired hosts.
=20
+``ClearwaterForest``
+ Intel Xeon Processor (ClearwaterForest, 2025)
+
+``SierraForest``, ``SierraForest-v2``
+ Intel Xeon Processor (SierraForest, 2024), SierraForest-v2 mitigates
+ the GDS and RFDS vulnerabilities with stepping 3.
+
+``GraniteRapids``, ``GraniteRapids-v2``
+ Intel Xeon Processor (GraniteRapids, 2024)
+
``Cascadelake-Server``, ``Cascadelake-Server-noTSX``
Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
or 7 only. (The Cascade Lake Xeon processor with *stepping 5 is
@@ -181,7 +191,7 @@ features are included if using "Host passthrough" or "H=
ost model".
CVE-2018-12127, [MSBDS] CVE-2018-12126).
=20
This is an MSR (Model-Specific Register) feature rather than a CPUID fea=
ture,
- so it will not appear in the Linux ``/proc/cpuinfo`` in the host or
+ therefore it will not appear in the Linux ``/proc/cpuinfo`` in the host =
or
guest. Instead, the host kernel uses it to populate the MDS
vulnerability file in ``sysfs``.
=20
@@ -189,10 +199,10 @@ features are included if using "Host passthrough" or =
"Host model".
affected} in the ``/sys/devices/system/cpu/vulnerabilities/mds`` file.
=20
``taa-no``
- Recommended to inform that the guest that the host is ``not``
+ Recommended to inform the guest that the host is ``not``
vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA).
=20
- This too is an MSR feature, so it does not show up in the Linux
+ This is also an MSR feature, therefore it does not show up in the Linux
``/proc/cpuinfo`` in the host or guest.
=20
It should only be enabled for VMs if the host reports ``Not affected``
@@ -214,7 +224,7 @@ features are included if using "Host passthrough" or "H=
ost model".
By disabling TSX, KVM-based guests can avoid paying the price of
mitigating TSX-based attacks.
=20
- Note that ``tsx-ctrl`` too is an MSR feature, so it does not show
+ Note that ``tsx-ctrl`` is also an MSR feature, therefore it does not show
up in the Linux ``/proc/cpuinfo`` in the host or guest.
=20
To validate that Intel TSX is indeed disabled for the guest, there are
@@ -223,6 +233,38 @@ features are included if using "Host passthrough" or "=
Host model".
``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` file in
the guest should report ``Mitigation: TSX disabled``.
=20
+``bhi-no``
+ Recommended to inform the guest that the host is ``not``
+ vulnerable to CVE-2022-0001, Branch History Injection (BHI).
+
+ This is also an MSR feature, therefore it does not show up in the Linux
+ ``/proc/cpuinfo`` in the host or guest.
+
+ It should only be enabled for VMs if the host reports
+ ``BHI: Not affected`` in the
+ ``/sys/devices/system/cpu/vulnerabilities/spectre_v2`` file.
+
+``gds-no``
+ Recommended to inform the guest that the host is ``not``
+ vulnerable to CVE-2022-40982, Gather Data Sampling (GDS).
+
+ This is also an MSR feature, therefore it does not show up in the Linux
+ ``/proc/cpuinfo`` in the host or guest.
+
+ It should only be enabled for VMs if the host reports ``Not affected``
+ in the ``/sys/devices/system/cpu/vulnerabilities/gather_data_sampling``
+ file.
+
+``rfds-no``
+ Recommended to inform the guest that the host is ``not``
+ vulnerable to CVE-2023-28746, Register File Data Sampling (RFDS).
+
+ This is also an MSR feature, therefore it does not show up in the Linux
+ ``/proc/cpuinfo`` in the host or guest.
+
+ It should only be enabled for VMs if the host reports ``Not affected``
+ in the ``/sys/devices/system/cpu/vulnerabilities/reg_file_data_sampling``
+ file.
=20
Preferred CPU models for AMD x86 hosts
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>,
qemu-stable@nongnu.org
Subject: [PULL 20/48] stub: Fix build failure with --enable-user
--disable-system --enable-tools
Date: Fri, 24 Jan 2025 10:44:14 +0100
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From: Zhao Liu <zhao1.liu@intel.com>
Configuring "--enable-user --disable-system --enable-tools" causes the
build failure with the following information:
/usr/bin/ld: libhwcore.a.p/hw_core_qdev.c.o: in function `device_finalize':
/qemu/build/../hw/core/qdev.c:688: undefined reference to `qapi_event_send_=
device_deleted'
collect2: error: ld returned 1 exit status
To fix the above issue, add qdev.c stub when build with `have_tools`.
With this fix, QEMU could be successfully built in the following cases:
--enable-user --disable-system --enable-tools
--enable-user --disable-system --disable-tools
--enable-user --disable-system
Cc: qemu-stable@nongnu.org
Fixes: 388b849fb6c3 ("stubs: avoid duplicate symbols in libqemuutil.a")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2766
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121154318.214680-1-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
stubs/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/stubs/meson.build b/stubs/meson.build
index e91614a874d..a8b3aeb5645 100644
--- a/stubs/meson.build
+++ b/stubs/meson.build
@@ -57,8 +57,8 @@ if have_user
stub_ss.add(files('cpu-synchronize-state.c'))
=20
# Stubs for QAPI events. Those can always be included in the build, but
- # they are not built at all for --disable-system --disable-tools builds.
- if not (have_system or have_tools)
+ # they are not built at all for --disable-system builds.
+ if not have_system
stub_ss.add(files('qdev.c'))
endif
endif
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 21/48] rust/qdev: Make REALIZE safe
Date: Fri, 24 Jan 2025 10:44:15 +0100
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From: Zhao Liu <zhao1.liu@intel.com>
A safe REALIZE accepts immutable reference.
Since current PL011's realize() only calls a char binding function (
qemu_chr_fe_set_handlers), it is possible to convert mutable reference
(&mut self) to immutable reference (&self), which only needs to convert
the pointers passed to C to mutable pointers.
Thus, make REALIZE accept immutable reference.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121140457.84631-2-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 10 +++++-----
rust/qemu-api/src/qdev.rs | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 65a1234b9ff..a0e0fbdd9dd 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -2,7 +2,7 @@
// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
// SPDX-License-Identifier: GPL-2.0-or-later
=20
-use core::ptr::{addr_of_mut, NonNull};
+use core::ptr::{addr_of, addr_of_mut, NonNull};
use std::{
ffi::CStr,
os::raw::{c_int, c_uint, c_void},
@@ -156,7 +156,7 @@ fn properties() -> &'static [Property] {
fn vmsd() -> Option<&'static VMStateDescription> {
Some(&device_class::VMSTATE_PL011)
}
- const REALIZE: Option<fn(&mut Self)> =3D Some(Self::realize);
+ const REALIZE: Option<fn(&Self)> =3D Some(Self::realize);
const RESET: Option<fn(&mut Self)> =3D Some(Self::reset);
}
=20
@@ -439,17 +439,17 @@ fn set_read_trigger(&mut self) {
self.read_trigger =3D 1;
}
=20
- pub fn realize(&mut self) {
+ pub fn realize(&self) {
// SAFETY: self.char_backend has the correct size and alignment fo=
r a
// CharBackend object, and its callbacks are of the correct types.
unsafe {
qemu_chr_fe_set_handlers(
- addr_of_mut!(self.char_backend),
+ addr_of!(self.char_backend) as *mut CharBackend,
Some(pl011_can_receive),
Some(pl011_receive),
Some(pl011_event),
None,
- addr_of_mut!(*self).cast::<c_void>(),
+ addr_of!(*self).cast::<c_void>() as *mut c_void,
core::ptr::null_mut(),
true,
);
diff --git a/rust/qemu-api/src/qdev.rs b/rust/qemu-api/src/qdev.rs
index 686054e737a..a5121e31a37 100644
--- a/rust/qemu-api/src/qdev.rs
+++ b/rust/qemu-api/src/qdev.rs
@@ -23,7 +23,7 @@ pub trait DeviceImpl {
///
/// If not `None`, the parent class's `realize` method is overridden
/// with the function pointed to by `REALIZE`.
- const REALIZE: Option<fn(&mut Self)> =3D None;
+ const REALIZE: Option<fn(&Self)> =3D None;
=20
/// If not `None`, the parent class's `reset` method is overridden
/// with the function pointed to by `RESET`.
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 22/48] rust/pl011: Avoid bindings::*
Date: Fri, 24 Jan 2025 10:44:16 +0100
Message-ID: <20250124094442.13207-23-pbonzini@redhat.com>
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From: Zhao Liu <zhao1.liu@intel.com>
List all the necessary bindings to better identify gaps in rust/qapi.
And include the bindings wrapped by rust/qapi instead mapping the raw
bindings directly.
Inspired-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121140457.84631-3-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index a0e0fbdd9dd..4f1080ff19f 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -9,12 +9,19 @@
};
=20
use qemu_api::{
- bindings::{self, *},
+ bindings::{
+ error_fatal, hwaddr, memory_region_init_io, qdev_init_clock_in, qd=
ev_new,
+ qdev_prop_set_chr, qemu_chr_fe_ioctl, qemu_chr_fe_set_handlers, qe=
mu_chr_fe_write_all,
+ qemu_irq, sysbus_connect_irq, sysbus_mmio_map, sysbus_realize_and_=
unref, CharBackend,
+ Chardev, Clock, ClockEvent, MemoryRegion, QEMUChrEvent, CHR_IOCTL_=
SERIAL_SET_BREAK,
+ },
c_str,
irq::InterruptSource,
prelude::*,
- qdev::DeviceImpl,
+ qdev::{DeviceImpl, DeviceState, Property},
qom::{ClassInitImpl, ObjectImpl, ParentField},
+ sysbus::{SysBusDevice, SysBusDeviceClass},
+ vmstate::VMStateDescription,
};
=20
use crate::{
@@ -494,7 +501,7 @@ pub fn can_receive(&self) -> bool {
}
=20
pub fn event(&mut self, event: QEMUChrEvent) {
- if event =3D=3D bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.l=
oopback_enabled() {
+ if event =3D=3D QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_en=
abled() {
self.put_fifo(registers::Data::BREAK.into());
}
}
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 23/48] memattrs: Convert unspecified member to bool
Date: Fri, 24 Jan 2025 10:44:17 +0100
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From: Zhao Liu <zhao1.liu@intel.com>
Convert `unspecified` member of MemTxAttrs from bit field to bool, so
that bindgen could generate more ergonomic Rust binding with bool type.
As a result, MemTxAttrs needs to be expanded from 4 bytes to 8 bytes.
Therefore, move `unspecified` to after the bit fields and add reserved
members to ensure that the whole structure is packed into 8 bytes.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121151322.171832-2-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
include/exec/memattrs.h | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index e27c18f3dc3..4fde4eee843 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -23,12 +23,6 @@
* different semantics.
*/
typedef struct MemTxAttrs {
- /* Bus masters which don't specify any attributes will get this
- * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
- * distinguish "all attributes deliberately clear" from
- * "didn't specify" if necessary.
- */
- unsigned int unspecified:1;
/*
* ARM/AMBA: TrustZone Secure access
* x86: System Management Mode access
@@ -57,6 +51,17 @@ typedef struct MemTxAttrs {
* PID (PCI PASID) support: Limited to 8 bits process identifier.
*/
unsigned int pid:8;
+
+ /*
+ * Bus masters which don't specify any attributes will get this
+ * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
+ * distinguish "all attributes deliberately clear" from
+ * "didn't specify" if necessary.
+ */
+ bool unspecified;
+
+ uint8_t _reserved1;
+ uint16_t _reserved2;
} MemTxAttrs;
=20
/* Bus masters which don't specify any attributes will get this,
@@ -64,7 +69,7 @@ typedef struct MemTxAttrs {
* (so that we can distinguish "all attributes deliberately clear"
* from "didn't specify" if necessary).
*/
-#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified =3D 1 })
+#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified =3D true })
=20
/* New-style MMIO accessors can indicate that the transaction failed.
* A zero (MEMTX_OK) response means success; anything else is a failure
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 24/48] memattrs: Check the size of MemTxAttrs
Date: Fri, 24 Jan 2025 10:44:18 +0100
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From: Zhao Liu <zhao1.liu@intel.com>
Make sure MemTxAttrs is packed into 8 bytes and does not exceed 8 bytes.
Suggested-by: Philippe Mathieu-Daud=C3=83 <philmd@linaro.org>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250121151322.171832-3-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
include/exec/memattrs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 4fde4eee843..060b7e71314 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -64,6 +64,8 @@ typedef struct MemTxAttrs {
uint16_t _reserved2;
} MemTxAttrs;
=20
+QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8);
+
/* Bus masters which don't specify any attributes will get this,
* which has all attribute bits clear except the topmost one
* (so that we can distinguish "all attributes deliberately clear"
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 25/48] rust: vmstate: add new type safe implementation
Date: Fri, 24 Jan 2025 10:44:19 +0100
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The existing translation of the C macros for vmstate does not make
any attempt to type-check vmstate declarations against the struct, so
introduce a new system that computes VMStateField based on the actual
struct declaration.
Macros do not have full access to the type system, therefore a full
implementation of this scheme requires a helper trait to analyze the
type and produce a VMStateField from it; a macro "vmstate_of!" accepts
arguments similar to "offset_of!" and tricks the compiler into looking
up the trait for the right type.
The patch introduces not just vmstate_of!, but also the slightly too
clever enabling macro call_func_with_field!. The particular trick used
here was proposed on the users.rust-lang.org forum, so I take no merit
and all the blame.
Introduce the trait and some functions to access it; the actual
implementation comes later.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/prelude.rs | 2 +
rust/qemu-api/src/vmstate.rs | 113 +++++++++++++++++++++++++++++++++--
2 files changed, 109 insertions(+), 6 deletions(-)
diff --git a/rust/qemu-api/src/prelude.rs b/rust/qemu-api/src/prelude.rs
index 4ea70b9c823..2dc86e19b29 100644
--- a/rust/qemu-api/src/prelude.rs
+++ b/rust/qemu-api/src/prelude.rs
@@ -18,3 +18,5 @@
pub use crate::qom_isa;
=20
pub use crate::sysbus::SysBusDeviceMethods;
+
+pub use crate::vmstate::VMState;
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 63c897abcdf..b839a7d6b7f 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -4,13 +4,114 @@
=20
//! Helper macros to declare migration state for device models.
//!
-//! Some macros are direct equivalents to the C macros declared in
-//! `include/migration/vmstate.h` while
-//! [`vmstate_subsections`](crate::vmstate_subsections) and
-//! [`vmstate_fields`](crate::vmstate_fields) are meant to be used when
-//! declaring a device model state struct.
+//! This module includes three families of macros:
+//!
+//! * [`vmstate_unused!`](crate::vmstate_unused) and
+//! [`vmstate_of!`](crate::vmstate_of), which are used to express the
+//! migration format for a struct. This is based on the [`VMState`] tra=
it,
+//! which is defined by all migrateable types.
+//!
+//! * helper macros to declare a device model state struct, in particular
+//! [`vmstate_subsections`](crate::vmstate_subsections) and
+//! [`vmstate_fields`](crate::vmstate_fields).
+//!
+//! * direct equivalents to the C macros declared in
+//! `include/migration/vmstate.h`. These are not type-safe and should no=
t be
+//! used if the equivalent functionality is available with `vmstate_of!`.
=20
-pub use crate::bindings::VMStateDescription;
+use core::marker::PhantomData;
+
+pub use crate::bindings::{VMStateDescription, VMStateField};
+
+/// This macro is used to call a function with a generic argument bound
+/// to the type of a field. The function must take a
+/// [`PhantomData`]`<T>` argument; `T` is the type of
+/// field `$field` in the `$typ` type.
+///
+/// # Examples
+///
+/// ```
+/// # use qemu_api::call_func_with_field;
+/// # use core::marker::PhantomData;
+/// const fn size_of_field<T>(_: PhantomData<T>) -> usize {
+/// std::mem::size_of::<T>()
+/// }
+///
+/// struct Foo {
+/// x: u16,
+/// };
+/// // calls size_of_field::<u16>()
+/// assert_eq!(call_func_with_field!(size_of_field, Foo, x), 2);
+/// ```
+#[macro_export]
+macro_rules! call_func_with_field {
+ // Based on the answer by user steffahn (Frank Steffahn) at
+ // https://users.rust-lang.org/t/inferring-type-of-field/122857
+ // and used under MIT license
+ ($func:expr, $typ:ty, $($field:tt).+) =3D> {
+ $func(loop {
+ #![allow(unreachable_code)]
+ const fn phantom__<T>(_: &T) -> ::core::marker::PhantomData<T>=
{ ::core::marker::PhantomData }
+ // Unreachable code is exempt from checks on uninitialized val=
ues.
+ // Use that trick to infer the type of this PhantomData.
+ break ::core::marker::PhantomData;
+ break phantom__(&{ let value__: $typ; value__.$($field).+ });
+ })
+ };
+}
+
+/// A trait for types that can be included in a device's migration stream.=
It
+/// provides the base contents of a `VMStateField` (minus the name and off=
set).
+///
+/// # Safety
+///
+/// The contents of this trait go straight into structs that are parsed by=
C
+/// code and used to introspect into other structs. Be careful.
+pub unsafe trait VMState {
+ /// The base contents of a `VMStateField` (minus the name and offset) =
for
+ /// the type that is implementing the trait.
+ const BASE: VMStateField;
+}
+
+/// Internal utility function to retrieve a type's `VMStateField`;
+/// used by [`vmstate_of!`](crate::vmstate_of).
+pub const fn vmstate_base<T: VMState>(_: PhantomData<T>) -> VMStateField {
+ T::BASE
+}
+
+/// Return the `VMStateField` for a field of a struct. The field must be
+/// visible in the current scope.
+///
+/// In order to support other types, the trait `VMState` must be implement=
ed
+/// for them.
+#[macro_export]
+macro_rules! vmstate_of {
+ ($struct_name:ty, $field_name:ident $(,)?) =3D> {
+ $crate::bindings::VMStateField {
+ name: ::core::concat!(::core::stringify!($field_name), "\0")
+ .as_bytes()
+ .as_ptr() as *const ::std::os::raw::c_char,
+ offset: $crate::offset_of!($struct_name, $field_name),
+ // Compute most of the VMStateField from the type of the field.
+ ..$crate::call_func_with_field!(
+ $crate::vmstate::vmstate_base,
+ $struct_name,
+ $field_name
+ )
+ }
+ };
+}
+
+// Add a couple builder-style methods to VMStateField, allowing
+// easy derivation of VMStateField constants from other types.
+impl VMStateField {
+ #[must_use]
+ pub const fn with_version_id(mut self, version_id: i32) -> Self {
+ assert!(version_id >=3D 0);
+ self.version_id =3D version_id;
+ self
+ }
+}
=20
#[doc(alias =3D "VMSTATE_UNUSED_BUFFER")]
#[macro_export]
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 26/48] rust: vmstate: implement VMState for non-leaf types
Date: Fri, 24 Jan 2025 10:44:20 +0100
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Arrays, pointers and cells use a VMStateField that is based on that
for the inner type. The implementation therefore delegates to the
VMState implementation of the inner type.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/vmstate.rs | 79 +++++++++++++++++++++++++++++++++++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index b839a7d6b7f..211c3d096b7 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -19,8 +19,9 @@
//! `include/migration/vmstate.h`. These are not type-safe and should no=
t be
//! used if the equivalent functionality is available with `vmstate_of!`.
=20
-use core::marker::PhantomData;
+use core::{marker::PhantomData, mem, ptr::NonNull};
=20
+use crate::bindings::VMStateFlags;
pub use crate::bindings::{VMStateDescription, VMStateField};
=20
/// This macro is used to call a function with a generic argument bound
@@ -102,6 +103,15 @@ macro_rules! vmstate_of {
};
}
=20
+impl VMStateFlags {
+ const VMS_VARRAY_FLAGS: VMStateFlags =3D VMStateFlags(
+ VMStateFlags::VMS_VARRAY_INT32.0
+ | VMStateFlags::VMS_VARRAY_UINT8.0
+ | VMStateFlags::VMS_VARRAY_UINT16.0
+ | VMStateFlags::VMS_VARRAY_UINT32.0,
+ );
+}
+
// Add a couple builder-style methods to VMStateField, allowing
// easy derivation of VMStateField constants from other types.
impl VMStateField {
@@ -111,6 +121,73 @@ pub const fn with_version_id(mut self, version_id: i32=
) -> Self {
self.version_id =3D version_id;
self
}
+
+ #[must_use]
+ pub const fn with_array_flag(mut self, num: usize) -> Self {
+ assert!(num <=3D 0x7FFF_FFFFusize);
+ assert!((self.flags.0 & VMStateFlags::VMS_ARRAY.0) =3D=3D 0);
+ assert!((self.flags.0 & VMStateFlags::VMS_VARRAY_FLAGS.0) =3D=3D 0=
);
+ if (self.flags.0 & VMStateFlags::VMS_POINTER.0) !=3D 0 {
+ self.flags =3D VMStateFlags(self.flags.0 & !VMStateFlags::VMS_=
POINTER.0);
+ self.flags =3D VMStateFlags(self.flags.0 | VMStateFlags::VMS_A=
RRAY_OF_POINTER.0);
+ }
+ self.flags =3D VMStateFlags(self.flags.0 & !VMStateFlags::VMS_SING=
LE.0);
+ self.flags =3D VMStateFlags(self.flags.0 | VMStateFlags::VMS_ARRAY=
.0);
+ self.num =3D num as i32;
+ self
+ }
+
+ #[must_use]
+ pub const fn with_pointer_flag(mut self) -> Self {
+ assert!((self.flags.0 & VMStateFlags::VMS_POINTER.0) =3D=3D 0);
+ self.flags =3D VMStateFlags(self.flags.0 | VMStateFlags::VMS_POINT=
ER.0);
+ self
+ }
+}
+
+// Transparent wrappers: just use the internal type
+
+macro_rules! impl_vmstate_transparent {
+ ($type:ty where $base:tt: VMState $($where:tt)*) =3D> {
+ unsafe impl<$base> VMState for $type where $base: VMState $($where=
)* {
+ const BASE: VMStateField =3D VMStateField {
+ size: mem::size_of::<$type>(),
+ ..<$base as VMState>::BASE
+ };
+ }
+ };
+}
+
+impl_vmstate_transparent!(std::cell::Cell<T> where T: VMState);
+impl_vmstate_transparent!(std::cell::UnsafeCell<T> where T: VMState);
+impl_vmstate_transparent!(crate::cell::BqlCell<T> where T: VMState);
+impl_vmstate_transparent!(crate::cell::BqlRefCell<T> where T: VMState);
+
+// Pointer types using the underlying type's VMState plus VMS_POINTER
+// Note that references are not supported, though references to cells
+// could be allowed.
+
+macro_rules! impl_vmstate_pointer {
+ ($type:ty where $base:tt: VMState $($where:tt)*) =3D> {
+ unsafe impl<$base> VMState for $type where $base: VMState $($where=
)* {
+ const BASE: VMStateField =3D <$base as VMState>::BASE.with_poi=
nter_flag();
+ }
+ };
+}
+
+impl_vmstate_pointer!(*const T where T: VMState);
+impl_vmstate_pointer!(*mut T where T: VMState);
+impl_vmstate_pointer!(NonNull<T> where T: VMState);
+
+// Unlike C pointers, Box is always non-null therefore there is no need
+// to specify VMS_ALLOC.
+impl_vmstate_pointer!(Box<T> where T: VMState);
+
+// Arrays using the underlying type's VMState plus
+// VMS_ARRAY/VMS_ARRAY_OF_POINTER
+
+unsafe impl<T: VMState, const N: usize> VMState for [T; N] {
+ const BASE: VMStateField =3D <T as VMState>::BASE.with_array_flag(N);
}
=20
#[doc(alias =3D "VMSTATE_UNUSED_BUFFER")]
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 27/48] rust: vmstate: add varray support to vmstate_of!
Date: Fri, 24 Jan 2025 10:44:21 +0100
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/vmstate.rs | 42 ++++++++++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 211c3d096b7..2b14d4839df 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -72,6 +72,15 @@ pub unsafe trait VMState {
/// The base contents of a `VMStateField` (minus the name and offset) =
for
/// the type that is implementing the trait.
const BASE: VMStateField;
+
+ /// A flag that is added to another field's `VMStateField` to specify =
the
+ /// length's type in a variable-sized array. If this is not a support=
ed
+ /// type for the length (i.e. if it is not `u8`, `u16`, `u32`), using =
it
+ /// in a call to [`vmstate_of!`](crate::vmstate_of) will cause a
+ /// compile-time error.
+ const VARRAY_FLAG: VMStateFlags =3D {
+ panic!("invalid type for variable-sized array");
+ };
}
=20
/// Internal utility function to retrieve a type's `VMStateField`;
@@ -80,6 +89,13 @@ pub const fn vmstate_base<T: VMState>(_: PhantomData<T>)=
-> VMStateField {
T::BASE
}
=20
+/// Internal utility function to retrieve a type's `VMStateFlags` when it
+/// is used as the element count of a `VMSTATE_VARRAY`; used by
+/// [`vmstate_of!`](crate::vmstate_of).
+pub const fn vmstate_varray_flag<T: VMState>(_: PhantomData<T>) -> VMState=
Flags {
+ T::VARRAY_FLAG
+}
+
/// Return the `VMStateField` for a field of a struct. The field must be
/// visible in the current scope.
///
@@ -87,18 +103,23 @@ pub const fn vmstate_base<T: VMState>(_: PhantomData<T=
>) -> VMStateField {
/// for them.
#[macro_export]
macro_rules! vmstate_of {
- ($struct_name:ty, $field_name:ident $(,)?) =3D> {
+ ($struct_name:ty, $field_name:ident $([0 .. $num:ident $(* $factor:exp=
r)?])? $(,)?) =3D> {
$crate::bindings::VMStateField {
name: ::core::concat!(::core::stringify!($field_name), "\0")
.as_bytes()
.as_ptr() as *const ::std::os::raw::c_char,
offset: $crate::offset_of!($struct_name, $field_name),
// Compute most of the VMStateField from the type of the field.
+ $(.num_offset: $crate::offset_of!($struct_name, $num),)?
..$crate::call_func_with_field!(
$crate::vmstate::vmstate_base,
$struct_name,
$field_name
- )
+ )$(.with_varray_flag($crate::call_func_with_field!(
+ $crate::vmstate::vmstate_varray_flag,
+ $struct_name,
+ $num))
+ $(.with_varray_multiply($factor))?)?
}
};
}
@@ -143,6 +164,22 @@ pub const fn with_pointer_flag(mut self) -> Self {
self.flags =3D VMStateFlags(self.flags.0 | VMStateFlags::VMS_POINT=
ER.0);
self
}
+
+ #[must_use]
+ pub const fn with_varray_flag<T: VMState>(mut self, flag: VMStateFlags=
) -> VMStateField {
+ assert!((self.flags.0 & VMStateFlags::VMS_ARRAY.0) !=3D 0);
+ self.flags =3D VMStateFlags(self.flags.0 & !VMStateFlags::VMS_ARRA=
Y.0);
+ self.flags =3D VMStateFlags(self.flags.0 | flag.0);
+ self
+ }
+
+ #[must_use]
+ pub const fn with_varray_multiply(mut self, num: u32) -> VMStateField {
+ assert!(num <=3D 0x7FFF_FFFFu32);
+ self.flags =3D VMStateFlags(self.flags.0 | VMStateFlags::VMS_MULTI=
PLY_ELEMENTS.0);
+ self.num =3D num as i32;
+ self
+ }
}
=20
// Transparent wrappers: just use the internal type
@@ -154,6 +191,7 @@ unsafe impl<$base> VMState for $type where $base: VMSta=
te $($where)* {
size: mem::size_of::<$type>(),
..<$base as VMState>::BASE
};
+ const VARRAY_FLAG: VMStateFlags =3D <$base as VMState>::VARRAY=
_FLAG;
}
};
}
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 28/48] rust: vmstate: implement Zeroable for VMStateField
Date: Fri, 24 Jan 2025 10:44:22 +0100
Message-ID: <20250124094442.13207-29-pbonzini@redhat.com>
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This shortens a bit the constants. Do not bother using it
in the vmstate macros since most of them will go away soon.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/vmstate.rs | 18 +++---------------
rust/qemu-api/src/zeroable.rs | 31 +++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 2b14d4839df..7652930affc 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -21,8 +21,8 @@
=20
use core::{marker::PhantomData, mem, ptr::NonNull};
=20
-use crate::bindings::VMStateFlags;
pub use crate::bindings::{VMStateDescription, VMStateField};
+use crate::bindings::VMStateFlags;
=20
/// This macro is used to call a function with a generic argument bound
/// to the type of a field. The function must take a
@@ -503,20 +503,8 @@ macro_rules! vmstate_fields {
static _FIELDS: &[$crate::bindings::VMStateField] =3D &[
$($field),*,
$crate::bindings::VMStateField {
- name: ::core::ptr::null(),
- err_hint: ::core::ptr::null(),
- offset: 0,
- size: 0,
- start: 0,
- num: 0,
- num_offset: 0,
- size_offset: 0,
- info: ::core::ptr::null(),
- flags: VMStateFlags::VMS_END,
- vmsd: ::core::ptr::null(),
- version_id: 0,
- struct_version_id: 0,
- field_exists: None,
+ flags: $crate::bindings::VMStateFlags::VMS_END,
+ ..$crate::zeroable::Zeroable::ZERO
}
];
_FIELDS.as_ptr()
diff --git a/rust/qemu-api/src/zeroable.rs b/rust/qemu-api/src/zeroable.rs
index 6125aeed8b4..57cac96de06 100644
--- a/rust/qemu-api/src/zeroable.rs
+++ b/rust/qemu-api/src/zeroable.rs
@@ -49,6 +49,37 @@ unsafe impl Zeroable for crate::bindings::Property {
};
}
=20
+// bindgen does not derive Default here
+#[allow(clippy::derivable_impls)]
+impl Default for crate::bindings::VMStateFlags {
+ fn default() -> Self {
+ Self(0)
+ }
+}
+
+unsafe impl Zeroable for crate::bindings::VMStateFlags {
+ const ZERO: Self =3D Self(0);
+}
+
+unsafe impl Zeroable for crate::bindings::VMStateField {
+ const ZERO: Self =3D Self {
+ name: ptr::null(),
+ err_hint: ptr::null(),
+ offset: 0,
+ size: 0,
+ start: 0,
+ num: 0,
+ num_offset: 0,
+ size_offset: 0,
+ info: ptr::null(),
+ flags: Zeroable::ZERO,
+ vmsd: ptr::null(),
+ version_id: 0,
+ struct_version_id: 0,
+ field_exists: None,
+ };
+}
+
unsafe impl Zeroable for crate::bindings::VMStateDescription {
const ZERO: Self =3D Self {
name: ptr::null(),
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 29/48] rust: vmstate: implement VMState for scalar types
Date: Fri, 24 Jan 2025 10:44:23 +0100
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Scalar types are those that have their own VMStateInfo. This poses
a problem in that references to VMStateInfo can only be included in
associated consts starting with Rust 1.83.0, when the const_refs_static
was stabilized. Removing the requirement is done by placing a limited
list of VMStateInfos in an enum, and going from enum to &VMStateInfo
only when building the VMStateField.
The same thing cannot be done with VMS_STRUCT because the set of
VMStateDescriptions extends to structs defined by the devices.
Therefore, structs and cells cannot yet use vmstate_of!.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/vmstate.rs | 128 ++++++++++++++++++++++++++++++++++-
1 file changed, 126 insertions(+), 2 deletions(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 7652930affc..a262c315da1 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -22,7 +22,10 @@
use core::{marker::PhantomData, mem, ptr::NonNull};
=20
pub use crate::bindings::{VMStateDescription, VMStateField};
-use crate::bindings::VMStateFlags;
+use crate::{
+ bindings::{self, VMStateFlags},
+ zeroable::Zeroable,
+};
=20
/// This macro is used to call a function with a generic argument bound
/// to the type of a field. The function must take a
@@ -61,6 +64,70 @@ const fn phantom__<T>(_: &T) -> ::core::marker::PhantomD=
ata<T> { ::core::marker:
};
}
=20
+/// Workaround for lack of `const_refs_static`: references to global varia=
bles
+/// can be included in a `static`, but not in a `const`; unfortunately, th=
is
+/// is exactly what would go in the `VMStateField`'s `info` member.
+///
+/// This enum contains the contents of the `VMStateField`'s `info` member,
+/// but as an `enum` instead of a pointer.
+#[allow(non_camel_case_types)]
+pub enum VMStateFieldType {
+ null,
+ vmstate_info_bool,
+ vmstate_info_int8,
+ vmstate_info_int16,
+ vmstate_info_int32,
+ vmstate_info_int64,
+ vmstate_info_uint8,
+ vmstate_info_uint16,
+ vmstate_info_uint32,
+ vmstate_info_uint64,
+ vmstate_info_timer,
+}
+
+/// Workaround for lack of `const_refs_static`. Converts a `VMStateFieldT=
ype`
+/// to a `*const VMStateInfo`, for inclusion in a `VMStateField`.
+#[macro_export]
+macro_rules! info_enum_to_ref {
+ ($e:expr) =3D> {
+ unsafe {
+ match $e {
+ $crate::vmstate::VMStateFieldType::null =3D> ::core::ptr::=
null(),
+ $crate::vmstate::VMStateFieldType::vmstate_info_bool =3D> {
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_b=
ool)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_int8 =3D> {
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_i=
nt8)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_int16 =3D>=
{
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_i=
nt16)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_int32 =3D>=
{
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_i=
nt32)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_int64 =3D>=
{
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_i=
nt64)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_uint8 =3D>=
{
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_u=
int8)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_uint16 =3D=
> {
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_u=
int16)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_uint32 =3D=
> {
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_u=
int32)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_uint64 =3D=
> {
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_u=
int64)
+ }
+ $crate::vmstate::VMStateFieldType::vmstate_info_timer =3D>=
{
+ ::core::ptr::addr_of!($crate::bindings::vmstate_info_t=
imer)
+ }
+ }
+ }
+ };
+}
+
/// A trait for types that can be included in a device's migration stream.=
It
/// provides the base contents of a `VMStateField` (minus the name and off=
set).
///
@@ -69,6 +136,12 @@ const fn phantom__<T>(_: &T) -> ::core::marker::Phantom=
Data<T> { ::core::marker:
/// The contents of this trait go straight into structs that are parsed by=
C
/// code and used to introspect into other structs. Be careful.
pub unsafe trait VMState {
+ /// The `info` member of a `VMStateField` is a pointer and as such can=
not
+ /// yet be included in the [`BASE`](VMState::BASE) associated constant;
+ /// this is only allowed by Rust 1.83.0 and newer. For now, include t=
he
+ /// member as an enum which is stored in a separate constant.
+ const SCALAR_TYPE: VMStateFieldType =3D VMStateFieldType::null;
+
/// The base contents of a `VMStateField` (minus the name and offset) =
for
/// the type that is implementing the trait.
const BASE: VMStateField;
@@ -83,6 +156,12 @@ pub unsafe trait VMState {
};
}
=20
+/// Internal utility function to retrieve a type's `VMStateFieldType`;
+/// used by [`vmstate_of!`](crate::vmstate_of).
+pub const fn vmstate_scalar_type<T: VMState>(_: PhantomData<T>) -> VMState=
FieldType {
+ T::SCALAR_TYPE
+}
+
/// Internal utility function to retrieve a type's `VMStateField`;
/// used by [`vmstate_of!`](crate::vmstate_of).
pub const fn vmstate_base<T: VMState>(_: PhantomData<T>) -> VMStateField {
@@ -99,6 +178,15 @@ pub const fn vmstate_varray_flag<T: VMState>(_: Phantom=
Data<T>) -> VMStateFlags
/// Return the `VMStateField` for a field of a struct. The field must be
/// visible in the current scope.
///
+/// Only a limited set of types is supported out of the box:
+/// * scalar types (integer and `bool`)
+/// * the C struct `QEMUTimer`
+/// * a transparent wrapper for any of the above (`Cell`, `UnsafeCell`,
+/// [`BqlCell`](crate::cell::BqlCell), [`BqlRefCell`](crate::cell::BqlRe=
fCell)
+/// * a raw pointer to any of the above
+/// * a `NonNull` pointer or a `Box` for any of the above
+/// * an array of any of the above
+///
/// In order to support other types, the trait `VMState` must be implement=
ed
/// for them.
#[macro_export]
@@ -109,8 +197,14 @@ macro_rules! vmstate_of {
.as_bytes()
.as_ptr() as *const ::std::os::raw::c_char,
offset: $crate::offset_of!($struct_name, $field_name),
- // Compute most of the VMStateField from the type of the field.
$(.num_offset: $crate::offset_of!($struct_name, $num),)?
+ // The calls to `call_func_with_field!` are the magic that
+ // computes most of the VMStateField from the type of the fiel=
d.
+ info: $crate::info_enum_to_ref!($crate::call_func_with_field!(
+ $crate::vmstate::vmstate_scalar_type,
+ $struct_name,
+ $field_name
+ )),
..$crate::call_func_with_field!(
$crate::vmstate::vmstate_base,
$struct_name,
@@ -187,6 +281,7 @@ pub const fn with_varray_multiply(mut self, num: u32) -=
> VMStateField {
macro_rules! impl_vmstate_transparent {
($type:ty where $base:tt: VMState $($where:tt)*) =3D> {
unsafe impl<$base> VMState for $type where $base: VMState $($where=
)* {
+ const SCALAR_TYPE: VMStateFieldType =3D <$base as VMState>::SC=
ALAR_TYPE;
const BASE: VMStateField =3D VMStateField {
size: mem::size_of::<$type>(),
..<$base as VMState>::BASE
@@ -201,6 +296,33 @@ unsafe impl<$base> VMState for $type where $base: VMSt=
ate $($where)* {
impl_vmstate_transparent!(crate::cell::BqlCell<T> where T: VMState);
impl_vmstate_transparent!(crate::cell::BqlRefCell<T> where T: VMState);
=20
+// Scalar types using predefined VMStateInfos
+
+macro_rules! impl_vmstate_scalar {
+ ($info:ident, $type:ty$(, $varray_flag:ident)?) =3D> {
+ unsafe impl VMState for $type {
+ const SCALAR_TYPE: VMStateFieldType =3D VMStateFieldType::$inf=
o;
+ const BASE: VMStateField =3D VMStateField {
+ size: mem::size_of::<$type>(),
+ flags: VMStateFlags::VMS_SINGLE,
+ ..Zeroable::ZERO
+ };
+ $(const VARRAY_FLAG: VMStateFlags =3D VMStateFlags::$varray_fl=
ag;)?
+ }
+ };
+}
+
+impl_vmstate_scalar!(vmstate_info_bool, bool);
+impl_vmstate_scalar!(vmstate_info_int8, i8);
+impl_vmstate_scalar!(vmstate_info_int16, i16);
+impl_vmstate_scalar!(vmstate_info_int32, i32);
+impl_vmstate_scalar!(vmstate_info_int64, i64);
+impl_vmstate_scalar!(vmstate_info_uint8, u8, VMS_VARRAY_UINT8);
+impl_vmstate_scalar!(vmstate_info_uint16, u16, VMS_VARRAY_UINT16);
+impl_vmstate_scalar!(vmstate_info_uint32, u32, VMS_VARRAY_UINT32);
+impl_vmstate_scalar!(vmstate_info_uint64, u64);
+impl_vmstate_scalar!(vmstate_info_timer, bindings::QEMUTimer);
+
// Pointer types using the underlying type's VMState plus VMS_POINTER
// Note that references are not supported, though references to cells
// could be allowed.
@@ -208,6 +330,7 @@ unsafe impl<$base> VMState for $type where $base: VMSta=
te $($where)* {
macro_rules! impl_vmstate_pointer {
($type:ty where $base:tt: VMState $($where:tt)*) =3D> {
unsafe impl<$base> VMState for $type where $base: VMState $($where=
)* {
+ const SCALAR_TYPE: VMStateFieldType =3D <T as VMState>::SCALAR=
_TYPE;
const BASE: VMStateField =3D <$base as VMState>::BASE.with_poi=
nter_flag();
}
};
@@ -225,6 +348,7 @@ unsafe impl<$base> VMState for $type where $base: VMSta=
te $($where)* {
// VMS_ARRAY/VMS_ARRAY_OF_POINTER
=20
unsafe impl<T: VMState, const N: usize> VMState for [T; N] {
+ const SCALAR_TYPE: VMStateFieldType =3D <T as VMState>::SCALAR_TYPE;
const BASE: VMStateField =3D <T as VMState>::BASE.with_array_flag(N);
}
=20
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 30/48] rust: vmstate: add public utility macros to implement
VMState
Date: Fri, 24 Jan 2025 10:44:24 +0100
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/vmstate.rs | 61 ++++++++++++++++++++++++++++++++++--
1 file changed, 58 insertions(+), 3 deletions(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index a262c315da1..9ac699b73b7 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -4,13 +4,18 @@
=20
//! Helper macros to declare migration state for device models.
//!
-//! This module includes three families of macros:
+//! This module includes four families of macros:
//!
//! * [`vmstate_unused!`](crate::vmstate_unused) and
//! [`vmstate_of!`](crate::vmstate_of), which are used to express the
//! migration format for a struct. This is based on the [`VMState`] tra=
it,
//! which is defined by all migrateable types.
//!
+//! * [`impl_vmstate_forward`](crate::impl_vmstate_forward) and
+//! [`impl_vmstate_bitsized`](crate::impl_vmstate_bitsized), which help =
with
+//! the definition of the [`VMState`] trait (respectively for transparent
+//! structs and for `bilge`-defined types)
+//!
//! * helper macros to declare a device model state struct, in particular
//! [`vmstate_subsections`](crate::vmstate_subsections) and
//! [`vmstate_fields`](crate::vmstate_fields).
@@ -134,7 +139,9 @@ macro_rules! info_enum_to_ref {
/// # Safety
///
/// The contents of this trait go straight into structs that are parsed by=
C
-/// code and used to introspect into other structs. Be careful.
+/// code and used to introspect into other structs. Generally, you don't =
need
+/// to implement it except via macros that do it for you, such as
+/// `impl_vmstate_bitsized!`.
pub unsafe trait VMState {
/// The `info` member of a `VMStateField` is a pointer and as such can=
not
/// yet be included in the [`BASE`](VMState::BASE) associated constant;
@@ -188,7 +195,9 @@ pub const fn vmstate_varray_flag<T: VMState>(_: Phantom=
Data<T>) -> VMStateFlags
/// * an array of any of the above
///
/// In order to support other types, the trait `VMState` must be implement=
ed
-/// for them.
+/// for them. The macros
+/// [`impl_vmstate_bitsized!`](crate::impl_vmstate_bitsized)
+/// and [`impl_vmstate_forward!`](crate::impl_vmstate_forward) help with t=
his.
#[macro_export]
macro_rules! vmstate_of {
($struct_name:ty, $field_name:ident $([0 .. $num:ident $(* $factor:exp=
r)?])? $(,)?) =3D> {
@@ -276,6 +285,32 @@ pub const fn with_varray_multiply(mut self, num: u32) =
-> VMStateField {
}
}
=20
+/// This macro can be used (by just passing it a type) to forward the `VMS=
tate`
+/// trait to the first field of a tuple. This is a workaround for lack of
+/// support of nested [`offset_of`](core::mem::offset_of) until Rust 1.82.=
0.
+///
+/// # Examples
+///
+/// ```
+/// # use qemu_api::vmstate::impl_vmstate_forward;
+/// pub struct Fifo([u8; 16]);
+/// impl_vmstate_forward!(Fifo);
+/// ```
+#[macro_export]
+macro_rules! impl_vmstate_forward {
+ // This is similar to impl_vmstate_transparent below, but it
+ // uses the same trick as vmstate_of! to obtain the type of
+ // the first field of the tuple
+ ($tuple:ty) =3D> {
+ unsafe impl $crate::vmstate::VMState for $tuple {
+ const SCALAR_TYPE: $crate::vmstate::VMStateFieldType =3D
+ $crate::call_func_with_field!($crate::vmstate::vmstate_sca=
lar_type, $tuple, 0);
+ const BASE: $crate::bindings::VMStateField =3D
+ $crate::call_func_with_field!($crate::vmstate::vmstate_bas=
e, $tuple, 0);
+ }
+ };
+}
+
// Transparent wrappers: just use the internal type
=20
macro_rules! impl_vmstate_transparent {
@@ -296,6 +331,26 @@ unsafe impl<$base> VMState for $type where $base: VMSt=
ate $($where)* {
impl_vmstate_transparent!(crate::cell::BqlCell<T> where T: VMState);
impl_vmstate_transparent!(crate::cell::BqlRefCell<T> where T: VMState);
=20
+#[macro_export]
+macro_rules! impl_vmstate_bitsized {
+ ($type:ty) =3D> {
+ unsafe impl $crate::vmstate::VMState for $type {
+ const SCALAR_TYPE: $crate::vmstate::VMStateFieldType =3D
+ <<<$type as ::bilge::prelude::Bits=
ized>::ArbitraryInt
+ as ::bilge::prelude::Number>::Un=
derlyingType
+ as $crate::vmstate::VMState>::SCA=
LAR_TYPE;
+ const BASE: $crate::bindings::VMStateField =3D
+ <<<$type as ::bilge::prelude::Bits=
ized>::ArbitraryInt
+ as ::bilge::prelude::Number>::Un=
derlyingType
+ as $crate::vmstate::VMState>::BAS=
E;
+ const VARRAY_FLAG: $crate::bindings::VMStateFlags =3D
+ <<<$type as ::bilge::prelude::Bits=
ized>::ArbitraryInt
+ as ::bilge::prelude::Number>::Un=
derlyingType
+ as $crate::vmstate::VMState>::VAR=
RAY_FLAG;
+ }
+ };
+}
+
// Scalar types using predefined VMStateInfos
=20
macro_rules! impl_vmstate_scalar {
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 31/48] rust: qemu_api: add vmstate_struct
Date: Fri, 24 Jan 2025 10:44:25 +0100
Message-ID: <20250124094442.13207-32-pbonzini@redhat.com>
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It is not type safe, but it's the best that can be done without
const_refs_static. It can also be used with BqlCell and BqlRefCell.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/vmstate.rs | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 9ac699b73b7..d3a9cffdf3f 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -628,6 +628,39 @@ macro_rules! vmstate_array_of_pointer_to_struct {
}};
}
=20
+// FIXME: including the `vmsd` field in a `const` is not possible without
+// the const_refs_static feature (stabilized in Rust 1.83.0). Without it,
+// it is not possible to use VMS_STRUCT in a transparent manner using
+// `vmstate_of!`. While VMSTATE_CLOCK can at least try to be type-safe,
+// VMSTATE_STRUCT includes $type only for documentation purposes; it
+// is checked against $field_name and $struct_name, but not against $vmsd
+// which is what really would matter.
+#[doc(alias =3D "VMSTATE_STRUCT")]
+#[macro_export]
+macro_rules! vmstate_struct {
+ ($struct_name:ty, $field_name:ident $([0 .. $num:ident $(* $factor:exp=
r)?])?, $vmsd:expr, $type:ty $(,)?) =3D> {
+ $crate::bindings::VMStateField {
+ name: ::core::concat!(::core::stringify!($field_name), "\0")
+ .as_bytes()
+ .as_ptr() as *const ::std::os::raw::c_char,
+ $(.num_offset: $crate::offset_of!($struct_name, $num),)?
+ offset: {
+ $crate::assert_field_type!($struct_name, $field_name, $typ=
e);
+ $crate::offset_of!($struct_name, $field_name)
+ },
+ size: ::core::mem::size_of::<$type>(),
+ flags: $crate::bindings::VMStateFlags::VMS_STRUCT,
+ vmsd: unsafe { $vmsd },
+ ..$crate::zeroable::Zeroable::ZERO $(
+ .with_varray_flag($crate::call_func_with_field!(
+ $crate::vmstate::vmstate_varray_flag,
+ $struct_name,
+ $num))
+ $(.with_varray_multiply($factor))?)?
+ }
+ };
+}
+
#[doc(alias =3D "VMSTATE_CLOCK_V")]
#[macro_export]
macro_rules! vmstate_clock_v {
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 32/48] rust: pl011: switch vmstate to new-style macros
Date: Fri, 24 Jan 2025 10:44:26 +0100
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 3 ++-
rust/hw/char/pl011/src/device_class.rs | 36 +++++++++++++-------------
rust/hw/char/pl011/src/lib.rs | 6 +++++
3 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 4f1080ff19f..a1a522fdcdb 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -15,7 +15,7 @@
qemu_irq, sysbus_connect_irq, sysbus_mmio_map, sysbus_realize_and_=
unref, CharBackend,
Chardev, Clock, ClockEvent, MemoryRegion, QEMUChrEvent, CHR_IOCTL_=
SERIAL_SET_BREAK,
},
- c_str,
+ c_str, impl_vmstate_forward,
irq::InterruptSource,
prelude::*,
qdev::{DeviceImpl, DeviceState, Property},
@@ -61,6 +61,7 @@ impl DeviceId {
#[repr(transparent)]
#[derive(Debug, Default)]
pub struct Fifo([registers::Data; PL011_FIFO_DEPTH as usize]);
+impl_vmstate_forward!(Fifo);
=20
impl Fifo {
const fn len(&self) -> u32 {
diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr=
c/device_class.rs
index 7f3ca895071..e0d3532e956 100644
--- a/rust/hw/char/pl011/src/device_class.rs
+++ b/rust/hw/char/pl011/src/device_class.rs
@@ -6,11 +6,11 @@
use std::os::raw::{c_int, c_void};
=20
use qemu_api::{
- bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_subsections=
, vmstate_uint32,
- vmstate_uint32_array, vmstate_unused, zeroable::Zeroable,
+ bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_of, vmstate=
_subsections,
+ vmstate_unused, zeroable::Zeroable,
};
=20
-use crate::device::{PL011State, PL011_FIFO_DEPTH};
+use crate::device::PL011State;
=20
extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> bool {
unsafe {
@@ -52,21 +52,21 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, vers=
ion_id: c_int) -> c_int {
post_load: Some(pl011_post_load),
fields: vmstate_fields! {
vmstate_unused!(core::mem::size_of::<u32>()),
- vmstate_uint32!(flags, PL011State),
- vmstate_uint32!(line_control, PL011State),
- vmstate_uint32!(receive_status_error_clear, PL011State),
- vmstate_uint32!(control, PL011State),
- vmstate_uint32!(dmacr, PL011State),
- vmstate_uint32!(int_enabled, PL011State),
- vmstate_uint32!(int_level, PL011State),
- vmstate_uint32_array!(read_fifo, PL011State, PL011_FIFO_DEPTH),
- vmstate_uint32!(ilpr, PL011State),
- vmstate_uint32!(ibrd, PL011State),
- vmstate_uint32!(fbrd, PL011State),
- vmstate_uint32!(ifl, PL011State),
- vmstate_uint32!(read_pos, PL011State),
- vmstate_uint32!(read_count, PL011State),
- vmstate_uint32!(read_trigger, PL011State),
+ vmstate_of!(PL011State, flags),
+ vmstate_of!(PL011State, line_control),
+ vmstate_of!(PL011State, receive_status_error_clear),
+ vmstate_of!(PL011State, control),
+ vmstate_of!(PL011State, dmacr),
+ vmstate_of!(PL011State, int_enabled),
+ vmstate_of!(PL011State, int_level),
+ vmstate_of!(PL011State, read_fifo),
+ vmstate_of!(PL011State, ilpr),
+ vmstate_of!(PL011State, ibrd),
+ vmstate_of!(PL011State, fbrd),
+ vmstate_of!(PL011State, ifl),
+ vmstate_of!(PL011State, read_pos),
+ vmstate_of!(PL011State, read_count),
+ vmstate_of!(PL011State, read_trigger),
},
subsections: vmstate_subsections! {
VMSTATE_PL011_CLOCK
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index 0a89d393e0f..f30f9850ad4 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -106,6 +106,7 @@ pub mod registers {
//! Device registers exposed as typed structs which are backed by arbi=
trary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
use bilge::prelude::*;
+ use qemu_api::impl_vmstate_bitsized;
=20
/// Receive Status Register / Data Register common error bits
///
@@ -172,6 +173,7 @@ pub struct Data {
pub errors: Errors,
_reserved: u16,
}
+ impl_vmstate_bitsized!(Data);
=20
impl Data {
// bilge is not very const-friendly, unfortunately
@@ -208,6 +210,7 @@ pub struct ReceiveStatusErrorClear {
pub errors: Errors,
_reserved_unpredictable: u24,
}
+ impl_vmstate_bitsized!(ReceiveStatusErrorClear);
=20
impl ReceiveStatusErrorClear {
pub fn set_from_data(&mut self, data: Data) {
@@ -280,6 +283,7 @@ pub struct Flags {
pub ring_indicator: bool,
_reserved_zero_no_modify: u23,
}
+ impl_vmstate_bitsized!(Flags);
=20
impl Flags {
pub fn reset(&mut self) {
@@ -354,6 +358,7 @@ pub struct LineControl {
/// 31:8 - Reserved, do not modify, read as zero.
_reserved_zero_no_modify: u24,
}
+ impl_vmstate_bitsized!(LineControl);
=20
impl LineControl {
pub fn reset(&mut self) {
@@ -498,6 +503,7 @@ pub struct Control {
/// 31:16 - Reserved, do not modify, read as zero.
_reserved_zero_no_modify2: u16,
}
+ impl_vmstate_bitsized!(Control);
=20
impl Control {
pub fn reset(&mut self) {
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 33/48] rust: vmstate: remove translation of C vmstate macros
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Keep vmstate_clock!; because it uses a field of type VMStateDescription,
it cannot be converted to the VMState trait without access to the
const_refs_static feature.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/vmstate.rs | 274 +++--------------------------------
1 file changed, 23 insertions(+), 251 deletions(-)
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index d3a9cffdf3f..120933e60da 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -21,8 +21,8 @@
//! [`vmstate_fields`](crate::vmstate_fields).
//!
//! * direct equivalents to the C macros declared in
-//! `include/migration/vmstate.h`. These are not type-safe and should no=
t be
-//! used if the equivalent functionality is available with `vmstate_of!`.
+//! `include/migration/vmstate.h`. These are not type-safe and only prov=
ide
+//! functionality that is missing from `vmstate_of!`.
=20
use core::{marker::PhantomData, mem, ptr::NonNull};
=20
@@ -407,223 +407,16 @@ unsafe impl<$base> VMState for $type where $base: VM=
State $($where)* {
const BASE: VMStateField =3D <T as VMState>::BASE.with_array_flag(N);
}
=20
-#[doc(alias =3D "VMSTATE_UNUSED_BUFFER")]
-#[macro_export]
-macro_rules! vmstate_unused_buffer {
- ($field_exists_fn:expr, $version_id:expr, $size:expr) =3D> {{
- $crate::bindings::VMStateField {
- name: c_str!("unused").as_ptr(),
- err_hint: ::core::ptr::null(),
- offset: 0,
- size: $size,
- start: 0,
- num: 0,
- num_offset: 0,
- size_offset: 0,
- info: unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate=
_info_unused_buffer) },
- flags: VMStateFlags::VMS_BUFFER,
- vmsd: ::core::ptr::null(),
- version_id: $version_id,
- struct_version_id: 0,
- field_exists: $field_exists_fn,
- }
- }};
-}
-
-#[doc(alias =3D "VMSTATE_UNUSED_V")]
-#[macro_export]
-macro_rules! vmstate_unused_v {
- ($version_id:expr, $size:expr) =3D> {{
- $crate::vmstate_unused_buffer!(None, $version_id, $size)
- }};
-}
-
#[doc(alias =3D "VMSTATE_UNUSED")]
#[macro_export]
macro_rules! vmstate_unused {
($size:expr) =3D> {{
- $crate::vmstate_unused_v!(0, $size)
- }};
-}
-
-#[doc(alias =3D "VMSTATE_SINGLE_TEST")]
-#[macro_export]
-macro_rules! vmstate_single_test {
- ($field_name:ident, $struct_name:ty, $field_exists_fn:expr, $version_i=
d:expr, $info:expr, $size:expr) =3D> {{
$crate::bindings::VMStateField {
- name: ::core::concat!(::core::stringify!($field_name), 0)
- .as_bytes()
- .as_ptr() as *const ::std::os::raw::c_char,
- err_hint: ::core::ptr::null(),
- offset: $crate::offset_of!($struct_name, $field_name),
+ name: $crate::c_str!("unused").as_ptr(),
size: $size,
- start: 0,
- num: 0,
- num_offset: 0,
- size_offset: 0,
- info: unsafe { $info },
- flags: VMStateFlags::VMS_SINGLE,
- vmsd: ::core::ptr::null(),
- version_id: $version_id,
- struct_version_id: 0,
- field_exists: $field_exists_fn,
- }
- }};
-}
-
-#[doc(alias =3D "VMSTATE_SINGLE")]
-#[macro_export]
-macro_rules! vmstate_single {
- ($field_name:ident, $struct_name:ty, $version_id:expr, $info:expr, $si=
ze:expr) =3D> {{
- $crate::vmstate_single_test!($field_name, $struct_name, None, $ver=
sion_id, $info, $size)
- }};
-}
-
-#[doc(alias =3D "VMSTATE_UINT32_V")]
-#[macro_export]
-macro_rules! vmstate_uint32_v {
- ($field_name:ident, $struct_name:ty, $version_id:expr) =3D> {{
- $crate::vmstate_single!(
- $field_name,
- $struct_name,
- $version_id,
- ::core::ptr::addr_of!($crate::bindings::vmstate_info_uint32),
- ::core::mem::size_of::<u32>()
- )
- }};
-}
-
-#[doc(alias =3D "VMSTATE_UINT32")]
-#[macro_export]
-macro_rules! vmstate_uint32 {
- ($field_name:ident, $struct_name:ty) =3D> {{
- $crate::vmstate_uint32_v!($field_name, $struct_name, 0)
- }};
-}
-
-#[doc(alias =3D "VMSTATE_ARRAY")]
-#[macro_export]
-macro_rules! vmstate_array {
- ($field_name:ident, $struct_name:ty, $length:expr, $version_id:expr, $=
info:expr, $size:expr) =3D> {{
- $crate::bindings::VMStateField {
- name: ::core::concat!(::core::stringify!($field_name), 0)
- .as_bytes()
- .as_ptr() as *const ::std::os::raw::c_char,
- err_hint: ::core::ptr::null(),
- offset: $crate::offset_of!($struct_name, $field_name),
- size: $size,
- start: 0,
- num: $length as _,
- num_offset: 0,
- size_offset: 0,
- info: unsafe { $info },
- flags: VMStateFlags::VMS_ARRAY,
- vmsd: ::core::ptr::null(),
- version_id: $version_id,
- struct_version_id: 0,
- field_exists: None,
- }
- }};
-}
-
-#[doc(alias =3D "VMSTATE_UINT32_ARRAY_V")]
-#[macro_export]
-macro_rules! vmstate_uint32_array_v {
- ($field_name:ident, $struct_name:ty, $length:expr, $version_id:expr) =
=3D> {{
- $crate::vmstate_array!(
- $field_name,
- $struct_name,
- $length,
- $version_id,
- ::core::ptr::addr_of!($crate::bindings::vmstate_info_uint32),
- ::core::mem::size_of::<u32>()
- )
- }};
-}
-
-#[doc(alias =3D "VMSTATE_UINT32_ARRAY")]
-#[macro_export]
-macro_rules! vmstate_uint32_array {
- ($field_name:ident, $struct_name:ty, $length:expr) =3D> {{
- $crate::vmstate_uint32_array_v!($field_name, $struct_name, $length=
, 0)
- }};
-}
-
-#[doc(alias =3D "VMSTATE_STRUCT_POINTER_V")]
-#[macro_export]
-macro_rules! vmstate_struct_pointer_v {
- ($field_name:ident, $struct_name:ty, $version_id:expr, $vmsd:expr, $ty=
pe:ty) =3D> {{
- $crate::bindings::VMStateField {
- name: ::core::concat!(::core::stringify!($field_name), 0)
- .as_bytes()
- .as_ptr() as *const ::std::os::raw::c_char,
- err_hint: ::core::ptr::null(),
- offset: $crate::offset_of!($struct_name, $field_name),
- size: ::core::mem::size_of::<*const $type>(),
- start: 0,
- num: 0,
- num_offset: 0,
- size_offset: 0,
- info: ::core::ptr::null(),
- flags: VMStateFlags(VMStateFlags::VMS_STRUCT.0 | VMStateFlags:=
:VMS_POINTER.0),
- vmsd: unsafe { $vmsd },
- version_id: $version_id,
- struct_version_id: 0,
- field_exists: None,
- }
- }};
-}
-
-#[doc(alias =3D "VMSTATE_ARRAY_OF_POINTER")]
-#[macro_export]
-macro_rules! vmstate_array_of_pointer {
- ($field_name:ident, $struct_name:ty, $num:expr, $version_id:expr, $inf=
o:expr, $type:ty) =3D> {{
- $crate::bindings::VMStateField {
- name: ::core::concat!(::core::stringify!($field_name), 0)
- .as_bytes()
- .as_ptr() as *const ::std::os::raw::c_char,
- version_id: $version_id,
- num: $num as _,
- info: unsafe { $info },
- size: ::core::mem::size_of::<*const $type>(),
- flags: VMStateFlags(VMStateFlags::VMS_ARRAY.0 | VMStateFlags::=
VMS_ARRAY_OF_POINTER.0),
- offset: $crate::offset_of!($struct_name, $field_name),
- err_hint: ::core::ptr::null(),
- start: 0,
- num_offset: 0,
- size_offset: 0,
- vmsd: ::core::ptr::null(),
- struct_version_id: 0,
- field_exists: None,
- }
- }};
-}
-
-#[doc(alias =3D "VMSTATE_ARRAY_OF_POINTER_TO_STRUCT")]
-#[macro_export]
-macro_rules! vmstate_array_of_pointer_to_struct {
- ($field_name:ident, $struct_name:ty, $num:expr, $version_id:expr, $vms=
d:expr, $type:ty) =3D> {{
- $crate::bindings::VMStateField {
- name: ::core::concat!(::core::stringify!($field_name), 0)
- .as_bytes()
- .as_ptr() as *const ::std::os::raw::c_char,
- version_id: $version_id,
- num: $num as _,
- vmsd: unsafe { $vmsd },
- size: ::core::mem::size_of::<*const $type>(),
- flags: VMStateFlags(
- VMStateFlags::VMS_ARRAY.0
- | VMStateFlags::VMS_STRUCT.0
- | VMStateFlags::VMS_ARRAY_OF_POINTER.0,
- ),
- offset: $crate::offset_of!($struct_name, $field_name),
- err_hint: ::core::ptr::null(),
- start: 0,
- num_offset: 0,
- size_offset: 0,
- vmsd: ::core::ptr::null(),
- struct_version_id: 0,
- field_exists: None,
+ info: unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate=
_info_unused_buffer) },
+ flags: $crate::bindings::VMStateFlags::VMS_BUFFER,
+ ..$crate::zeroable::Zeroable::ZERO
}
}};
}
@@ -661,48 +454,27 @@ macro_rules! vmstate_struct {
};
}
=20
-#[doc(alias =3D "VMSTATE_CLOCK_V")]
-#[macro_export]
-macro_rules! vmstate_clock_v {
- ($field_name:ident, $struct_name:ty, $version_id:expr) =3D> {{
- $crate::vmstate_struct_pointer_v!(
- $field_name,
- $struct_name,
- $version_id,
- ::core::ptr::addr_of!($crate::bindings::vmstate_clock),
- $crate::bindings::Clock
- )
- }};
-}
-
#[doc(alias =3D "VMSTATE_CLOCK")]
#[macro_export]
macro_rules! vmstate_clock {
($field_name:ident, $struct_name:ty) =3D> {{
- $crate::vmstate_clock_v!($field_name, $struct_name, 0)
- }};
-}
-
-#[doc(alias =3D "VMSTATE_ARRAY_CLOCK_V")]
-#[macro_export]
-macro_rules! vmstate_array_clock_v {
- ($field_name:ident, $struct_name:ty, $num:expr, $version_id:expr) =3D>=
{{
- $crate::vmstate_array_of_pointer_to_struct!(
- $field_name,
- $struct_name,
- $num,
- $version_id,
- ::core::ptr::addr_of!($crate::bindings::vmstate_clock),
- $crate::bindings::Clock
- )
- }};
-}
-
-#[doc(alias =3D "VMSTATE_ARRAY_CLOCK")]
-#[macro_export]
-macro_rules! vmstate_array_clock {
- ($field_name:ident, $struct_name:ty, $num:expr) =3D> {{
- $crate::vmstate_array_clock_v!($field_name, $struct_name, $name, 0)
+ $crate::bindings::VMStateField {
+ name: ::core::concat!(::core::stringify!($field_name), "\0")
+ .as_bytes()
+ .as_ptr() as *const ::std::os::raw::c_char,
+ offset: {
+ $crate::assert_field_type!(
+ $struct_name,
+ $field_name,
+ core::ptr::NonNull<$crate::bindings::Clock>
+ );
+ $crate::offset_of!($struct_name, $field_name)
+ },
+ size: ::core::mem::size_of::<*const $crate::bindings::Clock>(),
+ flags: VMStateFlags(VMStateFlags::VMS_STRUCT.0 | VMStateFlags:=
:VMS_POINTER.0),
+ vmsd: unsafe { ::core::ptr::addr_of!($crate::bindings::vmstate=
_clock) },
+ ..$crate::zeroable::Zeroable::ZERO
+ }
}};
}
=20
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 34/48] rust: vmstate: make order of parameters consistent in
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Place struct_name before field_name, similar to offset_of.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device_class.rs | 2 +-
rust/qemu-api/src/vmstate.rs | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr=
c/device_class.rs
index e0d3532e956..b052d98803f 100644
--- a/rust/hw/char/pl011/src/device_class.rs
+++ b/rust/hw/char/pl011/src/device_class.rs
@@ -27,7 +27,7 @@ extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> =
bool {
minimum_version_id: 1,
needed: Some(pl011_clock_needed),
fields: vmstate_fields! {
- vmstate_clock!(clock, PL011State),
+ vmstate_clock!(PL011State, clock),
},
..Zeroable::ZERO
};
diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs
index 120933e60da..6ac432cf52f 100644
--- a/rust/qemu-api/src/vmstate.rs
+++ b/rust/qemu-api/src/vmstate.rs
@@ -457,7 +457,7 @@ macro_rules! vmstate_struct {
#[doc(alias =3D "VMSTATE_CLOCK")]
#[macro_export]
macro_rules! vmstate_clock {
- ($field_name:ident, $struct_name:ty) =3D> {{
+ ($struct_name:ty, $field_name:ident) =3D> {{
$crate::bindings::VMStateField {
name: ::core::concat!(::core::stringify!($field_name), "\0")
.as_bytes()
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 35/48] rust: prefer NonNull::new to assertions
Date: Fri, 24 Jan 2025 10:44:29 +0100
Message-ID: <20250124094442.13207-36-pbonzini@redhat.com>
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Do not use new_unchecked; the effect is the same, but the
code is easier to read and unsafe regions become smaller.
Likewise, NonNull::new can be used instead of assertion and
followed by as_ref() or as_mut() instead of dereferencing the
pointer.
Suggested-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 17 +++++------------
rust/hw/char/pl011/src/device_class.rs | 23 +++++++++--------------
rust/hw/char/pl011/src/memory_ops.rs | 9 +++------
rust/qemu-api/src/qdev.rs | 12 +++++-------
rust/qemu-api/src/qom.rs | 21 +++++++++++++--------
5 files changed, 35 insertions(+), 47 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index a1a522fdcdb..c0b53f2515c 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -593,11 +593,8 @@ pub fn post_load(&mut self, _version_id: u32) -> Resul=
t<(), ()> {
/// the same size as [`PL011State`]. We also expect the device is
/// readable/writeable from one thread at any time.
pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int {
- unsafe {
- debug_assert!(!opaque.is_null());
- let state =3D NonNull::new_unchecked(opaque.cast::<PL011State>());
- state.as_ref().can_receive().into()
- }
+ let state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ unsafe { state.as_ref().can_receive().into() }
}
=20
/// # Safety
@@ -608,9 +605,8 @@ pub fn post_load(&mut self, _version_id: u32) -> Result=
<(), ()> {
///
/// The buffer and size arguments must also be valid.
pub unsafe extern "C" fn pl011_receive(opaque: *mut c_void, buf: *const u8=
, size: c_int) {
+ let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
unsafe {
- debug_assert!(!opaque.is_null());
- let mut state =3D NonNull::new_unchecked(opaque.cast::<PL011State>=
());
if state.as_ref().loopback_enabled() {
return;
}
@@ -627,11 +623,8 @@ pub fn post_load(&mut self, _version_id: u32) -> Resul=
t<(), ()> {
/// the same size as [`PL011State`]. We also expect the device is
/// readable/writeable from one thread at any time.
pub unsafe extern "C" fn pl011_event(opaque: *mut c_void, event: QEMUChrEv=
ent) {
- unsafe {
- debug_assert!(!opaque.is_null());
- let mut state =3D NonNull::new_unchecked(opaque.cast::<PL011State>=
());
- state.as_mut().event(event)
- }
+ let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ unsafe { state.as_mut().event(event) }
}
=20
/// # Safety
diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr=
c/device_class.rs
index b052d98803f..6fa14ca0f9b 100644
--- a/rust/hw/char/pl011/src/device_class.rs
+++ b/rust/hw/char/pl011/src/device_class.rs
@@ -12,12 +12,10 @@
=20
use crate::device::PL011State;
=20
+#[allow(clippy::missing_const_for_fn)]
extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> bool {
- unsafe {
- debug_assert!(!opaque.is_null());
- let state =3D NonNull::new_unchecked(opaque.cast::<PL011State>());
- state.as_ref().migrate_clock
- }
+ let state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ unsafe { state.as_ref().migrate_clock }
}
=20
/// Migration subsection for [`PL011State`] clock.
@@ -33,15 +31,12 @@ extern "C" fn pl011_clock_needed(opaque: *mut c_void) -=
> bool {
};
=20
extern "C" fn pl011_post_load(opaque: *mut c_void, version_id: c_int) -> c=
_int {
- unsafe {
- debug_assert!(!opaque.is_null());
- let mut state =3D NonNull::new_unchecked(opaque.cast::<PL011State>=
());
- let result =3D state.as_mut().post_load(version_id as u32);
- if result.is_err() {
- -1
- } else {
- 0
- }
+ let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ let result =3D unsafe { state.as_mut().post_load(version_id as u32) };
+ if result.is_err() {
+ -1
+ } else {
+ 0
}
}
=20
diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/=
memory_ops.rs
index c4e8599ba43..a286003d136 100644
--- a/rust/hw/char/pl011/src/memory_ops.rs
+++ b/rust/hw/char/pl011/src/memory_ops.rs
@@ -25,7 +25,7 @@
=20
unsafe extern "C" fn pl011_read(opaque: *mut c_void, addr: hwaddr, size: c=
_uint) -> u64 {
assert!(!opaque.is_null());
- let mut state =3D unsafe { NonNull::new_unchecked(opaque.cast::<PL011S=
tate>()) };
+ let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
let val =3D unsafe { state.as_mut().read(addr, size) };
match val {
std::ops::ControlFlow::Break(val) =3D> val,
@@ -43,9 +43,6 @@
}
=20
unsafe extern "C" fn pl011_write(opaque: *mut c_void, addr: hwaddr, data: =
u64, _size: c_uint) {
- unsafe {
- assert!(!opaque.is_null());
- let mut state =3D NonNull::new_unchecked(opaque.cast::<PL011State>=
());
- state.as_mut().write(addr, data)
- }
+ let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ unsafe { state.as_mut().write(addr, data) }
}
diff --git a/rust/qemu-api/src/qdev.rs b/rust/qemu-api/src/qdev.rs
index a5121e31a37..42429903aae 100644
--- a/rust/qemu-api/src/qdev.rs
+++ b/rust/qemu-api/src/qdev.rs
@@ -4,7 +4,7 @@
=20
//! Bindings to create devices and access device functionality from Rust.
=20
-use std::ffi::CStr;
+use std::{ffi::CStr, ptr::NonNull};
=20
pub use bindings::{DeviceClass, DeviceState, Property};
=20
@@ -55,9 +55,8 @@ fn vmsd() -> Option<&'static VMStateDescription> {
/// can be downcasted to type `T`. We also expect the device is
/// readable/writeable from one thread at any time.
unsafe extern "C" fn rust_realize_fn<T: DeviceImpl>(dev: *mut DeviceState,=
_errp: *mut *mut Error) {
- assert!(!dev.is_null());
- let state =3D dev.cast::<T>();
- T::REALIZE.unwrap()(unsafe { &mut *state });
+ let state =3D NonNull::new(dev).unwrap().cast::<T>();
+ T::REALIZE.unwrap()(unsafe { state.as_ref() });
}
=20
/// # Safety
@@ -66,9 +65,8 @@ fn vmsd() -> Option<&'static VMStateDescription> {
/// can be downcasted to type `T`. We also expect the device is
/// readable/writeable from one thread at any time.
unsafe extern "C" fn rust_reset_fn<T: DeviceImpl>(dev: *mut DeviceState) {
- assert!(!dev.is_null());
- let state =3D dev.cast::<T>();
- T::RESET.unwrap()(unsafe { &mut *state });
+ let mut state =3D NonNull::new(dev).unwrap().cast::<T>();
+ T::RESET.unwrap()(unsafe { state.as_mut() });
}
=20
impl<T> ClassInitImpl<DeviceClass> for T
diff --git a/rust/qemu-api/src/qom.rs b/rust/qemu-api/src/qom.rs
index 97901fb9084..f50ee371aac 100644
--- a/rust/qemu-api/src/qom.rs
+++ b/rust/qemu-api/src/qom.rs
@@ -58,6 +58,7 @@
fmt,
ops::{Deref, DerefMut},
os::raw::c_void,
+ ptr::NonNull,
};
=20
pub use bindings::{Object, ObjectClass};
@@ -153,27 +154,34 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> Result<(=
), fmt::Error> {
}
=20
unsafe extern "C" fn rust_instance_init<T: ObjectImpl>(obj: *mut Object) {
+ let mut state =3D NonNull::new(obj).unwrap().cast::<T>();
// SAFETY: obj is an instance of T, since rust_instance_init<T>
// is called from QOM core as the instance_init function
// for class T
- unsafe { T::INSTANCE_INIT.unwrap()(&mut *obj.cast::<T>()) }
+ unsafe {
+ T::INSTANCE_INIT.unwrap()(state.as_mut());
+ }
}
=20
unsafe extern "C" fn rust_instance_post_init<T: ObjectImpl>(obj: *mut Obje=
ct) {
+ let state =3D NonNull::new(obj).unwrap().cast::<T>();
// SAFETY: obj is an instance of T, since rust_instance_post_init<T>
// is called from QOM core as the instance_post_init function
// for class T
- T::INSTANCE_POST_INIT.unwrap()(unsafe { &*obj.cast::<T>() })
+ T::INSTANCE_POST_INIT.unwrap()(unsafe { state.as_ref() });
}
=20
unsafe extern "C" fn rust_class_init<T: ObjectType + ClassInitImpl<T::Clas=
s>>(
klass: *mut ObjectClass,
_data: *mut c_void,
) {
+ let mut klass =3D NonNull::new(klass)
+ .unwrap()
+ .cast::<<T as ObjectType>::Class>();
// SAFETY: klass is a T::Class, since rust_class_init<T>
// is called from QOM core as the class_init function
// for class T
- T::class_init(unsafe { &mut *klass.cast::<T::Class>() })
+ T::class_init(unsafe { klass.as_mut() })
}
=20
unsafe extern "C" fn drop_object<T: ObjectImpl>(obj: *mut Object) {
@@ -581,11 +589,8 @@ pub trait ClassInitImpl<T> {
/// can be downcasted to type `T`. We also expect the device is
/// readable/writeable from one thread at any time.
unsafe extern "C" fn rust_unparent_fn<T: ObjectImpl>(dev: *mut Object) {
- unsafe {
- assert!(!dev.is_null());
- let state =3D core::ptr::NonNull::new_unchecked(dev.cast::<T>());
- T::UNPARENT.unwrap()(state.as_ref());
- }
+ let state =3D NonNull::new(dev).unwrap().cast::<T>();
+ T::UNPARENT.unwrap()(unsafe { state.as_ref() });
}
=20
impl<T> ClassInitImpl<ObjectClass> for T
--=20
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To: qemu-devel@nongnu.org
Subject: [PULL 36/48] rust: pl011: remove unnecessary "extern crate"
Date: Fri, 24 Jan 2025 10:44:30 +0100
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/lib.rs | 4 ----
1 file changed, 4 deletions(-)
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index f30f9850ad4..d10f0805aac 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -25,10 +25,6 @@
#![allow(clippy::upper_case_acronyms)]
#![allow(clippy::result_unit_err)]
=20
-extern crate bilge;
-extern crate bilge_impl;
-extern crate qemu_api;
-
use qemu_api::c_str;
=20
pub mod device;
--=20
2.48.1
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Subject: [PULL 37/48] rust: pl011: hide unnecessarily "pub" items from outside
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The only public interfaces for pl011 are TYPE_PL011 and pl011_create.
Remove pub from everything else.
Note: the "allow(dead_code)" is removed later.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 2 +-
rust/hw/char/pl011/src/device_class.rs | 2 +-
rust/hw/char/pl011/src/lib.rs | 13 ++++++++-----
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index c0b53f2515c..c8496eeb1b6 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -573,7 +573,7 @@ pub fn post_load(&mut self, _version_id: u32) -> Result=
<(), ()> {
}
=20
/// Which bits in the interrupt status matter for each outbound IRQ line ?
-pub const IRQMASK: [u32; 6] =3D [
+const IRQMASK: [u32; 6] =3D [
/* combined IRQ */
Interrupt::E
| Interrupt::MS
diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr=
c/device_class.rs
index 6fa14ca0f9b..2336a768729 100644
--- a/rust/hw/char/pl011/src/device_class.rs
+++ b/rust/hw/char/pl011/src/device_class.rs
@@ -19,7 +19,7 @@ extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> =
bool {
}
=20
/// Migration subsection for [`PL011State`] clock.
-pub static VMSTATE_PL011_CLOCK: VMStateDescription =3D VMStateDescription {
+static VMSTATE_PL011_CLOCK: VMStateDescription =3D VMStateDescription {
name: c_str!("pl011/clock").as_ptr(),
version_id: 1,
minimum_version_id: 1,
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index d10f0805aac..2baacba2306 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -27,9 +27,11 @@
=20
use qemu_api::c_str;
=20
-pub mod device;
-pub mod device_class;
-pub mod memory_ops;
+mod device;
+mod device_class;
+mod memory_ops;
+
+pub use device::pl011_create;
=20
pub const TYPE_PL011: &::std::ffi::CStr =3D c_str!("pl011");
pub const TYPE_PL011_LUMINARY: &::std::ffi::CStr =3D c_str!("pl011_luminar=
y");
@@ -42,7 +44,7 @@
#[allow(non_camel_case_types)]
#[repr(u64)]
#[derive(Debug, qemu_api_macros::TryInto)]
-pub enum RegisterOffset {
+enum RegisterOffset {
/// Data Register
///
/// A write to this register initiates the actual data transmission
@@ -98,7 +100,8 @@ pub enum RegisterOffset {
//Reserved =3D 0x04C,
}
=20
-pub mod registers {
+#[allow(dead_code)]
+mod registers {
//! Device registers exposed as typed structs which are backed by arbi=
trary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
use bilge::prelude::*;
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 38/48] rust: pl011: extract conversion to RegisterOffset
Date: Fri, 24 Jan 2025 10:44:32 +0100
Message-ID: <20250124094442.13207-39-pbonzini@redhat.com>
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As an added bonus, this also makes the new function return u32 instead
of u64, thus factoring some casts into a single place.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 113 +++++++++++++++++--------------
1 file changed, 64 insertions(+), 49 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index c8496eeb1b6..58b54547336 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -5,6 +5,7 @@
use core::ptr::{addr_of, addr_of_mut, NonNull};
use std::{
ffi::CStr,
+ ops::ControlFlow,
os::raw::{c_int, c_uint, c_void},
};
=20
@@ -222,19 +223,11 @@ fn post_init(&self) {
}
}
=20
- pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::Con=
trolFlow<u64, u64> {
+ fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow<u32, u3=
2> {
use RegisterOffset::*;
=20
- let value =3D match RegisterOffset::try_from(offset) {
- Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> {
- let device_id =3D self.get_class().device_id;
- u32::from(device_id[(offset - 0xfe0) >> 2])
- }
- Err(_) =3D> {
- // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
- 0
- }
- Ok(DR) =3D> {
+ ControlFlow::Break(match offset {
+ DR =3D> {
self.flags.set_receive_fifo_full(false);
let c =3D self.read_fifo[self.read_pos];
if self.read_count > 0 {
@@ -251,39 +244,33 @@ pub fn read(&mut self, offset: hwaddr, _size: c_uint)=
-> std::ops::ControlFlow<u
self.receive_status_error_clear.set_from_data(c);
self.update();
// Must call qemu_chr_fe_accept_input, so return Continue:
- let c =3D u32::from(c);
- return std::ops::ControlFlow::Continue(u64::from(c));
+ return ControlFlow::Continue(u32::from(c));
}
- Ok(RSR) =3D> u32::from(self.receive_status_error_clear),
- Ok(FR) =3D> u32::from(self.flags),
- Ok(FBRD) =3D> self.fbrd,
- Ok(ILPR) =3D> self.ilpr,
- Ok(IBRD) =3D> self.ibrd,
- Ok(LCR_H) =3D> u32::from(self.line_control),
- Ok(CR) =3D> u32::from(self.control),
- Ok(FLS) =3D> self.ifl,
- Ok(IMSC) =3D> self.int_enabled,
- Ok(RIS) =3D> self.int_level,
- Ok(MIS) =3D> self.int_level & self.int_enabled,
- Ok(ICR) =3D> {
+ RSR =3D> u32::from(self.receive_status_error_clear),
+ FR =3D> u32::from(self.flags),
+ FBRD =3D> self.fbrd,
+ ILPR =3D> self.ilpr,
+ IBRD =3D> self.ibrd,
+ LCR_H =3D> u32::from(self.line_control),
+ CR =3D> u32::from(self.control),
+ FLS =3D> self.ifl,
+ IMSC =3D> self.int_enabled,
+ RIS =3D> self.int_level,
+ MIS =3D> self.int_level & self.int_enabled,
+ ICR =3D> {
// "The UARTICR Register is the interrupt clear register a=
nd is write-only"
// Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, =
UARTICR
0
}
- Ok(DMACR) =3D> self.dmacr,
- };
- std::ops::ControlFlow::Break(value.into())
+ DMACR =3D> self.dmacr,
+ })
}
=20
- pub fn write(&mut self, offset: hwaddr, value: u64) {
+ fn regs_write(&mut self, offset: RegisterOffset, value: u32) {
// eprintln!("write offset {offset} value {value}");
use RegisterOffset::*;
- let value: u32 =3D value as u32;
- match RegisterOffset::try_from(offset) {
- Err(_bad_offset) =3D> {
- eprintln!("write bad offset {offset} value {value}");
- }
- Ok(DR) =3D> {
+ match offset {
+ DR =3D> {
// ??? Check if transmitter is enabled.
let ch: u8 =3D value as u8;
// XXX this blocks entire thread. Rewrite to use
@@ -298,22 +285,22 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
self.int_level |=3D registers::INT_TX;
self.update();
}
- Ok(RSR) =3D> {
- self.receive_status_error_clear.reset();
+ RSR =3D> {
+ self.receive_status_error_clear =3D 0.into();
}
- Ok(FR) =3D> {
+ FR =3D> {
// flag writes are ignored
}
- Ok(ILPR) =3D> {
+ ILPR =3D> {
self.ilpr =3D value;
}
- Ok(IBRD) =3D> {
+ IBRD =3D> {
self.ibrd =3D value;
}
- Ok(FBRD) =3D> {
+ FBRD =3D> {
self.fbrd =3D value;
}
- Ok(LCR_H) =3D> {
+ LCR_H =3D> {
let new_val: registers::LineControl =3D value.into();
// Reset the FIFO state on FIFO enable or disable
if self.line_control.fifos_enabled() !=3D new_val.fifos_en=
abled() {
@@ -336,26 +323,26 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
self.line_control =3D new_val;
self.set_read_trigger();
}
- Ok(CR) =3D> {
+ CR =3D> {
// ??? Need to implement the enable bit.
self.control =3D value.into();
self.loopback_mdmctrl();
}
- Ok(FLS) =3D> {
+ FLS =3D> {
self.ifl =3D value;
self.set_read_trigger();
}
- Ok(IMSC) =3D> {
+ IMSC =3D> {
self.int_enabled =3D value;
self.update();
}
- Ok(RIS) =3D> {}
- Ok(MIS) =3D> {}
- Ok(ICR) =3D> {
+ RIS =3D> {}
+ MIS =3D> {}
+ ICR =3D> {
self.int_level &=3D !value;
self.update();
}
- Ok(DMACR) =3D> {
+ DMACR =3D> {
self.dmacr =3D value;
if value & 3 > 0 {
// qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente=
d\n");
@@ -570,6 +557,34 @@ pub fn post_load(&mut self, _version_id: u32) -> Resul=
t<(), ()> {
=20
Ok(())
}
+
+ pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow<u64,=
u64> {
+ match RegisterOffset::try_from(offset) {
+ Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> {
+ let device_id =3D self.get_class().device_id;
+ ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >>=
2]))
+ }
+ Err(_) =3D> {
+ // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
+ ControlFlow::Break(0)
+ }
+ Ok(field) =3D> {
+ let result =3D self.regs_read(field);
+ match result {
+ ControlFlow::Break(value) =3D> ControlFlow::Break(valu=
e.into()),
+ ControlFlow::Continue(value) =3D> ControlFlow::Continu=
e(value.into()),
+ }
+ }
+ }
+ }
+
+ pub fn write(&mut self, offset: hwaddr, value: u64) {
+ if let Ok(field) =3D RegisterOffset::try_from(offset) {
+ self.regs_write(field, value as u32);
+ } else {
+ eprintln!("write bad offset {offset} value {value}");
+ }
+ }
}
=20
/// Which bits in the interrupt status matter for each outbound IRQ line ?
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 39/48] rust: pl011: extract CharBackend receive logic into a
separate function
Date: Fri, 24 Jan 2025 10:44:33 +0100
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Prepare for moving all references to the registers and the FIFO into a
separate struct.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 58b54547336..de5110038a5 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -6,7 +6,7 @@
use std::{
ffi::CStr,
ops::ControlFlow,
- os::raw::{c_int, c_uint, c_void},
+ os::raw::{c_int, c_void},
};
=20
use qemu_api::{
@@ -488,6 +488,12 @@ pub fn can_receive(&self) -> bool {
self.read_count < self.fifo_depth()
}
=20
+ pub fn receive(&mut self, ch: u32) {
+ if !self.loopback_enabled() {
+ self.put_fifo(ch)
+ }
+ }
+
pub fn event(&mut self, event: QEMUChrEvent) {
if event =3D=3D QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_en=
abled() {
self.put_fifo(registers::Data::BREAK.into());
@@ -513,7 +519,7 @@ pub fn fifo_depth(&self) -> u32 {
1
}
=20
- pub fn put_fifo(&mut self, value: c_uint) {
+ pub fn put_fifo(&mut self, value: u32) {
let depth =3D self.fifo_depth();
assert!(depth > 0);
let slot =3D (self.read_pos + self.read_count) & (depth - 1);
@@ -622,12 +628,9 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
pub unsafe extern "C" fn pl011_receive(opaque: *mut c_void, buf: *const u8=
, size: c_int) {
let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
unsafe {
- if state.as_ref().loopback_enabled() {
- return;
- }
if size > 0 {
debug_assert!(!buf.is_null());
- state.as_mut().put_fifo(c_uint::from(buf.read_volatile()))
+ state.as_mut().receive(u32::from(buf.read_volatile()));
}
}
}
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 40/48] rust: pl011: pull interrupt updates out of read/write
ops
Date: Fri, 24 Jan 2025 10:44:34 +0100
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qemu_irqs are not part of the vmstate, therefore they will remain in
PL011State. Update them if needed after regs_read()/regs_write().
Apply #[must_use] to functions that return whether the interrupt state
could have changed, so that it's harder to forget the call to update().
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 84 ++++++++++++++++++--------------
1 file changed, 48 insertions(+), 36 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index de5110038a5..9cac9d352a2 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -242,7 +242,6 @@ fn regs_read(&mut self, offset: RegisterOffset) -> Cont=
rolFlow<u32, u32> {
}
// Update error bits.
self.receive_status_error_clear.set_from_data(c);
- self.update();
// Must call qemu_chr_fe_accept_input, so return Continue:
return ControlFlow::Continue(u32::from(c));
}
@@ -266,7 +265,7 @@ fn regs_read(&mut self, offset: RegisterOffset) -> Cont=
rolFlow<u32, u32> {
})
}
=20
- fn regs_write(&mut self, offset: RegisterOffset, value: u32) {
+ fn regs_write(&mut self, offset: RegisterOffset, value: u32) -> bool {
// eprintln!("write offset {offset} value {value}");
use RegisterOffset::*;
match offset {
@@ -281,9 +280,10 @@ fn regs_write(&mut self, offset: RegisterOffset, value=
: u32) {
unsafe {
qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),=
&ch, 1);
}
- self.loopback_tx(value);
+ // interrupts always checked
+ let _ =3D self.loopback_tx(value);
self.int_level |=3D registers::INT_TX;
- self.update();
+ return true;
}
RSR =3D> {
self.receive_status_error_clear =3D 0.into();
@@ -307,7 +307,7 @@ fn regs_write(&mut self, offset: RegisterOffset, value:=
u32) {
self.reset_rx_fifo();
self.reset_tx_fifo();
}
- if self.line_control.send_break() ^ new_val.send_break() {
+ let update =3D (self.line_control.send_break() !=3D new_va=
l.send_break()) && {
let mut break_enable: c_int =3D new_val.send_break().i=
nto();
// SAFETY: self.char_backend is a valid CharBackend in=
stance after it's been
// initialized in realize().
@@ -318,15 +318,16 @@ fn regs_write(&mut self, offset: RegisterOffset, valu=
e: u32) {
addr_of_mut!(break_enable).cast::<c_void>(),
);
}
- self.loopback_break(break_enable > 0);
- }
+ self.loopback_break(break_enable > 0)
+ };
self.line_control =3D new_val;
self.set_read_trigger();
+ return update;
}
CR =3D> {
// ??? Need to implement the enable bit.
self.control =3D value.into();
- self.loopback_mdmctrl();
+ return self.loopback_mdmctrl();
}
FLS =3D> {
self.ifl =3D value;
@@ -334,13 +335,13 @@ fn regs_write(&mut self, offset: RegisterOffset, valu=
e: u32) {
}
IMSC =3D> {
self.int_enabled =3D value;
- self.update();
+ return true;
}
RIS =3D> {}
MIS =3D> {}
ICR =3D> {
self.int_level &=3D !value;
- self.update();
+ return true;
}
DMACR =3D> {
self.dmacr =3D value;
@@ -350,14 +351,12 @@ fn regs_write(&mut self, offset: RegisterOffset, valu=
e: u32) {
}
}
}
+ false
}
=20
#[inline]
- fn loopback_tx(&mut self, value: u32) {
- if !self.loopback_enabled() {
- return;
- }
-
+ #[must_use]
+ fn loopback_tx(&mut self, value: u32) -> bool {
// Caveat:
//
// In real hardware, TX loopback happens at the serial-bit level
@@ -375,12 +374,13 @@ fn loopback_tx(&mut self, value: u32) {
// hardware flow-control is enabled.
//
// For simplicity, the above described is not emulated.
- self.put_fifo(value);
+ self.loopback_enabled() && self.put_fifo(value)
}
=20
- fn loopback_mdmctrl(&mut self) {
+ #[must_use]
+ fn loopback_mdmctrl(&mut self) -> bool {
if !self.loopback_enabled() {
- return;
+ return false;
}
=20
/*
@@ -421,13 +421,11 @@ fn loopback_mdmctrl(&mut self) {
il |=3D Interrupt::RI as u32;
}
self.int_level =3D il;
- self.update();
+ true
}
=20
- fn loopback_break(&mut self, enable: bool) {
- if enable {
- self.loopback_tx(registers::Data::BREAK.into());
- }
+ fn loopback_break(&mut self, enable: bool) -> bool {
+ enable && self.loopback_tx(registers::Data::BREAK.into())
}
=20
fn set_read_trigger(&mut self) {
@@ -489,14 +487,17 @@ pub fn can_receive(&self) -> bool {
}
=20
pub fn receive(&mut self, ch: u32) {
- if !self.loopback_enabled() {
- self.put_fifo(ch)
+ if !self.loopback_enabled() && self.put_fifo(ch) {
+ self.update();
}
}
=20
pub fn event(&mut self, event: QEMUChrEvent) {
if event =3D=3D QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_en=
abled() {
- self.put_fifo(registers::Data::BREAK.into());
+ let update =3D self.put_fifo(registers::Data::BREAK.into());
+ if update {
+ self.update();
+ }
}
}
=20
@@ -519,7 +520,8 @@ pub fn fifo_depth(&self) -> u32 {
1
}
=20
- pub fn put_fifo(&mut self, value: u32) {
+ #[must_use]
+ pub fn put_fifo(&mut self, value: u32) -> bool {
let depth =3D self.fifo_depth();
assert!(depth > 0);
let slot =3D (self.read_pos + self.read_count) & (depth - 1);
@@ -532,8 +534,9 @@ pub fn put_fifo(&mut self, value: u32) {
=20
if self.read_count =3D=3D self.read_trigger {
self.int_level |=3D registers::INT_RX;
- self.update();
+ return true;
}
+ false
}
=20
pub fn update(&self) {
@@ -565,7 +568,8 @@ pub fn post_load(&mut self, _version_id: u32) -> Result=
<(), ()> {
}
=20
pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow<u64,=
u64> {
- match RegisterOffset::try_from(offset) {
+ let mut update_irq =3D false;
+ let result =3D match RegisterOffset::try_from(offset) {
Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> {
let device_id =3D self.get_class().device_id;
ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >>=
2]))
@@ -574,22 +578,30 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) ->=
ControlFlow<u64, u64> {
// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
ControlFlow::Break(0)
}
- Ok(field) =3D> {
- let result =3D self.regs_read(field);
- match result {
- ControlFlow::Break(value) =3D> ControlFlow::Break(valu=
e.into()),
- ControlFlow::Continue(value) =3D> ControlFlow::Continu=
e(value.into()),
+ Ok(field) =3D> match self.regs_read(field) {
+ ControlFlow::Break(value) =3D> ControlFlow::Break(value.in=
to()),
+ ControlFlow::Continue(value) =3D> {
+ update_irq =3D true;
+ ControlFlow::Continue(value.into())
}
- }
+ },
+ };
+ if update_irq {
+ self.update();
}
+ result
}
=20
pub fn write(&mut self, offset: hwaddr, value: u64) {
+ let mut update_irq =3D false;
if let Ok(field) =3D RegisterOffset::try_from(offset) {
- self.regs_write(field, value as u32);
+ update_irq =3D self.regs_write(field, value as u32);
} else {
eprintln!("write bad offset {offset} value {value}");
}
+ if update_irq {
+ self.update();
+ }
}
}
=20
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 41/48] rust: pl011: extract PL011Registers
Date: Fri, 24 Jan 2025 10:44:35 +0100
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Pull all the mutable fields of PL011State into a separate struct.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 251 ++++++++++++++-----------
rust/hw/char/pl011/src/device_class.rs | 46 +++--
2 files changed, 168 insertions(+), 129 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 9cac9d352a2..f1319d1a8bd 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -85,11 +85,8 @@ fn index(&self, idx: u32) -> &Self::Output {
}
=20
#[repr(C)]
-#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)]
-/// PL011 Device Model in QEMU
-pub struct PL011State {
- pub parent_obj: ParentField<SysBusDevice>,
- pub iomem: MemoryRegion,
+#[derive(Debug, Default, qemu_api_macros::offsets)]
+pub struct PL011Registers {
#[doc(alias =3D "fr")]
pub flags: registers::Flags,
#[doc(alias =3D "lcr")]
@@ -109,8 +106,17 @@ pub struct PL011State {
pub read_pos: u32,
pub read_count: u32,
pub read_trigger: u32,
+}
+
+#[repr(C)]
+#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)]
+/// PL011 Device Model in QEMU
+pub struct PL011State {
+ pub parent_obj: ParentField<SysBusDevice>,
+ pub iomem: MemoryRegion,
#[doc(alias =3D "chr")]
pub char_backend: CharBackend,
+ pub regs: PL011Registers,
/// QEMU interrupts
///
/// ```text
@@ -169,61 +175,8 @@ fn vmsd() -> Option<&'static VMStateDescription> {
const RESET: Option<fn(&mut Self)> =3D Some(Self::reset);
}
=20
-impl PL011State {
- /// Initializes a pre-allocated, unitialized instance of `PL011State`.
- ///
- /// # Safety
- ///
- /// `self` must point to a correctly sized and aligned location for the
- /// `PL011State` type. It must not be called more than once on the same
- /// location/instance. All its fields are expected to hold unitialized
- /// values with the sole exception of `parent_obj`.
- unsafe fn init(&mut self) {
- const CLK_NAME: &CStr =3D c_str!("clk");
-
- // SAFETY:
- //
- // self and self.iomem are guaranteed to be valid at this point si=
nce callers
- // must make sure the `self` reference is valid.
- unsafe {
- memory_region_init_io(
- addr_of_mut!(self.iomem),
- addr_of_mut!(*self).cast::<Object>(),
- &PL011_OPS,
- addr_of_mut!(*self).cast::<c_void>(),
- Self::TYPE_NAME.as_ptr(),
- 0x1000,
- );
- }
-
- // SAFETY:
- //
- // self.clock is not initialized at this point; but since `NonNull=
<_>` is Copy,
- // we can overwrite the undefined value without side effects. This=
is
- // safe since all PL011State instances are created by QOM code whi=
ch
- // calls this function to initialize the fields; therefore no code=
is
- // able to access an invalid self.clock value.
- unsafe {
- let dev: &mut DeviceState =3D self.upcast_mut();
- self.clock =3D NonNull::new(qdev_init_clock_in(
- dev,
- CLK_NAME.as_ptr(),
- None, /* pl011_clock_update */
- addr_of_mut!(*self).cast::<c_void>(),
- ClockEvent::ClockUpdate.0,
- ))
- .unwrap();
- }
- }
-
- fn post_init(&self) {
- self.init_mmio(&self.iomem);
- for irq in self.interrupts.iter() {
- self.init_irq(irq);
- }
- }
-
- fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow<u32, u3=
2> {
+impl PL011Registers {
+ pub(self) fn read(&mut self, offset: RegisterOffset) -> ControlFlow<u3=
2, u32> {
use RegisterOffset::*;
=20
ControlFlow::Break(match offset {
@@ -265,7 +218,12 @@ fn regs_read(&mut self, offset: RegisterOffset) -> Con=
trolFlow<u32, u32> {
})
}
=20
- fn regs_write(&mut self, offset: RegisterOffset, value: u32) -> bool {
+ pub(self) fn write(
+ &mut self,
+ offset: RegisterOffset,
+ value: u32,
+ char_backend: *mut CharBackend,
+ ) -> bool {
// eprintln!("write offset {offset} value {value}");
use RegisterOffset::*;
match offset {
@@ -275,10 +233,10 @@ fn regs_write(&mut self, offset: RegisterOffset, valu=
e: u32) -> bool {
// XXX this blocks entire thread. Rewrite to use
// qemu_chr_fe_write and background I/O callbacks
=20
- // SAFETY: self.char_backend is a valid CharBackend instan=
ce after it's been
+ // SAFETY: char_backend is a valid CharBackend instance af=
ter it's been
// initialized in realize().
unsafe {
- qemu_chr_fe_write_all(addr_of_mut!(self.char_backend),=
&ch, 1);
+ qemu_chr_fe_write_all(char_backend, &ch, 1);
}
// interrupts always checked
let _ =3D self.loopback_tx(value);
@@ -313,7 +271,7 @@ fn regs_write(&mut self, offset: RegisterOffset, value:=
u32) -> bool {
// initialized in realize().
unsafe {
qemu_chr_fe_ioctl(
- addr_of_mut!(self.char_backend),
+ char_backend,
CHR_IOCTL_SERIAL_SET_BREAK as i32,
addr_of_mut!(break_enable).cast::<c_void>(),
);
@@ -432,23 +390,6 @@ fn set_read_trigger(&mut self) {
self.read_trigger =3D 1;
}
=20
- pub fn realize(&self) {
- // SAFETY: self.char_backend has the correct size and alignment fo=
r a
- // CharBackend object, and its callbacks are of the correct types.
- unsafe {
- qemu_chr_fe_set_handlers(
- addr_of!(self.char_backend) as *mut CharBackend,
- Some(pl011_can_receive),
- Some(pl011_receive),
- Some(pl011_event),
- None,
- addr_of!(*self).cast::<c_void>() as *mut c_void,
- core::ptr::null_mut(),
- true,
- );
- }
- }
-
pub fn reset(&mut self) {
self.line_control.reset();
self.receive_status_error_clear.reset();
@@ -481,26 +422,6 @@ pub fn reset_tx_fifo(&mut self) {
self.flags.set_transmit_fifo_empty(true);
}
=20
- pub fn can_receive(&self) -> bool {
- // trace_pl011_can_receive(s->lcr, s->read_count, r);
- self.read_count < self.fifo_depth()
- }
-
- pub fn receive(&mut self, ch: u32) {
- if !self.loopback_enabled() && self.put_fifo(ch) {
- self.update();
- }
- }
-
- pub fn event(&mut self, event: QEMUChrEvent) {
- if event =3D=3D QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_en=
abled() {
- let update =3D self.put_fifo(registers::Data::BREAK.into());
- if update {
- self.update();
- }
- }
- }
-
#[inline]
pub fn fifo_enabled(&self) -> bool {
self.line_control.fifos_enabled() =3D=3D registers::Mode::FIFO
@@ -539,14 +460,7 @@ pub fn put_fifo(&mut self, value: u32) -> bool {
false
}
=20
- pub fn update(&self) {
- let flags =3D self.int_level & self.int_enabled;
- for (irq, i) in self.interrupts.iter().zip(IRQMASK) {
- irq.set(flags & i !=3D 0);
- }
- }
-
- pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> {
+ pub fn post_load(&mut self) -> Result<(), ()> {
/* Sanity-check input state */
if self.read_pos >=3D self.read_fifo.len() || self.read_count > se=
lf.read_fifo.len() {
return Err(());
@@ -566,6 +480,63 @@ pub fn post_load(&mut self, _version_id: u32) -> Resul=
t<(), ()> {
=20
Ok(())
}
+}
+
+impl PL011State {
+ /// Initializes a pre-allocated, unitialized instance of `PL011State`.
+ ///
+ /// # Safety
+ ///
+ /// `self` must point to a correctly sized and aligned location for the
+ /// `PL011State` type. It must not be called more than once on the same
+ /// location/instance. All its fields are expected to hold unitialized
+ /// values with the sole exception of `parent_obj`.
+ unsafe fn init(&mut self) {
+ const CLK_NAME: &CStr =3D c_str!("clk");
+
+ // SAFETY:
+ //
+ // self and self.iomem are guaranteed to be valid at this point si=
nce callers
+ // must make sure the `self` reference is valid.
+ unsafe {
+ memory_region_init_io(
+ addr_of_mut!(self.iomem),
+ addr_of_mut!(*self).cast::<Object>(),
+ &PL011_OPS,
+ addr_of_mut!(*self).cast::<c_void>(),
+ Self::TYPE_NAME.as_ptr(),
+ 0x1000,
+ );
+ }
+
+ self.regs =3D Default::default();
+
+ // SAFETY:
+ //
+ // self.clock is not initialized at this point; but since `NonNull=
<_>` is Copy,
+ // we can overwrite the undefined value without side effects. This=
is
+ // safe since all PL011State instances are created by QOM code whi=
ch
+ // calls this function to initialize the fields; therefore no code=
is
+ // able to access an invalid self.clock value.
+ unsafe {
+ let dev: &mut DeviceState =3D self.upcast_mut();
+ self.clock =3D NonNull::new(qdev_init_clock_in(
+ dev,
+ CLK_NAME.as_ptr(),
+ None, /* pl011_clock_update */
+ addr_of_mut!(*self).cast::<c_void>(),
+ ClockEvent::ClockUpdate.0,
+ ))
+ .unwrap();
+ }
+ }
+
+ fn post_init(&self) {
+ self.init_mmio(&self.iomem);
+ for irq in self.interrupts.iter() {
+ self.init_irq(irq);
+ }
+ }
=20
pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow<u64,=
u64> {
let mut update_irq =3D false;
@@ -578,7 +549,7 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> C=
ontrolFlow<u64, u64> {
// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
ControlFlow::Break(0)
}
- Ok(field) =3D> match self.regs_read(field) {
+ Ok(field) =3D> match self.regs.read(field) {
ControlFlow::Break(value) =3D> ControlFlow::Break(value.in=
to()),
ControlFlow::Continue(value) =3D> {
update_irq =3D true;
@@ -595,7 +566,7 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> C=
ontrolFlow<u64, u64> {
pub fn write(&mut self, offset: hwaddr, value: u64) {
let mut update_irq =3D false;
if let Ok(field) =3D RegisterOffset::try_from(offset) {
- update_irq =3D self.regs_write(field, value as u32);
+ update_irq =3D self.regs.write(field, value as u32, &mut self.=
char_backend);
} else {
eprintln!("write bad offset {offset} value {value}");
}
@@ -603,6 +574,64 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
self.update();
}
}
+
+ pub fn can_receive(&self) -> bool {
+ // trace_pl011_can_receive(s->lcr, s->read_count, r);
+ let regs =3D &self.regs;
+ regs.read_count < regs.fifo_depth()
+ }
+
+ pub fn receive(&mut self, ch: u32) {
+ let regs =3D &mut self.regs;
+ let update_irq =3D !regs.loopback_enabled() && regs.put_fifo(ch);
+ if update_irq {
+ self.update();
+ }
+ }
+
+ pub fn event(&mut self, event: QEMUChrEvent) {
+ let mut update_irq =3D false;
+ let regs =3D &mut self.regs;
+ if event =3D=3D QEMUChrEvent::CHR_EVENT_BREAK && !regs.loopback_en=
abled() {
+ update_irq =3D regs.put_fifo(registers::Data::BREAK.into());
+ }
+ if update_irq {
+ self.update()
+ }
+ }
+
+ pub fn realize(&self) {
+ // SAFETY: self.char_backend has the correct size and alignment fo=
r a
+ // CharBackend object, and its callbacks are of the correct types.
+ unsafe {
+ qemu_chr_fe_set_handlers(
+ addr_of!(self.char_backend) as *mut CharBackend,
+ Some(pl011_can_receive),
+ Some(pl011_receive),
+ Some(pl011_event),
+ None,
+ addr_of!(*self).cast::<c_void>() as *mut c_void,
+ core::ptr::null_mut(),
+ true,
+ );
+ }
+ }
+
+ pub fn reset(&mut self) {
+ self.regs.reset();
+ }
+
+ pub fn update(&self) {
+ let regs =3D &self.regs;
+ let flags =3D regs.int_level & regs.int_enabled;
+ for (irq, i) in self.interrupts.iter().zip(IRQMASK) {
+ irq.set(flags & i !=3D 0);
+ }
+ }
+
+ pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> {
+ self.regs.post_load()
+ }
}
=20
/// Which bits in the interrupt status matter for each outbound IRQ line ?
diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr=
c/device_class.rs
index 2336a768729..d94b98de7bb 100644
--- a/rust/hw/char/pl011/src/device_class.rs
+++ b/rust/hw/char/pl011/src/device_class.rs
@@ -6,11 +6,11 @@
use std::os::raw::{c_int, c_void};
=20
use qemu_api::{
- bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_of, vmstate=
_subsections,
- vmstate_unused, zeroable::Zeroable,
+ bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_of, vmstate=
_struct,
+ vmstate_subsections, vmstate_unused, zeroable::Zeroable,
};
=20
-use crate::device::PL011State;
+use crate::device::{PL011Registers, PL011State};
=20
#[allow(clippy::missing_const_for_fn)]
extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> bool {
@@ -40,6 +40,30 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, versi=
on_id: c_int) -> c_int {
}
}
=20
+static VMSTATE_PL011_REGS: VMStateDescription =3D VMStateDescription {
+ name: c_str!("pl011/regs").as_ptr(),
+ version_id: 2,
+ minimum_version_id: 2,
+ fields: vmstate_fields! {
+ vmstate_of!(PL011Registers, flags),
+ vmstate_of!(PL011Registers, line_control),
+ vmstate_of!(PL011Registers, receive_status_error_clear),
+ vmstate_of!(PL011Registers, control),
+ vmstate_of!(PL011Registers, dmacr),
+ vmstate_of!(PL011Registers, int_enabled),
+ vmstate_of!(PL011Registers, int_level),
+ vmstate_of!(PL011Registers, read_fifo),
+ vmstate_of!(PL011Registers, ilpr),
+ vmstate_of!(PL011Registers, ibrd),
+ vmstate_of!(PL011Registers, fbrd),
+ vmstate_of!(PL011Registers, ifl),
+ vmstate_of!(PL011Registers, read_pos),
+ vmstate_of!(PL011Registers, read_count),
+ vmstate_of!(PL011Registers, read_trigger),
+ },
+ ..Zeroable::ZERO
+};
+
pub static VMSTATE_PL011: VMStateDescription =3D VMStateDescription {
name: c_str!("pl011").as_ptr(),
version_id: 2,
@@ -47,21 +71,7 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, versi=
on_id: c_int) -> c_int {
post_load: Some(pl011_post_load),
fields: vmstate_fields! {
vmstate_unused!(core::mem::size_of::<u32>()),
- vmstate_of!(PL011State, flags),
- vmstate_of!(PL011State, line_control),
- vmstate_of!(PL011State, receive_status_error_clear),
- vmstate_of!(PL011State, control),
- vmstate_of!(PL011State, dmacr),
- vmstate_of!(PL011State, int_enabled),
- vmstate_of!(PL011State, int_level),
- vmstate_of!(PL011State, read_fifo),
- vmstate_of!(PL011State, ilpr),
- vmstate_of!(PL011State, ibrd),
- vmstate_of!(PL011State, fbrd),
- vmstate_of!(PL011State, ifl),
- vmstate_of!(PL011State, read_pos),
- vmstate_of!(PL011State, read_count),
- vmstate_of!(PL011State, read_trigger),
+ vmstate_struct!(PL011State, regs, &VMSTATE_PL011_REGS, PL011Regist=
ers),
},
subsections: vmstate_subsections! {
VMSTATE_PL011_CLOCK
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 42/48] rust: pl011: wrap registers with BqlRefCell
Date: Fri, 24 Jan 2025 10:44:36 +0100
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This is a step towards making memory ops use a shared reference to the
device type; it's not yet possible due to the calls to character device
functions.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 40 ++++++++++++++------------
rust/hw/char/pl011/src/device_class.rs | 8 +++---
2 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index f1319d1a8bd..4fd9bdc8584 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -109,14 +109,14 @@ pub struct PL011Registers {
}
=20
#[repr(C)]
-#[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)]
+#[derive(qemu_api_macros::Object, qemu_api_macros::offsets)]
/// PL011 Device Model in QEMU
pub struct PL011State {
pub parent_obj: ParentField<SysBusDevice>,
pub iomem: MemoryRegion,
#[doc(alias =3D "chr")]
pub char_backend: CharBackend,
- pub regs: PL011Registers,
+ pub regs: BqlRefCell<PL011Registers>,
/// QEMU interrupts
///
/// ```text
@@ -538,6 +538,7 @@ fn post_init(&self) {
}
}
=20
+ #[allow(clippy::needless_pass_by_ref_mut)]
pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow<u64,=
u64> {
let mut update_irq =3D false;
let result =3D match RegisterOffset::try_from(offset) {
@@ -549,7 +550,7 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> C=
ontrolFlow<u64, u64> {
// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
ControlFlow::Break(0)
}
- Ok(field) =3D> match self.regs.read(field) {
+ Ok(field) =3D> match self.regs.borrow_mut().read(field) {
ControlFlow::Break(value) =3D> ControlFlow::Break(value.in=
to()),
ControlFlow::Continue(value) =3D> {
update_irq =3D true;
@@ -566,7 +567,10 @@ pub fn read(&mut self, offset: hwaddr, _size: u32) -> =
ControlFlow<u64, u64> {
pub fn write(&mut self, offset: hwaddr, value: u64) {
let mut update_irq =3D false;
if let Ok(field) =3D RegisterOffset::try_from(offset) {
- update_irq =3D self.regs.write(field, value as u32, &mut self.=
char_backend);
+ update_irq =3D self
+ .regs
+ .borrow_mut()
+ .write(field, value as u32, &mut self.char_backend);
} else {
eprintln!("write bad offset {offset} value {value}");
}
@@ -577,21 +581,21 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
=20
pub fn can_receive(&self) -> bool {
// trace_pl011_can_receive(s->lcr, s->read_count, r);
- let regs =3D &self.regs;
+ let regs =3D self.regs.borrow();
regs.read_count < regs.fifo_depth()
}
=20
- pub fn receive(&mut self, ch: u32) {
- let regs =3D &mut self.regs;
+ pub fn receive(&self, ch: u32) {
+ let mut regs =3D self.regs.borrow_mut();
let update_irq =3D !regs.loopback_enabled() && regs.put_fifo(ch);
if update_irq {
self.update();
}
}
=20
- pub fn event(&mut self, event: QEMUChrEvent) {
+ pub fn event(&self, event: QEMUChrEvent) {
let mut update_irq =3D false;
- let regs =3D &mut self.regs;
+ let mut regs =3D self.regs.borrow_mut();
if event =3D=3D QEMUChrEvent::CHR_EVENT_BREAK && !regs.loopback_en=
abled() {
update_irq =3D regs.put_fifo(registers::Data::BREAK.into());
}
@@ -618,19 +622,19 @@ pub fn realize(&self) {
}
=20
pub fn reset(&mut self) {
- self.regs.reset();
+ self.regs.borrow_mut().reset();
}
=20
pub fn update(&self) {
- let regs =3D &self.regs;
+ let regs =3D self.regs.borrow();
let flags =3D regs.int_level & regs.int_enabled;
for (irq, i) in self.interrupts.iter().zip(IRQMASK) {
irq.set(flags & i !=3D 0);
}
}
=20
- pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> {
- self.regs.post_load()
+ pub fn post_load(&self, _version_id: u32) -> Result<(), ()> {
+ self.regs.borrow_mut().post_load()
}
}
=20
@@ -667,11 +671,11 @@ pub fn post_load(&mut self, _version_id: u32) -> Resu=
lt<(), ()> {
///
/// The buffer and size arguments must also be valid.
pub unsafe extern "C" fn pl011_receive(opaque: *mut c_void, buf: *const u8=
, size: c_int) {
- let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ let state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
unsafe {
if size > 0 {
debug_assert!(!buf.is_null());
- state.as_mut().receive(u32::from(buf.read_volatile()));
+ state.as_ref().receive(u32::from(buf.read_volatile()));
}
}
}
@@ -682,8 +686,8 @@ pub fn post_load(&mut self, _version_id: u32) -> Result=
<(), ()> {
/// the same size as [`PL011State`]. We also expect the device is
/// readable/writeable from one thread at any time.
pub unsafe extern "C" fn pl011_event(opaque: *mut c_void, event: QEMUChrEv=
ent) {
- let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
- unsafe { state.as_mut().event(event) }
+ let state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ unsafe { state.as_ref().event(event) }
}
=20
/// # Safety
@@ -708,7 +712,7 @@ pub fn post_load(&mut self, _version_id: u32) -> Result=
<(), ()> {
}
=20
#[repr(C)]
-#[derive(Debug, qemu_api_macros::Object)]
+#[derive(qemu_api_macros::Object)]
/// PL011 Luminary device model.
pub struct PL011Luminary {
parent_obj: ParentField<PL011State>,
diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/sr=
c/device_class.rs
index d94b98de7bb..8a157a663fb 100644
--- a/rust/hw/char/pl011/src/device_class.rs
+++ b/rust/hw/char/pl011/src/device_class.rs
@@ -6,7 +6,7 @@
use std::os::raw::{c_int, c_void};
=20
use qemu_api::{
- bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_of, vmstate=
_struct,
+ bindings::*, c_str, prelude::*, vmstate_clock, vmstate_fields, vmstate=
_of, vmstate_struct,
vmstate_subsections, vmstate_unused, zeroable::Zeroable,
};
=20
@@ -31,8 +31,8 @@ extern "C" fn pl011_clock_needed(opaque: *mut c_void) -> =
bool {
};
=20
extern "C" fn pl011_post_load(opaque: *mut c_void, version_id: c_int) -> c=
_int {
- let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
- let result =3D unsafe { state.as_mut().post_load(version_id as u32) };
+ let state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
+ let result =3D unsafe { state.as_ref().post_load(version_id as u32) };
if result.is_err() {
-1
} else {
@@ -71,7 +71,7 @@ extern "C" fn pl011_post_load(opaque: *mut c_void, versio=
n_id: c_int) -> c_int {
post_load: Some(pl011_post_load),
fields: vmstate_fields! {
vmstate_unused!(core::mem::size_of::<u32>()),
- vmstate_struct!(PL011State, regs, &VMSTATE_PL011_REGS, PL011Regist=
ers),
+ vmstate_struct!(PL011State, regs, &VMSTATE_PL011_REGS, BqlRefCell<=
PL011Registers>),
},
subsections: vmstate_subsections! {
VMSTATE_PL011_CLOCK
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 43/48] rust: pl011: remove duplicate definitions
Date: Fri, 24 Jan 2025 10:44:37 +0100
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Unify the "Interrupt" enum and the "INT_*" constants with a struct
that contains the bits. The "int_level" and "int_enabled" fields
could use a crate such as "bitflags".
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 32 ++++++++++------------
rust/hw/char/pl011/src/lib.rs | 46 +++++++++++---------------------
2 files changed, 29 insertions(+), 49 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 4fd9bdc8584..eab3cf96f4c 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -191,7 +191,7 @@ pub(self) fn read(&mut self, offset: RegisterOffset) ->=
ControlFlow<u32, u32> {
self.flags.set_receive_fifo_empty(true);
}
if self.read_count + 1 =3D=3D self.read_trigger {
- self.int_level &=3D !registers::INT_RX;
+ self.int_level &=3D !Interrupt::RX.0;
}
// Update error bits.
self.receive_status_error_clear.set_from_data(c);
@@ -240,7 +240,7 @@ pub(self) fn write(
}
// interrupts always checked
let _ =3D self.loopback_tx(value);
- self.int_level |=3D registers::INT_TX;
+ self.int_level |=3D Interrupt::TX.0;
return true;
}
RSR =3D> {
@@ -364,19 +364,19 @@ fn loopback_mdmctrl(&mut self) -> bool {
// Change interrupts based on updated FR
let mut il =3D self.int_level;
=20
- il &=3D !Interrupt::MS;
+ il &=3D !Interrupt::MS.0;
=20
if self.flags.data_set_ready() {
- il |=3D Interrupt::DSR as u32;
+ il |=3D Interrupt::DSR.0;
}
if self.flags.data_carrier_detect() {
- il |=3D Interrupt::DCD as u32;
+ il |=3D Interrupt::DCD.0;
}
if self.flags.clear_to_send() {
- il |=3D Interrupt::CTS as u32;
+ il |=3D Interrupt::CTS.0;
}
if self.flags.ring_indicator() {
- il |=3D Interrupt::RI as u32;
+ il |=3D Interrupt::RI.0;
}
self.int_level =3D il;
true
@@ -454,7 +454,7 @@ pub fn put_fifo(&mut self, value: u32) -> bool {
}
=20
if self.read_count =3D=3D self.read_trigger {
- self.int_level |=3D registers::INT_RX;
+ self.int_level |=3D Interrupt::RX.0;
return true;
}
false
@@ -641,16 +641,12 @@ pub fn post_load(&self, _version_id: u32) -> Result<(=
), ()> {
/// Which bits in the interrupt status matter for each outbound IRQ line ?
const IRQMASK: [u32; 6] =3D [
/* combined IRQ */
- Interrupt::E
- | Interrupt::MS
- | Interrupt::RT as u32
- | Interrupt::TX as u32
- | Interrupt::RX as u32,
- Interrupt::RX as u32,
- Interrupt::TX as u32,
- Interrupt::RT as u32,
- Interrupt::MS,
- Interrupt::E,
+ Interrupt::E.0 | Interrupt::MS.0 | Interrupt::RT.0 | Interrupt::TX.0 |=
Interrupt::RX.0,
+ Interrupt::RX.0,
+ Interrupt::TX.0,
+ Interrupt::RT.0,
+ Interrupt::MS.0,
+ Interrupt::E.0,
];
=20
/// # Safety
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index 2baacba2306..300c732ae1d 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -100,7 +100,6 @@ enum RegisterOffset {
//Reserved =3D 0x04C,
}
=20
-#[allow(dead_code)]
mod registers {
//! Device registers exposed as typed structs which are backed by arbi=
trary
//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
@@ -521,38 +520,23 @@ fn default() -> Self {
}
=20
/// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
- pub const INT_OE: u32 =3D 1 << 10;
- pub const INT_BE: u32 =3D 1 << 9;
- pub const INT_PE: u32 =3D 1 << 8;
- pub const INT_FE: u32 =3D 1 << 7;
- pub const INT_RT: u32 =3D 1 << 6;
- pub const INT_TX: u32 =3D 1 << 5;
- pub const INT_RX: u32 =3D 1 << 4;
- pub const INT_DSR: u32 =3D 1 << 3;
- pub const INT_DCD: u32 =3D 1 << 2;
- pub const INT_CTS: u32 =3D 1 << 1;
- pub const INT_RI: u32 =3D 1 << 0;
- pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE;
- pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS;
-
- #[repr(u32)]
- pub enum Interrupt {
- OE =3D 1 << 10,
- BE =3D 1 << 9,
- PE =3D 1 << 8,
- FE =3D 1 << 7,
- RT =3D 1 << 6,
- TX =3D 1 << 5,
- RX =3D 1 << 4,
- DSR =3D 1 << 3,
- DCD =3D 1 << 2,
- CTS =3D 1 << 1,
- RI =3D 1 << 0,
- }
+ pub struct Interrupt(pub u32);
=20
impl Interrupt {
- pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE;
- pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS;
+ pub const OE: Self =3D Self(1 << 10);
+ pub const BE: Self =3D Self(1 << 9);
+ pub const PE: Self =3D Self(1 << 8);
+ pub const FE: Self =3D Self(1 << 7);
+ pub const RT: Self =3D Self(1 << 6);
+ pub const TX: Self =3D Self(1 << 5);
+ pub const RX: Self =3D Self(1 << 4);
+ pub const DSR: Self =3D Self(1 << 3);
+ pub const DCD: Self =3D Self(1 << 2);
+ pub const CTS: Self =3D Self(1 << 1);
+ pub const RI: Self =3D Self(1 << 0);
+
+ pub const E: Self =3D Self(Self::OE.0 | Self::BE.0 | Self::PE.0 | =
Self::FE.0);
+ pub const MS: Self =3D Self(Self::RI.0 | Self::DSR.0 | Self::DCD.0=
| Self::CTS.0);
}
}
=20
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 44/48] rust: pl011: pull device-specific code out of
MemoryRegionOps callbacks
Date: Fri, 24 Jan 2025 10:44:38 +0100
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read() can now return a simple u64.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 23 +++++++++++++----------
rust/hw/char/pl011/src/memory_ops.rs | 18 ++----------------
2 files changed, 15 insertions(+), 26 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index eab3cf96f4c..9a0ba87aa5b 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -12,9 +12,10 @@
use qemu_api::{
bindings::{
error_fatal, hwaddr, memory_region_init_io, qdev_init_clock_in, qd=
ev_new,
- qdev_prop_set_chr, qemu_chr_fe_ioctl, qemu_chr_fe_set_handlers, qe=
mu_chr_fe_write_all,
- qemu_irq, sysbus_connect_irq, sysbus_mmio_map, sysbus_realize_and_=
unref, CharBackend,
- Chardev, Clock, ClockEvent, MemoryRegion, QEMUChrEvent, CHR_IOCTL_=
SERIAL_SET_BREAK,
+ qdev_prop_set_chr, qemu_chr_fe_accept_input, qemu_chr_fe_ioctl, qe=
mu_chr_fe_set_handlers,
+ qemu_chr_fe_write_all, qemu_irq, sysbus_connect_irq, sysbus_mmio_m=
ap,
+ sysbus_realize_and_unref, CharBackend, Chardev, Clock, ClockEvent,=
MemoryRegion,
+ QEMUChrEvent, CHR_IOCTL_SERIAL_SET_BREAK,
},
c_str, impl_vmstate_forward,
irq::InterruptSource,
@@ -538,30 +539,32 @@ fn post_init(&self) {
}
}
=20
- #[allow(clippy::needless_pass_by_ref_mut)]
- pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow<u64,=
u64> {
+ pub fn read(&mut self, offset: hwaddr, _size: u32) -> u64 {
let mut update_irq =3D false;
let result =3D match RegisterOffset::try_from(offset) {
Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> {
let device_id =3D self.get_class().device_id;
- ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >>=
2]))
+ u32::from(device_id[(offset - 0xfe0) >> 2])
}
Err(_) =3D> {
// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
- ControlFlow::Break(0)
+ 0
}
Ok(field) =3D> match self.regs.borrow_mut().read(field) {
- ControlFlow::Break(value) =3D> ControlFlow::Break(value.in=
to()),
+ ControlFlow::Break(value) =3D> value,
ControlFlow::Continue(value) =3D> {
update_irq =3D true;
- ControlFlow::Continue(value.into())
+ value
}
},
};
if update_irq {
self.update();
+ unsafe {
+ qemu_chr_fe_accept_input(&mut self.char_backend);
+ }
}
- result
+ result.into()
}
=20
pub fn write(&mut self, offset: hwaddr, value: u64) {
diff --git a/rust/hw/char/pl011/src/memory_ops.rs b/rust/hw/char/pl011/src/=
memory_ops.rs
index a286003d136..432d3263898 100644
--- a/rust/hw/char/pl011/src/memory_ops.rs
+++ b/rust/hw/char/pl011/src/memory_ops.rs
@@ -24,25 +24,11 @@
};
=20
unsafe extern "C" fn pl011_read(opaque: *mut c_void, addr: hwaddr, size: c=
_uint) -> u64 {
- assert!(!opaque.is_null());
let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
- let val =3D unsafe { state.as_mut().read(addr, size) };
- match val {
- std::ops::ControlFlow::Break(val) =3D> val,
- std::ops::ControlFlow::Continue(val) =3D> {
- // SAFETY: self.char_backend is a valid CharBackend instance a=
fter it's been
- // initialized in realize().
- let cb_ptr =3D unsafe { core::ptr::addr_of_mut!(state.as_mut()=
.char_backend) };
- unsafe {
- qemu_chr_fe_accept_input(cb_ptr);
- }
-
- val
- }
- }
+ unsafe { state.as_mut() }.read(addr, size)
}
=20
unsafe extern "C" fn pl011_write(opaque: *mut c_void, addr: hwaddr, data: =
u64, _size: c_uint) {
let mut state =3D NonNull::new(opaque).unwrap().cast::<PL011State>();
- unsafe { state.as_mut().write(addr, data) }
+ unsafe { state.as_mut() }.write(addr, data);
}
--=20
2.48.1
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 45/48] rust: pl011: drop use of ControlFlow
Date: Fri, 24 Jan 2025 10:44:39 +0100
Message-ID: <20250124094442.13207-46-pbonzini@redhat.com>
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It is a poor match for what the code is doing, anyway.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 39 +++++++++++++++-----------------
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index 9a0ba87aa5b..e916ea11884 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -5,7 +5,6 @@
use core::ptr::{addr_of, addr_of_mut, NonNull};
use std::{
ffi::CStr,
- ops::ControlFlow,
os::raw::{c_int, c_void},
};
=20
@@ -177,10 +176,11 @@ fn vmsd() -> Option<&'static VMStateDescription> {
}
=20
impl PL011Registers {
- pub(self) fn read(&mut self, offset: RegisterOffset) -> ControlFlow<u3=
2, u32> {
+ pub(self) fn read(&mut self, offset: RegisterOffset) -> (bool, u32) {
use RegisterOffset::*;
=20
- ControlFlow::Break(match offset {
+ let mut update =3D false;
+ let result =3D match offset {
DR =3D> {
self.flags.set_receive_fifo_full(false);
let c =3D self.read_fifo[self.read_pos];
@@ -196,8 +196,9 @@ pub(self) fn read(&mut self, offset: RegisterOffset) ->=
ControlFlow<u32, u32> {
}
// Update error bits.
self.receive_status_error_clear.set_from_data(c);
- // Must call qemu_chr_fe_accept_input, so return Continue:
- return ControlFlow::Continue(u32::from(c));
+ // Must call qemu_chr_fe_accept_input
+ update =3D true;
+ u32::from(c)
}
RSR =3D> u32::from(self.receive_status_error_clear),
FR =3D> u32::from(self.flags),
@@ -216,7 +217,8 @@ pub(self) fn read(&mut self, offset: RegisterOffset) ->=
ControlFlow<u32, u32> {
0
}
DMACR =3D> self.dmacr,
- })
+ };
+ (update, result)
}
=20
pub(self) fn write(
@@ -540,31 +542,26 @@ fn post_init(&self) {
}
=20
pub fn read(&mut self, offset: hwaddr, _size: u32) -> u64 {
- let mut update_irq =3D false;
- let result =3D match RegisterOffset::try_from(offset) {
+ match RegisterOffset::try_from(offset) {
Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> {
let device_id =3D self.get_class().device_id;
- u32::from(device_id[(offset - 0xfe0) >> 2])
+ u64::from(device_id[(offset - 0xfe0) >> 2])
}
Err(_) =3D> {
// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset =
0x%x\n", (int)offset);
0
}
- Ok(field) =3D> match self.regs.borrow_mut().read(field) {
- ControlFlow::Break(value) =3D> value,
- ControlFlow::Continue(value) =3D> {
- update_irq =3D true;
- value
+ Ok(field) =3D> {
+ let (update_irq, result) =3D self.regs.borrow_mut().read(f=
ield);
+ if update_irq {
+ self.update();
+ unsafe {
+ qemu_chr_fe_accept_input(&mut self.char_backend);
+ }
}
- },
- };
- if update_irq {
- self.update();
- unsafe {
- qemu_chr_fe_accept_input(&mut self.char_backend);
+ result.into()
}
}
- result.into()
}
=20
pub fn write(&mut self, offset: hwaddr, value: u64) {
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Subject: [PULL 46/48] rust: qdev: make reset take a shared reference
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Because register reset is within a borrow_mut() call, reset
does not need anymore a mut reference to the PL011State.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 4 ++--
rust/qemu-api/src/qdev.rs | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi=
ce.rs
index e916ea11884..fad190a9133 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -172,7 +172,7 @@ fn vmsd() -> Option<&'static VMStateDescription> {
Some(&device_class::VMSTATE_PL011)
}
const REALIZE: Option<fn(&Self)> =3D Some(Self::realize);
- const RESET: Option<fn(&mut Self)> =3D Some(Self::reset);
+ const RESET: Option<fn(&Self)> =3D Some(Self::reset);
}
=20
impl PL011Registers {
@@ -621,7 +621,7 @@ pub fn realize(&self) {
}
}
=20
- pub fn reset(&mut self) {
+ pub fn reset(&self) {
self.regs.borrow_mut().reset();
}
=20
diff --git a/rust/qemu-api/src/qdev.rs b/rust/qemu-api/src/qdev.rs
index 42429903aae..f4c75c752f1 100644
--- a/rust/qemu-api/src/qdev.rs
+++ b/rust/qemu-api/src/qdev.rs
@@ -30,7 +30,7 @@ pub trait DeviceImpl {
///
/// Rust does not yet support the three-phase reset protocol; this is
/// usually okay for leaf classes.
- const RESET: Option<fn(&mut Self)> =3D None;
+ const RESET: Option<fn(&Self)> =3D None;
=20
/// An array providing the properties that the user can set on the
/// device. Not a `const` because referencing statics in constants
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 47/48] rust/zeroable: Implement Zeroable with const_zero macro
Date: Fri, 24 Jan 2025 10:44:41 +0100
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The `const_zero` crate provides a nice macro to zero type-specific
constants, which doesn't need to enumerates the fields one by one.
Introduce the `const_zero` macro to QEMU (along with its documentation), and
use it to simplify the implementation of `Zeroable` trait.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250123163143.679841-1-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/src/zeroable.rs | 137 +++++++++++++++-------------------
1 file changed, 61 insertions(+), 76 deletions(-)
diff --git a/rust/qemu-api/src/zeroable.rs b/rust/qemu-api/src/zeroable.rs
index 57cac96de06..7b04947cb6c 100644
--- a/rust/qemu-api/src/zeroable.rs
+++ b/rust/qemu-api/src/zeroable.rs
@@ -1,13 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later
=20
-use std::ptr;
-
/// Encapsulates the requirement that
/// `MaybeUninit::<Self>::zeroed().assume_init()` does not cause undefined
/// behavior. This trait in principle could be implemented as just:
///
/// ```
-/// pub unsafe trait Zeroable: Default {
+/// pub unsafe trait Zeroable {
/// const ZERO: Self =3D unsafe { ::core::mem::MaybeUninit::<Self>::ze=
roed().assume_init() };
/// }
/// ```
@@ -29,23 +27,61 @@ pub unsafe trait Zeroable: Default {
const ZERO: Self;
}
=20
-unsafe impl Zeroable for crate::bindings::Property__bindgen_ty_1 {
- const ZERO: Self =3D Self { i: 0 };
+/// A macro that acts similarly to [`core::mem::zeroed()`], only is const
+///
+/// ## Safety
+///
+/// Similar to `core::mem::zeroed()`, except this zeroes padding bits. Zer=
oed
+/// padding usually isn't relevant to safety, but might be if a C union is=
used.
+///
+/// Just like for `core::mem::zeroed()`, an all zero byte pattern might not
+/// be a valid value for a type, as is the case for references `&T` and `&=
mut
+/// T`. Reference types trigger a (denied by default) lint and cause immed=
iate
+/// undefined behavior if the lint is ignored
+///
+/// ```rust compile_fail
+/// use const_zero::const_zero;
+/// // error: any use of this value will cause an error
+/// // note: `#[deny(const_err)]` on by default
+/// const STR: &str =3D unsafe{const_zero!(&'static str)};
+/// ```
+///
+/// `const_zero` does not work on unsized types:
+///
+/// ```rust compile_fail
+/// use const_zero::const_zero;
+/// // error[E0277]: the size for values of type `[u8]` cannot be known at=
compilation time
+/// const BYTES: [u8] =3D unsafe{const_zero!([u8])};
+/// ```
+/// ## Differences with `core::mem::zeroed`
+///
+/// `const_zero` zeroes padding bits, while `core::mem::zeroed` doesn't
+macro_rules! const_zero {
+ // This macro to produce a type-generic zero constant is taken from the
+ // const_zero crate (v0.1.1):
+ //
+ // https://docs.rs/const-zero/latest/src/const_zero/lib.rs.html
+ //
+ // and used under MIT license
+ ($type_:ty) =3D> {{
+ const TYPE_SIZE: ::core::primitive::usize =3D ::core::mem::size_of=
::<$type_>();
+ union TypeAsBytes {
+ bytes: [::core::primitive::u8; TYPE_SIZE],
+ inner: ::core::mem::ManuallyDrop<$type_>,
+ }
+ const ZERO_BYTES: TypeAsBytes =3D TypeAsBytes {
+ bytes: [0; TYPE_SIZE],
+ };
+ ::core::mem::ManuallyDrop::<$type_>::into_inner(ZERO_BYTES.inner)
+ }};
}
=20
-unsafe impl Zeroable for crate::bindings::Property {
- const ZERO: Self =3D Self {
- name: ptr::null(),
- info: ptr::null(),
- offset: 0,
- bitnr: 0,
- bitmask: 0,
- set_default: false,
- defval: Zeroable::ZERO,
- arrayoffset: 0,
- arrayinfo: ptr::null(),
- arrayfieldsize: 0,
- link_type: ptr::null(),
+/// A wrapper to implement the `Zeroable` trait through the `const_zero` m=
acro.
+macro_rules! impl_zeroable {
+ ($type:ty) =3D> {
+ unsafe impl Zeroable for $type {
+ const ZERO: Self =3D unsafe { const_zero!($type) };
+ }
};
}
=20
@@ -57,61 +93,10 @@ fn default() -> Self {
}
}
=20
-unsafe impl Zeroable for crate::bindings::VMStateFlags {
- const ZERO: Self =3D Self(0);
-}
-
-unsafe impl Zeroable for crate::bindings::VMStateField {
- const ZERO: Self =3D Self {
- name: ptr::null(),
- err_hint: ptr::null(),
- offset: 0,
- size: 0,
- start: 0,
- num: 0,
- num_offset: 0,
- size_offset: 0,
- info: ptr::null(),
- flags: Zeroable::ZERO,
- vmsd: ptr::null(),
- version_id: 0,
- struct_version_id: 0,
- field_exists: None,
- };
-}
-
-unsafe impl Zeroable for crate::bindings::VMStateDescription {
- const ZERO: Self =3D Self {
- name: ptr::null(),
- unmigratable: false,
- early_setup: false,
- version_id: 0,
- minimum_version_id: 0,
- priority: crate::bindings::MigrationPriority::MIG_PRI_DEFAULT,
- pre_load: None,
- post_load: None,
- pre_save: None,
- post_save: None,
- needed: None,
- dev_unplug_pending: None,
- fields: ptr::null(),
- subsections: ptr::null(),
- };
-}
-
-unsafe impl Zeroable for crate::bindings::MemoryRegionOps__bindgen_ty_1 {
- const ZERO: Self =3D Self {
- min_access_size: 0,
- max_access_size: 0,
- unaligned: false,
- accepts: None,
- };
-}
-
-unsafe impl Zeroable for crate::bindings::MemoryRegionOps__bindgen_ty_2 {
- const ZERO: Self =3D Self {
- min_access_size: 0,
- max_access_size: 0,
- unaligned: false,
- };
-}
+impl_zeroable!(crate::bindings::Property__bindgen_ty_1);
+impl_zeroable!(crate::bindings::Property);
+impl_zeroable!(crate::bindings::VMStateFlags);
+impl_zeroable!(crate::bindings::VMStateField);
+impl_zeroable!(crate::bindings::VMStateDescription);
+impl_zeroable!(crate::bindings::MemoryRegionOps__bindgen_ty_1);
+impl_zeroable!(crate::bindings::MemoryRegionOps__bindgen_ty_2);
--=20
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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 48/48] rust: qemu-api: add sub-subclass to the integration
tests
Date: Fri, 24 Jan 2025 10:44:42 +0100
Message-ID: <20250124094442.13207-49-pbonzini@redhat.com>
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Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/qemu-api/tests/tests.rs | 56 ++++++++++++++++++++++++++++++++++--
1 file changed, 53 insertions(+), 3 deletions(-)
diff --git a/rust/qemu-api/tests/tests.rs b/rust/qemu-api/tests/tests.rs
index 526c3f4f8ea..5c3e75ed3d5 100644
--- a/rust/qemu-api/tests/tests.rs
+++ b/rust/qemu-api/tests/tests.rs
@@ -14,8 +14,8 @@
cell::{self, BqlCell},
declare_properties, define_property,
prelude::*,
- qdev::{DeviceImpl, DeviceState, Property},
- qom::{ObjectImpl, ParentField},
+ qdev::{DeviceClass, DeviceImpl, DeviceState, Property},
+ qom::{ClassInitImpl, ObjectImpl, ParentField},
vmstate::VMStateDescription,
zeroable::Zeroable,
};
@@ -37,6 +37,10 @@ pub struct DummyState {
=20
qom_isa!(DummyState: Object, DeviceState);
=20
+pub struct DummyClass {
+ parent_class: <DeviceState as ObjectType>::Class,
+}
+
declare_properties! {
DUMMY_PROPERTIES,
define_property!(
@@ -49,7 +53,7 @@ pub struct DummyState {
}
=20
unsafe impl ObjectType for DummyState {
- type Class =3D <DeviceState as ObjectType>::Class;
+ type Class =3D DummyClass;
const TYPE_NAME: &'static CStr =3D c_str!("dummy");
}
=20
@@ -67,6 +71,51 @@ fn vmsd() -> Option<&'static VMStateDescription> {
}
}
=20
+// `impl<T> ClassInitImpl<DummyClass> for T` doesn't work since it violates
+// orphan rule.
+impl ClassInitImpl<DummyClass> for DummyState {
+ fn class_init(klass: &mut DummyClass) {
+ <Self as ClassInitImpl<DeviceClass>>::class_init(&mut klass.parent=
_class);
+ }
+}
+
+#[derive(qemu_api_macros::offsets)]
+#[repr(C)]
+#[derive(qemu_api_macros::Object)]
+pub struct DummyChildState {
+ parent: ParentField<DummyState>,
+}
+
+qom_isa!(DummyChildState: Object, DeviceState, DummyState);
+
+pub struct DummyChildClass {
+ parent_class: <DummyState as ObjectType>::Class,
+}
+
+unsafe impl ObjectType for DummyChildState {
+ type Class =3D DummyChildClass;
+ const TYPE_NAME: &'static CStr =3D c_str!("dummy_child");
+}
+
+impl ObjectImpl for DummyChildState {
+ type ParentType =3D DummyState;
+ const ABSTRACT: bool =3D false;
+}
+
+impl DeviceImpl for DummyChildState {}
+
+impl ClassInitImpl<DummyClass> for DummyChildState {
+ fn class_init(klass: &mut DummyClass) {
+ <Self as ClassInitImpl<DeviceClass>>::class_init(&mut klass.parent=
_class);
+ }
+}
+
+impl ClassInitImpl<DummyChildClass> for DummyChildState {
+ fn class_init(klass: &mut DummyChildClass) {
+ <Self as ClassInitImpl<DummyClass>>::class_init(&mut klass.parent_=
class);
+ }
+}
+
fn init_qom() {
static ONCE: BqlCell<bool> =3D BqlCell::new(false);
=20
@@ -85,6 +134,7 @@ fn test_object_new() {
init_qom();
unsafe {
object_unref(object_new(DummyState::TYPE_NAME.as_ptr()).cast());
+ object_unref(object_new(DummyChildState::TYPE_NAME.as_ptr()).cast(=
));
}
}
=20
--=20
2.48.1