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Wed, 22 Jan 2025 09:17:48 -0800 (PST) From: Tomita Moeko To: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: qemu-devel@nongnu.org, Tomita Moeko Subject: [PATCH 1/4] vfio/igd: remove GTT write quirk in IO BAR 4 Date: Thu, 23 Jan 2025 01:17:28 +0800 Message-ID: <20250122171731.40444-2-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122171731.40444-1-tomitamoeko@gmail.com> References: <20250122171731.40444-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=tomitamoeko@gmail.com; helo=mail-pj1-x1044.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1737566316555019000 Content-Type: text/plain; charset="utf-8" The IO BAR4 of IGD devices contains a pair of 32-bit address/data registers, MMIO_Index (0x0) and MMIO_Data (0x4), which provide access to the MMIO BAR0 (GTTMMADR) from IO space. These registers are probably only used by the VBIOS, and are not documented by intel. The observed layout of MMIO_Index register is: 31 2 1 0 +-------------------------------------------------------------------+ | Offset | Rsvd | Sel | +-------------------------------------------------------------------+ - Offset: Byte offset in specified region, 4-byte aligned. - Sel: Region selector 0: MMIO register region (first half of MMIO BAR0) 1: GTT region (second half of MMIO BAR0). Pre Gen11 only. Currently, QEMU implements a quirk that adjusts the guest Data Stolen Memory (DSM) region address to be (addr - host BDSM + guest BDSM) when programming GTT entries via IO BAR4, assuming guest still programs GTT with host DSM address, which is not the case. Guest's BDSM register is emulated and initialized to 0 at startup by QEMU, then SeaBIOS programs its value[1]. As result, the address programmed to GTT entries by VBIOS running in guest are valid GPA, and this unnecessary adjustment brings inconsistency. [1] https://gitlab.com/qemu-project/seabios/-/blob/1.12-stable/src/fw/pciin= it.c#L319-332 Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 191 +------------------------------------------------- 1 file changed, 1 insertion(+), 190 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index a77cd09289..4f9a90f36f 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -106,12 +106,6 @@ static int igd_gen(VFIOPCIDevice *vdev) return -1; } =20 -typedef struct VFIOIGDQuirk { - struct VFIOPCIDevice *vdev; - uint32_t index; - uint64_t bdsm; -} VFIOIGDQuirk; - #define IGD_GMCH 0x50 /* Graphics Control Register */ #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and la= ter */ @@ -300,129 +294,6 @@ static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev, return ret; } =20 -/* - * IGD Gen8 and newer support up to 8MB for the GTT and use a 64bit PTE - * entry, older IGDs use 2MB and 32bit. Each PTE maps a 4k page. Therefo= re - * we either have 2M/4k * 4 =3D 2k or 8M/4k * 8 =3D 16k as the maximum iob= ar index - * for programming the GTT. - * - * See linux:include/drm/i915_drm.h for shift and mask values. - */ -static int vfio_igd_gtt_max(VFIOPCIDevice *vdev) -{ - uint32_t gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, sizeof(g= mch)); - int gen =3D igd_gen(vdev); - uint64_t ggms_size =3D igd_gtt_memory_size(gen, gmch); - - return (ggms_size / (4 * KiB)) * (gen < 8 ? 4 : 8); -} - -/* - * The IGD ROM will make use of stolen memory (GGMS) for support of VESA m= odes. - * Somehow the host stolen memory range is used for this, but how the ROM = gets - * it is a mystery, perhaps it's hardcoded into the ROM. Thankfully thoug= h, it - * reprograms the GTT through the IOBAR where we can trap it and transpose= the - * programming to the VM allocated buffer. That buffer gets reserved by t= he VM - * firmware via the fw_cfg entry added below. Here we're just monitoring = the - * IOBAR address and data registers to detect a write sequence targeting t= he - * GTTADR. This code is developed by observed behavior and doesn't have a - * direct spec reference, unfortunately. - */ -static uint64_t vfio_igd_quirk_data_read(void *opaque, - hwaddr addr, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D ~0; - - return vfio_region_read(&vdev->bars[4].region, addr + 4, size); -} - -static void vfio_igd_quirk_data_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - uint64_t val =3D data; - int gen =3D igd_gen(vdev); - - /* - * Programming the GGMS starts at index 0x1 and uses every 4th index (= ie. - * 0x1, 0x5, 0x9, 0xd,...). For pre-Gen8 each 4-byte write is a whole= PTE - * entry, with 0th bit enable set. For Gen8 and up, PTEs are 64bit, so - * entries 0x5 & 0xd are the high dword, in our case zero. Each PTE p= oints - * to a 4k page, which we translate to a page from the VM allocated re= gion, - * pointed to by the BDSM register. If this is not set, we fail. - * - * We trap writes to the full configured GTT size, but we typically on= ly - * see the vBIOS writing up to (nearly) the 1MB barrier. In fact it o= ften - * seems to miss the last entry for an even 1MB GTT. Doing a gratuito= us - * write of that last entry does work, but is hopefully unnecessary si= nce - * we clear the previous GTT on initialization. - */ - if ((igd->index % 4 =3D=3D 1) && igd->index < vfio_igd_gtt_max(vdev)) { - if (gen < 8 || (igd->index % 8 =3D=3D 1)) { - uint64_t base; - - if (gen < 11) { - base =3D pci_get_long(vdev->pdev.config + IGD_BDSM); - } else { - base =3D pci_get_quad(vdev->pdev.config + IGD_BDSM_GEN11); - } - if (!base) { - hw_error("vfio-igd: Guest attempted to program IGD GTT bef= ore " - "BIOS reserved stolen memory. Unsupported BIOS?"= ); - } - - val =3D data - igd->bdsm + base; - } else { - val =3D 0; /* upper 32bits of pte, we only enable below 4G PTE= s */ - } - - trace_vfio_pci_igd_bar4_write(vdev->vbasedev.name, - igd->index, data, val); - } - - vfio_region_write(&vdev->bars[4].region, addr + 4, val, size); - - igd->index =3D ~0; -} - -static const MemoryRegionOps vfio_igd_data_quirk =3D { - .read =3D vfio_igd_quirk_data_read, - .write =3D vfio_igd_quirk_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static uint64_t vfio_igd_quirk_index_read(void *opaque, - hwaddr addr, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D ~0; - - return vfio_region_read(&vdev->bars[4].region, addr, size); -} - -static void vfio_igd_quirk_index_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D data; - - vfio_region_write(&vdev->bars[4].region, addr, data, size); -} - -static const MemoryRegionOps vfio_igd_index_quirk =3D { - .read =3D vfio_igd_quirk_index_read, - .write =3D vfio_igd_quirk_index_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - #define IGD_GGC_MMIO_OFFSET 0x108040 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 =20 @@ -494,14 +365,11 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, i= nt nr) g_autofree struct vfio_region_info *opregion =3D NULL; g_autofree struct vfio_region_info *host =3D NULL; g_autofree struct vfio_region_info *lpc =3D NULL; - VFIOQuirk *quirk; - VFIOIGDQuirk *igd; PCIDevice *lpc_bridge; - int i, ret, gen; + int ret, gen; uint64_t ggms_size, gms_size; uint64_t *bdsm_size; uint32_t gmch; - uint16_t cmd_orig, cmd; Error *err =3D NULL; =20 /* @@ -634,32 +502,6 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, in= t nr) return; } =20 - /* Setup our quirk to munge GTT addresses to the VM allocated buffer */ - quirk =3D vfio_quirk_alloc(2); - igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); - igd->vdev =3D vdev; - igd->index =3D ~0; - if (gen < 11) { - igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); - } else { - igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM_GEN11, 4); - igd->bdsm |=3D - (uint64_t)vfio_pci_read_config(&vdev->pdev, IGD_BDSM_GEN11 + 4= , 4) << 32; - } - igd->bdsm &=3D ~((1 * MiB) - 1); /* 1MB aligned */ - - memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_qu= irk, - igd, "vfio-igd-index-quirk", 4); - memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, - 0, &quirk->mem[0], 1); - - memory_region_init_io(&quirk->mem[1], OBJECT(vdev), &vfio_igd_data_qui= rk, - igd, "vfio-igd-data-quirk", 4); - memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, - 4, &quirk->mem[1], 1); - - QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); - /* * Allow user to override dsm size using x-igd-gms option, in multiple= s of * 32MiB. This option should only be used when the desired size cannot= be @@ -717,37 +559,6 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, in= t nr) pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); } =20 - /* - * This IOBAR gives us access to GTTADR, which allows us to write to - * the GTT itself. So let's go ahead and write zero to all the GTT - * entries to avoid spurious DMA faults. Be sure I/O access is enabled - * before talking to the device. - */ - if (pread(vdev->vbasedev.fd, &cmd_orig, sizeof(cmd_orig), - vdev->config_offset + PCI_COMMAND) !=3D sizeof(cmd_orig)) { - error_report("IGD device %s - failed to read PCI command register", - vdev->vbasedev.name); - } - - cmd =3D cmd_orig | PCI_COMMAND_IO; - - if (pwrite(vdev->vbasedev.fd, &cmd, sizeof(cmd), - vdev->config_offset + PCI_COMMAND) !=3D sizeof(cmd)) { - error_report("IGD device %s - failed to write PCI command register= ", - vdev->vbasedev.name); - } - - for (i =3D 1; i < vfio_igd_gtt_max(vdev); i +=3D 4) { - vfio_region_write(&vdev->bars[4].region, 0, i, 4); - vfio_region_write(&vdev->bars[4].region, 4, 0, 4); - } - - if (pwrite(vdev->vbasedev.fd, &cmd_orig, sizeof(cmd_orig), - vdev->config_offset + PCI_COMMAND) !=3D sizeof(cmd_orig)) { - error_report("IGD device %s - failed to restore PCI command regist= er", - vdev->vbasedev.name); - } - trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (ggms_size + gms_size) / MiB); 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Wed, 22 Jan 2025 09:17:50 -0800 (PST) From: Tomita Moeko To: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: qemu-devel@nongnu.org, Tomita Moeko Subject: [PATCH 2/4] vfio/pci: add placeholder for device-specific config space quirks Date: Thu, 23 Jan 2025 01:17:29 +0800 Message-ID: <20250122171731.40444-3-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122171731.40444-1-tomitamoeko@gmail.com> References: <20250122171731.40444-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1737566318187019000 Content-Type: text/plain; charset="utf-8" Some devices, such as IGD, require device-specific quirks to be applied to their pci config spaces. Currently, these quirks are either part of BAR quirk, or being a part of vfio_realize(). Add a placeholder for pci config quirks for moving the quirks to one place later. Signed-off-by: Tomita Moeko --- hw/vfio/pci-quirks.c | 5 +++++ hw/vfio/pci.c | 4 ++++ hw/vfio/pci.h | 1 + 3 files changed, 10 insertions(+) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index fbe43b0a79..c40e3ca88f 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1167,6 +1167,11 @@ bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, /* * Common quirk probe entry points. */ +bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp) +{ + return true; +} + void vfio_vga_quirk_setup(VFIOPCIDevice *vdev) { vfio_vga_probe_ati_3c3_quirk(vdev); diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index ab17a98ee5..e624ae56c4 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -3124,6 +3124,10 @@ static void vfio_realize(PCIDevice *pdev, Error **er= rp) goto out_unset_idev; } =20 + if (!vfio_config_quirk_setup(vdev, errp)) { + goto out_unset_idev; + } + if (vdev->vga) { vfio_vga_quirk_setup(vdev); } diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index 43c166680a..5359e94f18 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -205,6 +205,7 @@ uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsig= ned size); void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned siz= e); =20 bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev); +bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp); void vfio_vga_quirk_setup(VFIOPCIDevice *vdev); void vfio_vga_quirk_exit(VFIOPCIDevice *vdev); void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev); --=20 2.45.2 From nobody Thu Jan 23 03:31:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1737566313; cv=none; d=zohomail.com; s=zohoarc; b=G8jrcMPE+Hcq51dIphCRscZpKkYK9Bla04tMuLvKcMkFAvVHy01bVsu8iqCh7sMN5ublZIe9fAB2Mrv+Cr8DAs9hmBkkpkBb0ZcQfqCZt1ElMQ1aawWEJj5JKVEEnIzT7oXFJgss54UNYiPikyYDykTlPAB0ap4W2lWJRBeipY0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 22 Jan 2025 09:17:52 -0800 (PST) From: Tomita Moeko To: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: qemu-devel@nongnu.org, Tomita Moeko Subject: [PATCH 3/4] vfio/igd: refactor vfio_probe_igd_bar4_quirk() into pci config quirk Date: Thu, 23 Jan 2025 01:17:30 +0800 Message-ID: <20250122171731.40444-4-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122171731.40444-1-tomitamoeko@gmail.com> References: <20250122171731.40444-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1737566314301019000 Content-Type: text/plain; charset="utf-8" The actual IO BAR4 write quirk in vfio_probe_igd_bar4_quirk() was removed in previous change, leaving the function not matching its name, so move it into the newly introduced vfio_config_quirk_setup(). There is no functional change in this commit. If any failure occurs, the function simply returns and proceeds. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 30 ++++++++++++++++-------------- hw/vfio/pci-quirks.c | 6 +++++- hw/vfio/pci.h | 2 +- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 4f9a90f36f..33e5202052 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -359,7 +359,8 @@ void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int= nr) QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next); } =20 -void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr) +bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, + Error **errp G_GNUC_UNUSED) { g_autofree struct vfio_region_info *rom =3D NULL; g_autofree struct vfio_region_info *opregion =3D NULL; @@ -378,10 +379,9 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, in= t nr) * PCI bus address. */ if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || - nr !=3D 4 || &vdev->pdev !=3D pci_find_device(pci_device_root_bus(&vdev->pdev), 0, PCI_DEVFN(0x2, 0))) { - return; + return true; } =20 /* @@ -395,7 +395,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) "vfio-pci-igd-lpc-bridge")) { error_report("IGD device %s cannot support legacy mode due to exis= ting " "devices at address 1f.0", vdev->vbasedev.name); - return; + return true; } =20 /* @@ -407,7 +407,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) if (gen =3D=3D -1) { error_report("IGD device %s is unsupported in legacy mode, " "try SandyBridge or newer", vdev->vbasedev.name); - return; + return true; } =20 /* @@ -420,7 +420,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) if ((ret || !rom->size) && !vdev->pdev.romfile) { error_report("IGD device %s has no ROM, legacy mode disabled", vdev->vbasedev.name); - return; + return true; } =20 /* @@ -431,7 +431,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) error_report("IGD device %s hotplugged, ROM disabled, " "legacy mode disabled", vdev->vbasedev.name); vdev->rom_read_failed =3D true; - return; + return true; } =20 /* @@ -444,7 +444,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) if (ret) { error_report("IGD device %s does not support OpRegion access," "legacy mode disabled", vdev->vbasedev.name); - return; + return true; } =20 ret =3D vfio_get_dev_region_info(&vdev->vbasedev, @@ -453,7 +453,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) if (ret) { error_report("IGD device %s does not support host bridge access," "legacy mode disabled", vdev->vbasedev.name); - return; + return true; } =20 ret =3D vfio_get_dev_region_info(&vdev->vbasedev, @@ -462,7 +462,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) if (ret) { error_report("IGD device %s does not support LPC bridge access," "legacy mode disabled", vdev->vbasedev.name); - return; + return true; } =20 gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); @@ -476,7 +476,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); error_report("IGD device %s failed to enable VGA access, " "legacy mode disabled", vdev->vbasedev.name); - return; + return true; } =20 /* Create our LPC/ISA bridge */ @@ -484,7 +484,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) if (ret) { error_report("IGD device %s failed to create LPC bridge, " "legacy mode disabled", vdev->vbasedev.name); - return; + return true; } =20 /* Stuff some host values into the VM PCI host bridge */ @@ -492,14 +492,14 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, i= nt nr) if (ret) { error_report("IGD device %s failed to modify host bridge, " "legacy mode disabled", vdev->vbasedev.name); - return; + return true; } =20 /* Setup OpRegion access */ if (!vfio_pci_igd_opregion_init(vdev, opregion, &err)) { error_append_hint(&err, "IGD legacy mode disabled\n"); error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); - return; + return true; } =20 /* @@ -561,4 +561,6 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int= nr) =20 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (ggms_size + gms_size) / MiB); + + return true; } diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index c40e3ca88f..b8379cb512 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1169,6 +1169,11 @@ bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, */ bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp) { +#ifdef CONFIG_VFIO_IGD + if (!vfio_probe_igd_config_quirk(vdev, errp)) { + return false; + } +#endif return true; } =20 @@ -1220,7 +1225,6 @@ void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr) vfio_probe_rtl8168_bar2_quirk(vdev, nr); #ifdef CONFIG_VFIO_IGD vfio_probe_igd_bar0_quirk(vdev, nr); - vfio_probe_igd_bar4_quirk(vdev, nr); #endif } =20 diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index 5359e94f18..5c64de0270 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -217,7 +217,7 @@ bool vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **er= rp); void vfio_quirk_reset(VFIOPCIDevice *vdev); VFIOQuirk *vfio_quirk_alloc(int nr_mem); void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr); 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Wed, 22 Jan 2025 09:17:55 -0800 (PST) From: Tomita Moeko To: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: qemu-devel@nongnu.org, Tomita Moeko Subject: [PATCH 4/4] vfio/igd: do not include GTT stolen size in etc/igd-bdsm-size Date: Thu, 23 Jan 2025 01:17:31 +0800 Message-ID: <20250122171731.40444-5-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250122171731.40444-1-tomitamoeko@gmail.com> References: <20250122171731.40444-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1737566334426019000 Content-Type: text/plain; charset="utf-8" Though GTT Stolen Memory (GSM) is right below Data Stolen Memory (DSM) in host address space, direct access to GSM is prohibited, and it is not mapped to guest address space. Both host and guest accesses GSM indirectly through the second half of MMIO BAR0 (GTTMMADR). Guest firmware only need to reserve a memory region for DSM and program the BDSM register with the base address of that region, that's actually what both SeaBIOS[1] and OVMF does now. [1] https://gitlab.com/qemu-project/seabios/-/blob/1.12-stable/src/fw/pciin= it.c#L319-332 Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 33e5202052..8bb67b3190 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -112,28 +112,8 @@ static int igd_gen(VFIOPCIDevice *vdev) =20 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */ #define IGD_GMCH_GEN6_GMS_MASK 0x1f -#define IGD_GMCH_GEN6_GGMS_SHIFT 8 -#define IGD_GMCH_GEN6_GGMS_MASK 0x3 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */ #define IGD_GMCH_GEN8_GMS_MASK 0xff -#define IGD_GMCH_GEN8_GGMS_SHIFT 6 -#define IGD_GMCH_GEN8_GGMS_MASK 0x3 - -static uint64_t igd_gtt_memory_size(int gen, uint16_t gmch) -{ - uint64_t ggms; - - if (gen < 8) { - ggms =3D (gmch >> IGD_GMCH_GEN6_GGMS_SHIFT) & IGD_GMCH_GEN6_GGMS_M= ASK; - } else { - ggms =3D (gmch >> IGD_GMCH_GEN8_GGMS_SHIFT) & IGD_GMCH_GEN8_GGMS_M= ASK; - if (ggms !=3D 0) { - ggms =3D 1ULL << ggms; - } - } - - return ggms * MiB; -} =20 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch) { @@ -368,7 +348,7 @@ bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, g_autofree struct vfio_region_info *lpc =3D NULL; PCIDevice *lpc_bridge; int ret, gen; - uint64_t ggms_size, gms_size; + uint64_t gms_size; uint64_t *bdsm_size; uint32_t gmch; Error *err =3D NULL; @@ -527,7 +507,6 @@ bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, } } =20 - ggms_size =3D igd_gtt_memory_size(gen, gmch); gms_size =3D igd_stolen_memory_size(gen, gmch); =20 /* @@ -539,7 +518,7 @@ bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, * config offset 0x5C. */ bdsm_size =3D g_malloc(sizeof(*bdsm_size)); - *bdsm_size =3D cpu_to_le64(ggms_size + gms_size); + *bdsm_size =3D cpu_to_le64(gms_size); fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", bdsm_size, sizeof(*bdsm_size)); =20 @@ -559,8 +538,7 @@ bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); } =20 - trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, - (ggms_size + gms_size) / MiB); + trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB)); =20 return true; } --=20 2.45.2