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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322acdcsm16022223f8f.55.2025.01.22.01.30.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Jan 2025 01:30:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737538253; x=1738143053; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3ds9Wj0QZU42GLHBsVwmUFq56bCDGO06IGIH+Sdiodc=; b=PmjUjP9CKILYn+fBhV8S2ICj/3uSCLw237P+IYX0BTiPjRX8ugYkpGIFh0J5P9hza8 miDLGx0xAXEOtJHSzN1xWi3vDq3W2lBj7tq6x7At+f5wmrVJgv4ken15WR7zZRxla1zu c57wSXDRP/srDP6P3bbhwLwa1sx8ScPRU6iQ/5UbMvRI4BJwve+LKcQLkIrS2Usa843c 24VX6FTT7ciO8DS4Uu+mi4haxv982CCjBRX+4NY4jyktVwC8pqYYTn0uFb/6/2stJMAE skchOP/DHjMkrogdJ35rcyIuD2BmWCQTfVcCAuQ6Jc3kDuSF6evaX/YSvkuVDW5AHKga XEpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737538253; x=1738143053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3ds9Wj0QZU42GLHBsVwmUFq56bCDGO06IGIH+Sdiodc=; b=d6XepkMFcK5ZbZbe4PfLD8cP3cwZAKJGHKQwM0S0u5tCkv3POV5J70vQ0HSUEn+Sr5 FJ2W+7Oa6FTPzM0HF1CBQ3T813gSIymfyajKpOz8iZtFRju/9nE7gSy8svJNtovFBG1V 1ll8SKKFX0R9/7JkUcGuJphJM/s/Ns4qSjrnd7wilFz6omckjHuMEvEoBAmuCcYY79LH vsBfMUj9SWGdbzQCJOdEsdWNfPY8quAIdX/HaMFL6csZyQw/YAnuCB4TEzHtARbJ9h3m 8ee8N9LdZ92N1WFusrZifcKcDSMpP6Mo+LWD/CSYouWyQdPN9uRFa76TK3QXT4m/LHzP ZT6w== X-Gm-Message-State: AOJu0YyQbnxecDEO1+Fdc8qGR9RTUoVYLkMs2k4M6O67vmL8hGEyNfKg dK+itmpcPQxRwT009c2nEWL71FHsEOAexhBP86nCgeFBUFtSrYlko03N2vM+uBv2y8XlFUQXjfN hAcY= X-Gm-Gg: ASbGncsmvw421JehaOyq5jyjTyopjJ08ND6zegCH4bHPgdbGUDHvXX8VBeGDEPrwFS7 BEg8YFO1OWA69ifTs4INeSSEIgRP2j6tA0WWKL3LacId/y7Ny6MBYKc7paP76a0ZJ7I+6v8ws6y SXbvTvIJGYYnKCzBMY1lGe0UVg68TGR4VLbRS2f+ZYYfXPmlkEmm+5md7utrjC/e13O14mMT51E hKBoDIFiO7AJjZPGW7NNqAmhvj5QaFGon5ov4buoyjutKTmAhAMUl8qz09x8sEgw9LNp2NZUzzP lzMnTTy9qxpwFzshl3SLugLLdP5ylN7YI9ENdLnRgD7q X-Google-Smtp-Source: AGHT+IGpVW92Redmqgr+HmUbpNm8hsX+p2uNrDpzZR1xgMtAGnI2STvmEVxhrXqPqFc+p4wVYOA0OQ== X-Received: by 2002:a05:6000:1f81:b0:386:3213:5b9b with SMTP id ffacd0b85a97d-38bf57a9477mr21266255f8f.43.1737538253473; Wed, 22 Jan 2025 01:30:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/10] accel: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Wed, 22 Jan 2025 10:30:23 +0100 Message-ID: <20250122093028.52416-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250122093028.52416-1-philmd@linaro.org> References: <20250122093028.52416-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1737538401651019000 CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/accel-target.c | 12 +++++------- accel/tcg/tcg-accel-ops.c | 3 +-- accel/tcg/translate-all.c | 2 +- accel/tcg/watchpoint.c | 9 ++++----- 4 files changed, 11 insertions(+), 15 deletions(-) diff --git a/accel/accel-target.c b/accel/accel-target.c index 08626c00c2d..8a16c0c3ae0 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -112,22 +112,20 @@ void accel_init_interfaces(AccelClass *ac) =20 void accel_cpu_instance_init(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) { - cc->accel_cpu->cpu_instance_init(cpu); + if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) { + cpu->cc->accel_cpu->cpu_instance_init(cpu); } } =20 bool accel_cpu_common_realize(CPUState *cpu, Error **errp) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); AccelState *accel =3D current_accel(); AccelClass *acc =3D ACCEL_GET_CLASS(accel); =20 /* target specific realization */ - if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize - && !cc->accel_cpu->cpu_target_realize(cpu, errp)) { + if (cpu->cc->accel_cpu + && cpu->cc->accel_cpu->cpu_target_realize + && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) { return false; } =20 diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b2..299d6176cfb 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -120,10 +120,9 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdb= type) [GDB_WATCHPOINT_ACCESS] =3D BP_GDB | BP_MEM_ACCESS, }; =20 - CPUClass *cc =3D CPU_GET_CLASS(cpu); int cputype =3D xlat[gdbtype]; =20 - if (cc->gdb_stop_before_watchpoint) { + if (cpu->cc->gdb_stop_before_watchpoint) { cputype |=3D BP_STOP_BEFORE_ACCESS; } return cputype; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d56ca13cddf..5a378cb0281 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -622,7 +622,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) * to account for the re-execution of the branch. */ n =3D 1; - cc =3D CPU_GET_CLASS(cpu); + cc =3D cpu->cc; if (cc->tcg_ops->io_recompile_replay_branch && cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { cpu->neg.icount_decr.u16.low++; diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index af57d182d5b..52e550dec6b 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -69,7 +69,6 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr a= ddr, vaddr len) void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); CPUWatchpoint *wp; =20 assert(tcg_enabled()); @@ -85,9 +84,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd= r len, return; } =20 - if (cc->tcg_ops->adjust_watchpoint_address) { + if (cpu->cc->tcg_ops->adjust_watchpoint_address) { /* this is currently used only by ARM BE32 */ - addr =3D cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); + addr =3D cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, le= n); } =20 assert((flags & ~BP_MEM_ACCESS) =3D=3D 0); @@ -119,8 +118,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, wp->hitattrs =3D attrs; =20 if (wp->flags & BP_CPU - && cc->tcg_ops->debug_check_watchpoint - && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { + && cpu->cc->tcg_ops->debug_check_watchpoint + && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { wp->flags &=3D ~BP_WATCHPOINT_HIT; continue; } --=20 2.47.1