From nobody Thu Jan 23 05:35:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1737535780; cv=none; d=zohomail.com; s=zohoarc; b=kV2zm1a0k9Bi/LKdk/qeSU3+MLkwovyS+BVpI3RlXau1XNNBEVh26xAZYd5Zrs7dc3rAThiHM+HatD9KB5CpGA1mj5M6qYkLZpU5L6omRgH0EUSyt97aeFsGBtfGfb1TYRCXDiP8Sf1b2NKrkGfS0DI4co2FLZxOTfozj5XOdCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1737535780; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=QJ1XYgNNZBB8eJ987RbIvsjZRaKAx1GQy10l1MYLtwY=; b=Qjq2ADLPU5ClhC1lLaWvNaSXUf/UIOQ5KlEgSEVGyKkK/8F0Q+3Nr2+zb7gaS1t1mmdLhicsfLt465A+ksL7O1O+KYwFaeS3fcOTXFQjVpnqSxvHlk096ZkCvfnquU9FKNXRORpPAJC1phrELIaDVYnPVkP8hCLsVB7lxtyJpQM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1737535780465470.0919398758256; Wed, 22 Jan 2025 00:49:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1taWPm-0006I7-Rj; Wed, 22 Jan 2025 03:48:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taWPa-0005fA-3v; Wed, 22 Jan 2025 03:48:37 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1taWPW-0004OD-EH; Wed, 22 Jan 2025 03:48:33 -0500 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 50M8m4FF025899 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 22 Jan 2025 16:48:04 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from atcpcw16.andestech.com (10.0.1.106) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server (TLS) id 14.3.498.0; Wed, 22 Jan 2025 16:48:04 +0800 To: CC: , , , , , , , , , , , , Ethan Chen Subject: [PATCH v10 8/8] hw/riscv/virt: Add IOPMP support Date: Wed, 22 Jan 2025 16:47:47 +0800 Message-ID: <20250122084747.3971444-1-ethan84@andestech.com> X-Mailer: git-send-email 2.42.0.345.gaab89be2eb.dirty In-Reply-To: <20250122083617.3940240-1-ethan84@andestech.com> References: <20250122083617.3940240-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.1.106] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 50M8m4FF025899 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1737535782355019000 Content-Type: text/plain; charset="utf-8" - Add 'iopmp=3Don' option to enable IOPMP. It adds iopmp devices virt machi= ne to protect all regions of system memory. Signed-off-by: Ethan Chen --- docs/system/riscv/virt.rst | 7 ++++ hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 75 ++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 4 ++ 4 files changed, 87 insertions(+) diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 60850970ce..6b5fc1d37d 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -146,6 +146,13 @@ The following machine-specific options are supported: =20 Enables the riscv-iommu-sys platform device. Defaults to 'off'. =20 +- iopmp=3D[on|off] + + When this option is "on", IOPMP devices are added to machine. IOPMP chec= ks + memory transcations in system memory. This option is assumed to be "off"= . To + enable the CPU to perform transactions with a specified RRID, use the CPU + option "-cpu ,iopmp=3Dtrue,iopmp_rrid=3D" + Running Linux kernel -------------------- =20 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index e6a0ac1fa1..637438af2c 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -68,6 +68,7 @@ config RISCV_VIRT select PLATFORM_BUS select ACPI select ACPI_PCI + select RISCV_IOPMP =20 config SHAKTI_C bool diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 241389d72f..c5a8f7173e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -57,6 +57,8 @@ #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" +#include "hw/misc/riscv_iopmp.h" +#include "hw/misc/riscv_iopmp_dispatcher.h" =20 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU= . */ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) @@ -94,6 +96,7 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, [VIRT_FW_CFG] =3D { 0x10100000, 0x18 }, + [VIRT_IOPMP] =3D { 0x10200000, 0x100000 }, [VIRT_FLASH] =3D { 0x20000000, 0x4000000 }, [VIRT_IMSIC_M] =3D { 0x24000000, VIRT_IMSIC_MAX_SIZE }, [VIRT_IMSIC_S] =3D { 0x28000000, VIRT_IMSIC_MAX_SIZE }, @@ -102,6 +105,11 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_DRAM] =3D { 0x80000000, 0x0 }, }; =20 +static const MemMapEntry iopmp_protect_memmap[] =3D { + /* IOPMP protect all regions by default */ + {0x0, 0xFFFFFFFF}, +}; + /* PCIe high mmio is fixed for RV32 */ #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) @@ -1117,6 +1125,24 @@ static void create_fdt_iommu(RISCVVirtState *s, uint= 16_t bdf) bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); } =20 +static void create_fdt_iopmp(RISCVVirtState *s, const MemMapEntry *memmap, + uint32_t irq_mmio_phandle) { + g_autofree char *name =3D NULL; + MachineState *ms =3D MACHINE(s); + + name =3D g_strdup_printf("/soc/iopmp@%lx", (long)memmap[VIRT_IOPMP].ba= se); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv_iopmp"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_IOPMP].b= ase, + 0x0, memmap[VIRT_IOPMP].size); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phan= dle); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", IOPMP_IRQ); + } else { + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", IOPMP_IRQ, 0x4= ); + } +} + static void finalize_fdt(RISCVVirtState *s) { uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -1141,6 +1167,10 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_uart(s, virt_memmap, irq_mmio_phandle); =20 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); + + if (s->have_iopmp) { + create_fdt_iopmp(s, virt_memmap, irq_mmio_phandle); + } } =20 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) @@ -1529,6 +1559,8 @@ static void virt_machine_init(MachineState *machine) DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; int socket_count =3D riscv_socket_count(machine); + DeviceState *iopmp_dev, *iopmp_disp_dev; + StreamSink *iopmp_ss, *iopmp_disp_ss; =20 /* Check socket count limit */ if (VIRT_SOCKETS_MAX < socket_count) { @@ -1710,6 +1742,29 @@ static void virt_machine_init(MachineState *machine) } virt_flash_map(s, system_memory); =20 + if (s->have_iopmp) { + iopmp_dev =3D iopmp_create(memmap[VIRT_IOPMP].base, + qdev_get_gpio_in(DEVICE(mmio_irqchip), IOPMP_IRQ)); + + iopmp_setup_system_memory(iopmp_dev, &iopmp_protect_memmap[0], 1, = 0); + + iopmp_disp_dev =3D qdev_new(TYPE_RISCV_IOPMP_DISP); + qdev_prop_set_uint32(DEVICE(iopmp_disp_dev), "target-num", 1); + qdev_prop_set_uint32(DEVICE(iopmp_disp_dev), "stage-num", 1); + qdev_realize(DEVICE(iopmp_disp_dev), NULL, &error_fatal); + + /* Add memmap inforamtion to dispatcher */ + iopmp_ss =3D (StreamSink *)&(RISCV_IOPMP(iopmp_dev)->txn_info_sink= ); + iopmp_dispatcher_add_target(DEVICE(iopmp_disp_dev), iopmp_ss, + iopmp_protect_memmap[0].base, + iopmp_protect_memmap[0].size, + 0, 0); + + iopmp_disp_ss =3D + (StreamSink *)&(RISCV_IOPMP_DISP(iopmp_disp_dev)->txn_info_sin= k); + iopmp_setup_sink(iopmp_dev, iopmp_disp_ss); + } + /* load/create device tree */ if (machine->dtb) { machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); @@ -1845,6 +1900,20 @@ static void virt_set_iommu_sys(Object *obj, Visitor = *v, const char *name, visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); } =20 +static bool virt_get_iopmp(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + return s->have_iopmp; +} + +static void virt_set_iopmp(Object *obj, bool value, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->have_iopmp =3D value; +} + bool virt_is_acpi_enabled(RISCVVirtState *s) { return s->acpi !=3D ON_OFF_AUTO_OFF; @@ -1972,6 +2041,12 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) NULL, NULL); object_class_property_set_description(oc, "iommu-sys", "Enable IOMMU platform device"); + + object_class_property_add_bool(oc, "iopmp", virt_get_iopmp, + virt_set_iopmp); + object_class_property_set_description(oc, "iopmp", + "Set on/off to enable/disable " + "iopmp device"); } =20 static const TypeInfo virt_machine_typeinfo =3D { diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 48a14bea2e..77dcbd5450 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -55,6 +55,7 @@ struct RISCVVirtState { =20 int fdt_size; bool have_aclint; + bool have_iopmp; RISCVVirtAIAType aia_type; int aia_guests; char *oem_id; @@ -87,11 +88,14 @@ enum { VIRT_PLATFORM_BUS, VIRT_PCIE_ECAM, VIRT_IOMMU_SYS, + VIRT_IOPMP, }; =20 enum { UART0_IRQ =3D 10, RTC_IRQ =3D 11, + IOPMP_IRQ =3D 12, + DMA_IRQ =3D 13, VIRTIO_IRQ =3D 1, /* 1 to 8 */ VIRTIO_COUNT =3D 8, PCIE_IRQ =3D 0x20, /* 32 to 35 */ --=20 2.34.1