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Wed, 22 Jan 2025 16:36:35 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from atcpcw16.andestech.com (10.0.1.106) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server (TLS) id 14.3.498.0; Wed, 22 Jan 2025 16:36:34 +0800 To: CC: , , , , , , , , , , , , Ethan Chen Subject: [PATCH v10 4/8] target/riscv: Add support for IOPMP Date: Wed, 22 Jan 2025 16:36:13 +0800 Message-ID: <20250122083617.3940240-5-ethan84@andestech.com> X-Mailer: git-send-email 2.42.0.345.gaab89be2eb.dirty In-Reply-To: <20250122083617.3940240-1-ethan84@andestech.com> References: <20250122083617.3940240-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.1.106] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 50M8aZ4c018567 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1737535108338019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Ethan Chen Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 2 ++ target/riscv/cpu_helper.c | 18 +++++++++++++++--- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2..0788511cf4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2867,6 +2867,9 @@ static const Property riscv_cpu_properties[] =3D { * it with -x and default to 'false'. */ DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), + + DEFINE_PROP_BOOL("iopmp", RISCVCPU, cfg.iopmp, false), + DEFINE_PROP_UINT32("iopmp_rrid", RISCVCPU, cfg.iopmp_rrid, 0), }; =20 #if defined(TARGET_RISCV64) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index b410b1e603..09644b8252 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -188,6 +188,8 @@ struct RISCVCPUConfig { bool pmp; bool debug; bool misa_w; + bool iopmp; + uint32_t iopmp_rrid; =20 bool short_isa_string; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1dfc4ecbf..3940e612af 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1702,9 +1702,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, } =20 if (ret =3D=3D TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), - prot, mmu_idx, tlb_size); - return true; + if (cpu->cfg.iopmp) { + /* + * Do not align address on early stage because IOPMP needs ori= gin + * address for permission check. + */ + tlb_set_page_with_attrs(cs, address, pa, + (MemTxAttrs) + { + .requester_id =3D cpu->cfg.iopmp= _rrid, + }, + prot, mmu_idx, tlb_size); + } else { + tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - = 1), + prot, mmu_idx, tlb_size); + } } else if (probe) { return false; } else { --=20 2.34.1