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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529765; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ifvU6q0Cr9WI7jkOBvYCbrw0QaRB0v618Dxm7o9kGgE=; b=JiX/5tbHGAlteHP3Ih84XneCZGs3ZrfOWJfgpw9HyO/eU39tVMISd6ajPlPa2czbWRt/it R5HkVyDdG2hzA5KugjrqxmjWROcDPqkHsA0gT6DpuQOSXx3axDGAz65HIqFHqDOBcQt7BL nxnzgzPyb+NrasKpAMJ/LpNFx3A9uek= X-MC-Unique: 10Ns6XEVOne-piBszQVrFg-1 X-Mimecast-MFC-AGG-ID: 10Ns6XEVOne-piBszQVrFg From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , Kenneth Jia , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 1/9] hw/arm/aspeed: fix connect_serial_hds_to_uarts Date: Wed, 22 Jan 2025 08:09:01 +0100 Message-ID: <20250122070909.1138598-2-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.086, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529786532019000 From: Kenneth Jia In the loop, we need ignore the index increase when uart =3D=3D uart_chosen We should increase the index only after we allocate a serial. Signed-off-by: Kenneth Jia Fixes: d2b3eaefb4d7 ("aspeed: Refactor UART init for multi-SoC machines") Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/r/5f9b0c53f1644922ba85522046e92f4c@asus.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a18d4ed1fb10..2662465ada4f 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -364,11 +364,11 @@ static void connect_serial_hds_to_uarts(AspeedMachine= State *bmc) int uart_chosen =3D bmc->uart_chosen ? bmc->uart_chosen : amc->uart_de= fault; =20 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); - for (int i =3D 1, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uar= t++) { + for (int i =3D 1, uart =3D sc->uarts_base; i < sc->uarts_num; uart++) { if (uart =3D=3D uart_chosen) { continue; } - aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); + aspeed_soc_uart_set_chr(s, uart, serial_hd(i++)); } } =20 --=20 2.48.1 From nobody Thu Jan 23 03:23:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529775; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GyUuEd+mQAYgtLNlBd/uEG9AWCHY4JYbVKG1xXpW/Ho=; b=QMJWuGcE/bht3B16pJPpvidXKjdhwL8wd17Q2iUmpU9cjfEcV/I35MWkQqX7xBDtkPXvK2 Ir8o/4FSd/6Cf4Wpe1JLTeSEd25nZnqSrw3aS0D56kQzJ9VNmLswOH/2s+JigrlhA8OWZO JnkWF/yABA028eCZu9/8Z1F4QwsI0D8= X-MC-Unique: IYAD60OuPCu8XAv-ADK7nQ-1 X-Mimecast-MFC-AGG-ID: IYAD60OuPCu8XAv-ADK7nQ From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/9] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Date: Wed, 22 Jan 2025 08:09:02 +0100 Message-ID: <20250122070909.1138598-3-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529901356019000 From: Jamin Lin The Write Protect pin of SDHCI model is default active low to match the SDH= CI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable the bi= t 19 should be 0 and write protected the bit 19 should be 1 at the Present State Register (0x24). To support it, introduces a new "wp-inverted" property and set it false by default. Signed-off-by: Jamin Lin Acked-by: C=C3=A9dric Le Goater Acked-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/r/20241114094839.4128404-3-jamin_lin@aspeedte= ch.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/sd/sdhci.h | 5 +++++ hw/sd/sdhci.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 6cd2822f1d13..38c08e285980 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -100,6 +100,11 @@ struct SDHCIState { uint8_t sd_spec_version; uint8_t uhs_mode; uint8_t vendor; /* For vendor specific functionality */ + /* + * Write Protect pin default active low for detecting SD card + * to be protected. Set wp_inverted to invert the signal. + */ + bool wp_inverted; }; typedef struct SDHCIState SDHCIState; =20 diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 318587ff57ca..99dd4a4e9528 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -274,6 +274,10 @@ static void sdhci_set_readonly(DeviceState *dev, bool = level) { SDHCIState *s =3D (SDHCIState *)dev; =20 + if (s->wp_inverted) { + level =3D !level; + } + if (level) { s->prnsts &=3D ~SDHC_WRITE_PROTECT; } else { @@ -1555,6 +1559,8 @@ static const Property sdhci_sysbus_properties[] =3D { false), DEFINE_PROP_LINK("dma", SDHCIState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_BOOL("wp-inverted", SDHCIState, + wp_inverted, false), }; =20 static void sdhci_sysbus_init(Object *obj) --=20 2.48.1 From nobody Thu Jan 23 03:23:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=Ayl2E/VrUl+Llrmlcin4PivEBLaP2DgTB+tiRIfVc+M=; b=UxlHcGS4XPvRTZIiEoscGx2M4QI0jnirPXAKUcgpKjWWVimGp8/FMGWINLlVH6FPeLB+2l VarziGobvR9XGELib2OcWSFAiIRvkJ/r9OoVMtSldnDm3jw6t49xPrbFIGJOY7gK3Rinwv /Codiz2nPgdEa2wg3eJ4ftPmb17gv4o= X-MC-Unique: sNhgmxi9NqGM0qr2kchdLw-1 X-Mimecast-MFC-AGG-ID: sNhgmxi9NqGM0qr2kchdLw From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 3/9] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB Date: Wed, 22 Jan 2025 08:09:03 +0100 Message-ID: <20250122070909.1138598-4-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.086, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529913258019000 From: Jamin Lin The Write Protect pin of SDHCI model is default active low to match the SDH= CI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To support it, introduces a new "sdhci_wp_inverted" property in ASPEED MACHINE State and set it true for AST2600 EVB and set "wp_inverted" property true of sdhci-generic model. Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery Acked-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/r/20241114094839.4128404-4-jamin_lin@aspeedte= ch.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index cbeacb214ca4..9cae45a1c99c 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -39,6 +39,7 @@ struct AspeedMachineClass { uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; + bool sdhci_wp_inverted; }; =20 =20 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 2662465ada4f..53a859a6e4aa 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -409,6 +409,12 @@ static void aspeed_machine_init(MachineState *machine) OBJECT(get_system_memory()), &error_abort); object_property_set_link(OBJECT(bmc->soc), "dram", OBJECT(machine->ram), &error_abort); + if (amc->sdhci_wp_inverted) { + for (i =3D 0; i < bmc->soc->sdhci.num_slots; i++) { + object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), + "wp-inverted", true, &error_abort); + } + } if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot @@ -1415,6 +1421,7 @@ static void aspeed_machine_ast2600_evb_class_init(Obj= ectClass *oc, void *data) amc->num_cs =3D 1; amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->sdhci_wp_inverted =3D true; amc->i2c_init =3D ast2600_evb_i2c_init; mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); --=20 2.48.1 From nobody Thu Jan 23 03:23:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1737529892; cv=none; d=zohomail.com; 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Wed, 22 Jan 2025 07:09:29 +0000 (UTC) Received: from corto.redhat.com (unknown [10.39.192.154]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 4B1963003FD2; Wed, 22 Jan 2025 07:09:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529781; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0ZA1go/C/CGZZBr0BaFM7Sf1Rus0FnCIC3wK4bQP9NQ=; b=D5E/ZLE9xbI3cn6bN8ivuCUXiJFgbCRckE1MpdAFOgl5X/Yi5zq4E+Q2joKDhi88mIXsuE TkFDVrYNrLTfrtlzWy0ol3AHvAgTG9YVeGqkwzzSfJkGmmjKpJop3JGpuvBMa5Bvk7pqTw +ur8e5lZWa38a5pN74GxtN5TWbtr5h4= X-MC-Unique: T4BUVnIuMU-FRnwJP3V2Bg-1 X-Mimecast-MFC-AGG-ID: T4BUVnIuMU-FRnwJP3V2Bg From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 4/9] hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations Date: Wed, 22 Jan 2025 08:09:04 +0100 Message-ID: <20250122070909.1138598-5-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.086, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529893261019000 From: Jamin Lin The register set have a significant change in AST2700. The TMC00-TMC3C are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional, TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1, respectively. Besides, each TIMER has their own control and interrupt status register. In other words, users are able to set control and interrupt status for TIME= R0 in one register. Both aspeed_timer_read and aspeed_timer_write callback functions are not compatible AST2700. Introduce common read and write functions for ASPEED timers. Modify the aspeed_timer_read and aspeed_timer_write functions to delegate to SoC-specific callbacks first. Update the AST2400, AST2500, AST2600 and AST1030 specific read and write functions to call the common implementations for common register accesses. This refactoring improves the organization of call delegation and prepares = the codebase for future SoC-specific specializations, such as the AST2700. Signed-off-by: Jamin Lin Link: https://lore.kernel.org/r/20250113064455.1660564-2-jamin_lin@aspeedte= ch.com Signed-off-by: C=C3=A9dric Le Goater --- hw/timer/aspeed_timer.c | 55 ++++++++++++++++++++++++++++++----------- hw/timer/trace-events | 2 +- 2 files changed, 41 insertions(+), 16 deletions(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 4868651ad489..24ba40cbe9b4 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -239,9 +239,8 @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, = int reg) return value; } =20 -static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned si= ze) +static uint64_t aspeed_timer_read_common(AspeedTimerCtrlState *s, hwaddr o= ffset) { - AspeedTimerCtrlState *s =3D opaque; const int reg =3D (offset & 0xf) / 4; uint64_t value; =20 @@ -256,10 +255,11 @@ static uint64_t aspeed_timer_read(void *opaque, hwadd= r offset, unsigned size) value =3D aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], re= g); break; default: - value =3D ASPEED_TIMER_GET_CLASS(s)->read(s, offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", + __func__, offset); + value =3D 0; break; } - trace_aspeed_timer_read(offset, size, value); return value; } =20 @@ -431,12 +431,11 @@ static void aspeed_timer_set_ctrl2(AspeedTimerCtrlSta= te *s, uint32_t value) trace_aspeed_timer_set_ctrl2(value); } =20 -static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) +static void aspeed_timer_write_common(AspeedTimerCtrlState *s, hwaddr offs= et, + uint64_t value) { const uint32_t tv =3D (uint32_t)(value & 0xFFFFFFFF); const int reg =3D (offset & 0xf) / 4; - AspeedTimerCtrlState *s =3D opaque; =20 switch (offset) { /* Control Registers */ @@ -451,11 +450,25 @@ static void aspeed_timer_write(void *opaque, hwaddr o= ffset, uint64_t value, aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv); break; default: - ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", + __func__, offset); break; } } =20 +static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned si= ze) +{ + AspeedTimerCtrlState *s =3D ASPEED_TIMER(opaque); + return ASPEED_TIMER_GET_CLASS(s)->read(s, offset); +} + +static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + AspeedTimerCtrlState *s =3D ASPEED_TIMER(opaque); + ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value); +} + static const MemoryRegionOps aspeed_timer_ops =3D { .read =3D aspeed_timer_read, .write =3D aspeed_timer_write, @@ -475,12 +488,15 @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtr= lState *s, hwaddr offset) break; case 0x38: case 0x3C: - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", __func__, offset); value =3D 0; break; + default: + value =3D aspeed_timer_read_common(s, offset); + break; } + trace_aspeed_timer_read(offset, value); return value; } =20 @@ -495,10 +511,12 @@ static void aspeed_2400_timer_write(AspeedTimerCtrlSt= ate *s, hwaddr offset, break; case 0x38: case 0x3C: - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", __func__, offset); break; + default: + aspeed_timer_write_common(s, offset, value); + break; } } =20 @@ -514,12 +532,15 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtr= lState *s, hwaddr offset) value =3D s->ctrl3 & BIT(0); break; case 0x3C: - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", __func__, offset); value =3D 0; break; + default: + value =3D aspeed_timer_read_common(s, offset); + break; } + trace_aspeed_timer_read(offset, value); return value; } =20 @@ -548,8 +569,7 @@ static void aspeed_2500_timer_write(AspeedTimerCtrlStat= e *s, hwaddr offset, break; =20 default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", - __func__, offset); + aspeed_timer_write_common(s, offset, value); break; } } @@ -564,12 +584,15 @@ static uint64_t aspeed_2600_timer_read(AspeedTimerCtr= lState *s, hwaddr offset) break; case 0x38: case 0x3C: - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", __func__, offset); value =3D 0; break; + default: + value =3D aspeed_timer_read_common(s, offset); + break; } + trace_aspeed_timer_read(offset, value); return value; } =20 @@ -586,10 +609,12 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlSt= ate *s, hwaddr offset, aspeed_timer_set_ctrl(s, s->ctrl & ~tv); break; case 0x38: - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", __func__, offset); break; + default: + aspeed_timer_write_common(s, offset, value); + break; } } =20 diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 5cfc369fba46..c5b6db49f587 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -31,7 +31,7 @@ aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enab= le) "Timer %" PRIu8 ": aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": = %d" aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32 aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d regis= ter %d: 0x%" PRIx32 -aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x= %" PRIx64 ": of size %u: 0x%" PRIx64 +aspeed_timer_read(uint64_t offset, uint64_t value) "From 0x%" PRIx64 ": 0x= %" PRIx64 =20 # armv7m_systick.c systick_reload(void) "systick reload" --=20 2.48.1 From nobody Thu Jan 23 03:23:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1737529818; cv=none; d=zohomail.com; s=zohoarc; b=SJuiPNUaxUg5gsV4Gf4Wdqmzh0Nc/CtaYaMeEX/ki9skR67d+PsDSLqQMt/FiAKxG67xN2I0BiEGAsR24xjbwER/LpRTlSQNFDDgTnD6sBx6HbD3/u/auRaWCDQsB4joS9GUC6/GrYDFR+qKGR0Acoek918/387BQ8qIKpv7mXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1737529818; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gvxXCpgxcR8pnFAbFm1ZXD/+Uaq5sgKqZlPpIPkXai4=; b=MRLwTbGobO8GjeIZXhVpc62X0fg3ldUtInHSL8QuHYx2ATg6uiCXKCQBCQa0P9tpFDCRCbO1BDo+GBuxe7tp7K1PtILG1T4maDWd4ZpK4fGeutlBvwC4NOimez0W+1FlkCPHcnpp4TBFVNPQQzRx8R2Qm3NP5b3uH01LI4ki8mE= ARC-Authentication-Results: i=1; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529778; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gvxXCpgxcR8pnFAbFm1ZXD/+Uaq5sgKqZlPpIPkXai4=; b=LIcwAm6JNeaibDUuXHOc4ZQIt1TE+2knprhVx/I6JJyAb1CSOmEbZXxxGygInKXlqlRG2w uUoXjs95NmBWrZV85bDPaABTihOW82134uD0euhNMwXiqCMgZOtdQC7Pf1pykTuYnZwjTE 9dhrR/D6W/k30EvGdFdRWpQ7p8mzvQA= X-MC-Unique: vKgMT3LuMCCPRUe9CGdQ4Q-1 X-Mimecast-MFC-AGG-ID: vKgMT3LuMCCPRUe9CGdQ4Q From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 5/9] hw/timer/aspeed: Add AST2700 Support Date: Wed, 22 Jan 2025 08:09:05 +0100 Message-ID: <20250122070909.1138598-6-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529820842019000 From: Jamin Lin The timer controller include 8 sets of 32-bit decrement counters, based on either PCLK or 1MHZ clock and the design of timer controller between AST2600 and AST2700 are almost the same. TIMER0 =E2=80=93 TIMER7 has their own individual control and interrupt stat= us register. In other words, users are able to set timer control in register TMC10 with different TIMER base address and clear timer control and interrupt status in register TMC14 with different TIMER base address. Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write" callba= ck functions and a new ast2700 class to support AST2700. The base address of TIMER0 to TIMER7 as following. Base Address of Timer 0 =3D 0x12C1_0000 Base Address of Timer 1 =3D 0x12C1_0040 Base Address of Timer 2 =3D 0x12C1_0080 Base Address of Timer 3 =3D 0x12C1_00C0 Base Address of Timer 4 =3D 0x12C1_0100 Base Address of Timer 5 =3D 0x12C1_0140 Base Address of Timer 6 =3D 0x12C1_0180 Base Address of Timer 7 =3D 0x12C1_01C0 The register address space of each TIMER is "0x40" , and uses the following formula to get the index and register of each TIMER. timer_index =3D offset >> 6; timer_offset =3D offset & 0x3f; The TMC010 is a counter control set and interrupt status register. Write "1= " to TMC10[3:0] will set the specific bits to "1". Introduce a new "aspeed_2700_timer_set_ctrl" function to handle this register behavior. The TMC014 is a counter control clear and interrupt status register, to cle= ar the specific bits to "0", it should write "1" to TMC14[3:0] on the same bit position. Introduce a new "aspeed_2700_timer_clear_ctrl" function to handle this register behavior. TMC014 does not support read operation. Signed-off-by: Jamin Lin Acked-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/r/20250113064455.1660564-3-jamin_lin@aspeedte= ch.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/timer/aspeed_timer.h | 1 + hw/timer/aspeed_timer.c | 208 ++++++++++++++++++++++++++++++++ 2 files changed, 209 insertions(+) diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_time= r.h index 07dc6b6f2cbd..767cae4b05ba 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -32,6 +32,7 @@ OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClas= s, ASPEED_TIMER) #define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500" #define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600" #define TYPE_ASPEED_1030_TIMER TYPE_ASPEED_TIMER "-ast1030" +#define TYPE_ASPEED_2700_TIMER TYPE_ASPEED_TIMER "-ast2700" =20 #define ASPEED_TIMER_NR_TIMERS 8 =20 diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 24ba40cbe9b4..ecda49574e2c 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -618,6 +618,197 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlSt= ate *s, hwaddr offset, } } =20 +static void aspeed_2700_timer_set_ctrl(AspeedTimerCtrlState *s, int index, + uint32_t reg) +{ + const uint8_t overflow_interrupt_mask =3D BIT(op_overflow_interrupt); + const uint8_t external_clock_mask =3D BIT(op_external_clock); + const uint8_t pulse_enable_mask =3D BIT(op_pulse_enable); + const uint8_t enable_mask =3D BIT(op_enable); + AspeedTimer *t; + uint8_t t_old; + uint8_t t_new; + int shift; + + /* + * Only 1 will set the specific bits to 1 + * Handle a dependency between the 'enable' and remaining three + * configuration bits - i.e. if more than one bit in the control set h= as + * set, including the 'enable' bit, perform configuration and then + * enable the timer. + * Interrupt Status bit should not be set. + */ + + t =3D &s->timers[index]; + shift =3D index * TIMER_CTRL_BITS; + + t_old =3D (s->ctrl >> shift) & TIMER_CTRL_MASK; + t_new =3D reg & TIMER_CTRL_MASK; + + if (!(t_old & external_clock_mask) && + (t_new & external_clock_mask)) { + aspeed_timer_ctrl_external_clock(t, true); + s->ctrl =3D deposit32(s->ctrl, shift + op_external_clock, 1, 1); + } + + if (!(t_old & overflow_interrupt_mask) && + (t_new & overflow_interrupt_mask)) { + aspeed_timer_ctrl_overflow_interrupt(t, true); + s->ctrl =3D deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 1= ); + } + + + if (!(t_old & pulse_enable_mask) && + (t_new & pulse_enable_mask)) { + aspeed_timer_ctrl_pulse_enable(t, true); + s->ctrl =3D deposit32(s->ctrl, shift + op_pulse_enable, 1, 1); + } + + /* If we are enabling, do so last */ + if (!(t_old & enable_mask) && + (t_new & enable_mask)) { + aspeed_timer_ctrl_enable(t, true); + s->ctrl =3D deposit32(s->ctrl, shift + op_enable, 1, 1); + } +} + +static void aspeed_2700_timer_clear_ctrl(AspeedTimerCtrlState *s, int inde= x, + uint32_t reg) +{ + const uint8_t overflow_interrupt_mask =3D BIT(op_overflow_interrupt); + const uint8_t external_clock_mask =3D BIT(op_external_clock); + const uint8_t pulse_enable_mask =3D BIT(op_pulse_enable); + const uint8_t enable_mask =3D BIT(op_enable); + AspeedTimer *t; + uint8_t t_old; + uint8_t t_new; + int shift; + + /* + * Only 1 will clear the specific bits to 0 + * Handle a dependency between the 'enable' and remaining three + * configuration bits - i.e. if more than one bit in the control set h= as + * clear, including the 'enable' bit, then disable the timer and perfo= rm + * configuration + */ + + t =3D &s->timers[index]; + shift =3D index * TIMER_CTRL_BITS; + + t_old =3D (s->ctrl >> shift) & TIMER_CTRL_MASK; + t_new =3D reg & TIMER_CTRL_MASK; + + /* If we are disabling, do so first */ + if ((t_old & enable_mask) && + (t_new & enable_mask)) { + aspeed_timer_ctrl_enable(t, false); + s->ctrl =3D deposit32(s->ctrl, shift + op_enable, 1, 0); + } + + if ((t_old & external_clock_mask) && + (t_new & external_clock_mask)) { + aspeed_timer_ctrl_external_clock(t, false); + s->ctrl =3D deposit32(s->ctrl, shift + op_external_clock, 1, 0); + } + + if ((t_old & overflow_interrupt_mask) && + (t_new & overflow_interrupt_mask)) { + aspeed_timer_ctrl_overflow_interrupt(t, false); + s->ctrl =3D deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 0= ); + } + + if ((t_old & pulse_enable_mask) && + (t_new & pulse_enable_mask)) { + aspeed_timer_ctrl_pulse_enable(t, false); + s->ctrl =3D deposit32(s->ctrl, shift + op_pulse_enable, 1, 0); + } + + /* Clear interrupt status */ + if (reg & 0x10000) { + s->irq_sts =3D deposit32(s->irq_sts, index, 1, 0); + } +} + +static uint64_t aspeed_2700_timer_read(AspeedTimerCtrlState *s, hwaddr off= set) +{ + uint32_t timer_offset =3D offset & 0x3f; + int timer_index =3D offset >> 6; + uint64_t value =3D 0; + + if (timer_index >=3D ASPEED_TIMER_NR_TIMERS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: offset 0x%" PRIx64 " out of bounds\n", + __func__, offset); + return 0; + } + + switch (timer_offset) { + /* + * Counter Status + * Counter Reload + * Counter First Matching + * Counter Second Matching + */ + case 0x00 ... 0x0C: + value =3D aspeed_timer_get_value(&s->timers[timer_index], + timer_offset >> 2); + break; + /* Counter Control and Interrupt Status */ + case 0x10: + value =3D deposit64(value, 0, 4, + extract32(s->ctrl, timer_index * 4, 4)); + value =3D deposit64(value, 16, 1, + extract32(s->irq_sts, timer_index, 1)); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" + PRIx64"\n", __func__, offset); + value =3D 0; + break; + } + trace_aspeed_timer_read(offset, value); + return value; +} + +static void aspeed_2700_timer_write(AspeedTimerCtrlState *s, hwaddr offset, + uint64_t value) +{ + const uint32_t timer_value =3D (uint32_t)(value & 0xFFFFFFFF); + uint32_t timer_offset =3D offset & 0x3f; + int timer_index =3D offset >> 6; + + if (timer_index >=3D ASPEED_TIMER_NR_TIMERS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: offset 0x%" PRIx64 " out of bounds\n", + __func__, offset); + } + + switch (timer_offset) { + /* + * Counter Status + * Counter Reload + * Counter First Matching + * Counter Second Matching + */ + case 0x00 ... 0x0C: + aspeed_timer_set_value(s, timer_index, timer_offset >> 2, + timer_value); + break; + /* Counter Control Set and Interrupt Status */ + case 0x10: + aspeed_2700_timer_set_ctrl(s, timer_index, timer_value); + break; + /* Counter Control Clear and Interrupr Status */ + case 0x14: + aspeed_2700_timer_clear_ctrl(s, timer_index, timer_value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" + PRIx64"\n", __func__, offset); + break; + } +} + static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id) { AspeedTimer *t =3D &s->timers[id]; @@ -788,6 +979,22 @@ static const TypeInfo aspeed_1030_timer_info =3D { .class_init =3D aspeed_1030_timer_class_init, }; =20 +static void aspeed_2700_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedTimerClass *awc =3D ASPEED_TIMER_CLASS(klass); + + dc->desc =3D "ASPEED 2700 Timer"; + awc->read =3D aspeed_2700_timer_read; + awc->write =3D aspeed_2700_timer_write; +} + +static const TypeInfo aspeed_2700_timer_info =3D { + .name =3D TYPE_ASPEED_2700_TIMER, + .parent =3D TYPE_ASPEED_TIMER, + .class_init =3D aspeed_2700_timer_class_init, +}; + static void aspeed_timer_register_types(void) { type_register_static(&aspeed_timer_info); @@ -795,6 +1002,7 @@ static void aspeed_timer_register_types(void) type_register_static(&aspeed_2500_timer_info); type_register_static(&aspeed_2600_timer_info); type_register_static(&aspeed_1030_timer_info); + type_register_static(&aspeed_2700_timer_info); } =20 type_init(aspeed_timer_register_types) --=20 2.48.1 From nobody Thu Jan 23 03:23:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1737529817; cv=none; d=zohomail.com; s=zohoarc; b=F5P05uGUmZpgtYKLF9pj+8lQZOTifaHjGpgzDq4NpV/lNlcF86A7ApfZbs4Z3hvTi2O3OAUobFFBxlH/x58Al0R7maLwAJ+xA4UGjn9YlnBKoDO3X66OBhgLhvzePbWwGe50hMsH8QPXIKvxcHn68tuVJEj4ukiZsWn4trV38BI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1737529817; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 22 Jan 2025 07:09:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529783; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HCgBPHkwQ9noTFqoX4NtX4SFLU9O8jURWveoSWvlS7U=; b=ie8BYGyzWnaRA9aVTBx4/V0eKplGM7gF0OudGthchPBycnkG65/xTy3D3c8TdDSct8c/DN t0ZfHmdUBL9cS+ldKcIe8UcDeBe2i1pSwjIm78lLeISB03msASqNdTQOQdjZPmJGxUgXgT 725/FGaeCE0kqAj5VO4GUaFP4FLzvvw= X-MC-Unique: fExaK_lFO6iG2gnGkO0ahA-1 X-Mimecast-MFC-AGG-ID: fExaK_lFO6iG2gnGkO0ahA From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 6/9] aspeed/soc: Support Timer for AST2700 Date: Wed, 22 Jan 2025 08:09:06 +0100 Message-ID: <20250122070909.1138598-7-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529818858019000 From: Jamin Lin Add Timer model for AST2700 Timer support. The Timer controller include 8 s= ets of 32-bit decrement counters. The base address of TIMER0 to TIMER7 as following. Base Address of Timer 0 =3D 0x12C1_0000 Base Address of Timer 1 =3D 0x12C1_0040 Base Address of Timer 2 =3D 0x12C1_0080 Base Address of Timer 3 =3D 0x12C1_00C0 Base Address of Timer 4 =3D 0x12C1_0100 Base Address of Timer 5 =3D 0x12C1_0140 Base Address of Timer 6 =3D 0x12C1_0180 Base Address of Timer 7 =3D 0x12C1_01C0 The interrupt of TIMER0 to TIMER7 as following. GICINT16 =3D TIMER 0 interrupt GICINT17 =3D TIMER 1 interrupt GICINT18 =3D TIMER 2 interrupt GICINT19 =3D TIMER 3 interrupt GICINT20 =3D TIMER 4 interrupt GICINT21 =3D TIMER 5 interrupt GICINT22 =3D TIMER 6 interrupt GICINT23 =3D TIMER 7 interrupt Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/r/20250113064455.1660564-4-jamin_lin@aspeedte= ch.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index fee37558372a..4114e15dddf4 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -66,6 +66,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_GPIO] =3D 0x14C0B000, [ASPEED_DEV_RTC] =3D 0x12C0F000, [ASPEED_DEV_SDHCI] =3D 0x14080000, + [ASPEED_DEV_TIMER1] =3D 0x12C10000, }; =20 #define AST2700_MAX_IRQ 256 @@ -397,6 +398,9 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0= ], TYPE_SYSBUS_SDHCI); + + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); + object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); } =20 /* @@ -716,6 +720,19 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); =20 + /* Timer */ + object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, + sc->memmap[ASPEED_DEV_TIMER1]); + for (i =3D 0; i < ASPEED_TIMER_NR_TIMERS; i++) { + irq =3D aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); + } + create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); --=20 2.48.1 From nobody Thu Jan 23 03:23:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529787; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hAhVlXQET5eW9qZ7pK9kd+FVFwJRgIZEg09bqeq/ImE=; b=UYIx8EhAE89UL4z7slycAtA91DbjpDJwhTt+TNAuQXw5RdSVFuJ9miCiYZ5QmOJMhe87iu Fhh/C8AM/R/5aTEQX5iFOyiKququwAPH06KazM4xuvsqy7GoVAWU7lsdh/JIpt6jZtb4j3 jWWHsfdZhtXcgXNeHbFYUMbxLMTCj3w= X-MC-Unique: -zDHzrPWPN6ptbN5m9tjFQ-1 X-Mimecast-MFC-AGG-ID: -zDHzrPWPN6ptbN5m9tjFQ From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 7/9] test/functional: Update the Aspeed aarch64 test Date: Wed, 22 Jan 2025 08:09:07 +0100 Message-ID: <20250122070909.1138598-8-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.086, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529915228019000 Bumped SDK version to v09.03. v09.04 is available but not yet supported in QEMU. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Jamin Lin --- tests/functional/test_aarch64_aspeed.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/functional/test_aarch64_aspeed.py b/tests/functional/tes= t_aarch64_aspeed.py index 141d86385936..6a9ae2a34956 100755 --- a/tests/functional/test_aarch64_aspeed.py +++ b/tests/functional/test_aarch64_aspeed.py @@ -27,14 +27,14 @@ def do_test_aarch64_aspeed_sdk_start(self, image): wait_for_console_pattern(self, '## Loading kernel from FIT Image') wait_for_console_pattern(self, 'Starting kernel ...') =20 - ASSET_SDK_V902_AST2700 =3D Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.02/ast2700-default-obmc.tar.gz', - 'ac969c2602f4e6bdb69562ff466b89ae3fe1d86e1f6797bb7969d787f8211= 6a7') + ASSET_SDK_V903_AST2700 =3D Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.03/ast2700-default-obmc.tar.gz', + '91225f50d255e2905ba8d8e0c80b71b9d157c3609770c7a740cd786370d85= a77') =20 def test_aarch64_ast2700_evb_sdk_v09_02(self): self.set_machine('ast2700-evb') =20 - self.archive_extract(self.ASSET_SDK_V902_AST2700) + self.archive_extract(self.ASSET_SDK_V903_AST2700) =20 num_cpu =3D 4 uboot_size =3D os.path.getsize(self.scratch_file('ast2700-default', --=20 2.48.1 From nobody Thu Jan 23 03:23:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529788; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y1Mjmej+NWbtF9Rf0A/n1OqduglKw4V57isPbqGzMY8=; b=GEUWL9mDSqDRyWOGnWovLnt0q76oqQh8Y+sNMUd+2t3DOzBloZXHf42uAWiV6zwu6iOhp/ pWZ0jUNT1Zpb6umOi2u5GZ8srCj79O7sgJP4f/kV2EwrtwiROoM7s5jZLok1bpON/43YnR 1xEfheutHI9paGwq1pM4/1eyzVcq0qg= X-MC-Unique: ojttCmFEN6SI1hlgSjrwqg-1 X-Mimecast-MFC-AGG-ID: ojttCmFEN6SI1hlgSjrwqg From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 8/9] test/functional: Update buildroot images to 2024.11 Date: Wed, 22 Jan 2025 08:09:08 +0100 Message-ID: <20250122070909.1138598-9-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529840858019000 The main changes compared to upstream 2024.11 buildroot are - bumped Linux to version 6.11.11 with a custom config - changed U-Boot to OpenBMC branch for more support - included extra target packages See branch [1] for more details. There is a slight output change when powering off the machine, the console now contains : reboot: Power off not available: System halted Adjust accordingly the expect string in do_test_arm_aspeed_buildroot_poweroff(). [1] https://github.com/legoater/buildroot/commits/aspeed-2024.11 Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Jamin Lin --- tests/functional/aspeed.py | 2 +- tests/functional/test_arm_aspeed_ast2500.py | 8 ++++---- tests/functional/test_arm_aspeed_ast2600.py | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py index 62f50bab7a33..b52358bb8c61 100644 --- a/tests/functional/aspeed.py +++ b/tests/functional/aspeed.py @@ -42,7 +42,7 @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_i= d, pattern=3D'Aspeed EVB' =20 def do_test_arm_aspeed_buildroot_poweroff(self): exec_command_and_wait_for_pattern(self, 'poweroff', - 'reboot: System halted'); + 'System halted'); =20 def do_test_arm_aspeed_sdk_start(self, image): self.require_netdev('user') diff --git a/tests/functional/test_arm_aspeed_ast2500.py b/tests/functional= /test_arm_aspeed_ast2500.py index 743fc46eb29e..1ffba6c9953d 100755 --- a/tests/functional/test_arm_aspeed_ast2500.py +++ b/tests/functional/test_arm_aspeed_ast2500.py @@ -11,15 +11,15 @@ =20 class AST2500Machine(AspeedTest): =20 - ASSET_BR2_202311_AST2500_FLASH =3D Asset( + ASSET_BR2_202411_AST2500_FLASH =3D Asset( ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' - 'images/ast2500-evb/buildroot-2023.11/flash.img'), - 'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f') + 'images/ast2500-evb/buildroot-2024.11/flash.img'), + '641e6906c18c0f19a2aeb48099d66d4771929c361001d554d0d45c667413e13a') =20 def test_arm_ast2500_evb_buildroot(self): self.set_machine('ast2500-evb') =20 - image_path =3D self.ASSET_BR2_202311_AST2500_FLASH.fetch() + image_path =3D self.ASSET_BR2_202411_AST2500_FLASH.fetch() =20 self.vm.add_args('-device', 'tmp105,bus=3Daspeed.i2c.bus.3,address=3D0x4d,id= =3Dtmp-test'); diff --git a/tests/functional/test_arm_aspeed_ast2600.py b/tests/functional= /test_arm_aspeed_ast2600.py index 21640123ee81..6ae4ed636ac3 100755 --- a/tests/functional/test_arm_aspeed_ast2600.py +++ b/tests/functional/test_arm_aspeed_ast2600.py @@ -16,15 +16,15 @@ =20 class AST2600Machine(AspeedTest): =20 - ASSET_BR2_202311_AST2600_FLASH =3D Asset( + ASSET_BR2_202411_AST2600_FLASH =3D Asset( ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' - 'images/ast2600-evb/buildroot-2023.11/flash.img'), - 'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68') + 'images/ast2600-evb/buildroot-2024.11/flash.img'), + '4bb2f3dfdea31199b51d66b42f686dc5374c144a7346fdc650194a5578b73609') =20 def test_arm_ast2600_evb_buildroot(self): self.set_machine('ast2600-evb') =20 - image_path =3D self.ASSET_BR2_202311_AST2600_FLASH.fetch() + image_path =3D self.ASSET_BR2_202411_AST2600_FLASH.fetch() =20 self.vm.add_args('-device', 'tmp105,bus=3Daspeed.i2c.bus.3,address=3D0x4d,id= =3Dtmp-test'); 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1737529789; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7t8xLV1oAxbTo2485dr0ahXFjfD7BJskv2TEDI49Ohs=; b=R7kjZizRG8ISu6rZCiAOjHPgs3ZcJ47Hfw0x+/fSRhiV6FvPH8t+UPXVyqlWFM5Y5X8OlU pKKlpgO4SIeedkmK1E81BvcXCvW56iL4Qb+BYs54gJdLLGF2NtEZALPJVuUxvu7tsQ035Q rzFtOPhNV465TFWeRMkSvHlW8BNVrDU= X-MC-Unique: EaxTZQRuMymnzKaOw4H5zQ-1 X-Mimecast-MFC-AGG-ID: EaxTZQRuMymnzKaOw4H5zQ From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Joel Stanley , Andrew Jeffery , Troy Lee , Jamin Lin , Steven Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 9/9] aspeed: Create sd devices only when defaults are enabled Date: Wed, 22 Jan 2025 08:09:09 +0100 Message-ID: <20250122070909.1138598-10-clg@redhat.com> In-Reply-To: <20250122070909.1138598-1-clg@redhat.com> References: <20250122070909.1138598-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737529840790019000 When the -nodefaults option is set, sd devices should not be automatically created by the machine. Instead they should be defined on the command line. Note that it is not currently possible to define which bus an "sd-card" device is attached to: -blockdev node-name=3Ddrive0,driver=3Dfile,filename=3D/path/to/file.img \ -device sd-card,drive=3Ddrive0,id=3Dsd0 and the first bus named "sd-bus" will be used. Signed-off-by: C=C3=A9dric Le Goater Acked-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jamin Lin --- hw/arm/aspeed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 53a859a6e4aa..d9418e2b9f2c 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -456,14 +456,14 @@ static void aspeed_machine_init(MachineState *machine) amc->i2c_init(bmc); } =20 - for (i =3D 0; i < bmc->soc->sdhci.num_slots; i++) { + for (i =3D 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++= ) { sdhci_attach_drive(&bmc->soc->sdhci.slots[i], drive_get(IF_SD, 0, i), false, false); } =20 boot_emmc =3D sc->boot_from_emmc(bmc->soc); =20 - if (bmc->soc->emmc.num_slots) { + if (bmc->soc->emmc.num_slots && defaults_enabled()) { emmc0 =3D drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emm= c); } --=20 2.48.1