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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf3221c30sm13728474f8f.32.2025.01.21.06.23.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 06:23:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737469433; x=1738074233; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=An4WuoQ9oUhjA0b8UFcs05igfO0lRfI1lKgEsGkbyfQ=; b=KkkzBTS5ciSvtq2OK554eAKDXOLXhQ2KEU1BXDdO187J9bLIuuvcUQ0pp/0tpx3+7L RyioxP70JY2TOsG/IOTRFK0s0v2MPYuFbCPdEWkkatZaWuSk5jZ9Xyxf3y7x3vEWE7NU eT6Op7mlU2pdU7IDpk4XjEI7q18fVw3ieB8wLEHk4d5mVhjh2PO69O47tqzqaZUIDnV4 obcBn7JbD99cYTCxkzDmoA9983jj2ZaOunuIsFcn5B8X6s2mekHixtS2y2b53yd/0HYL v7GG29ALGzqeg8aTjHiR4pdLVEDNNihhZiO9OfQk0aUJps5goswIlNXfRgwBfj2udROZ 523Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737469433; x=1738074233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=An4WuoQ9oUhjA0b8UFcs05igfO0lRfI1lKgEsGkbyfQ=; b=DQA9GwbQJHpFHPOj4s/k7XI2iEPpl/Wyaxd+5VKlExJyBg04x6eo2O2IQrHpmS5h4k 4Ygce7TItcLXoCKorIZM3Qnu3HyoABOpIo1JTlWJqFhu/u7v4OYR7Xll8gfICA/yF6SE yxYjh80K4cLF2dY1oAOdHfELad+bGU93vCubdaPAGk/9R7b2+Qf9y5WNKcBBZaSWuAu2 UAyXOoWzxpxzsid5A/SnE7TEbERxX/2Fyc93o4ncWLwiAwf1d+67Hs1PzT4+QeSuBIgv CIhxDld2TKZheQTUedrxhEmcZgZwBbgLtT1QOxV9/0Fj8a0F5143kP/VT03HxTZUdT/d 3u+w== X-Gm-Message-State: AOJu0Yyg11Ok7XJTbEYKap8r2bf8Wt3dw/De9qNGdQFK4nT4SD6i0U0g pEw1pk5i0/jT/HEJoaOQMqlYy2NTqeK3X1AcNjTY0My1pkc8qLrPtRV4sJIA4cZV3MHUCb4/vBS gqME= X-Gm-Gg: ASbGncuUtN+Z6Wi2EFXOOD9rEQykz64ogyFVzte9MttK8EdvvhPDbM6qBquE1rhfyrV pLQtlN9DLV1w5XyxYWtIq+TRZbLCZhfa/zH+GS6/oeY4mVsCEGLrHhaAjtWf0M5vmRidpmvmTW3 PNx9bzf987gDlJoM9Llrk2O+qA/ageLhukdPA0WrjM599keEpcpG3eYbkUL/7m+9VErcoYpcX9G pYxLG//SLwpbRQAljR/ITeRq8zR60KEFgeiq3+mODyVyPI7scJ2RgJg3rjXZAeQsWF0TLqAj6rH nJUnGVNSZA6Qx7MFVUjqN+QXxBgomRvw6si98FsCUoy7 X-Google-Smtp-Source: AGHT+IFdnHijVGQ8OHgYhsJUBUXhSM/tYw4Ahr+XweE1xA6xZ9bEyVW6TlKLZf0El257Bd7ogaAjfg== X-Received: by 2002:a5d:64ed:0:b0:386:3e87:2cd6 with SMTP id ffacd0b85a97d-38bf57b7633mr19466181f8f.38.1737469433241; Tue, 21 Jan 2025 06:23:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 02/28] target/rx: Ensure not being build on user emulation Date: Tue, 21 Jan 2025 15:23:15 +0100 Message-ID: <20250121142341.17001-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121142341.17001-1-philmd@linaro.org> References: <20250121142341.17001-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1737469648312019000 Currently only system emulation is supported. Assert no target code is built for user emulation. Remove #ifdef'ry since more work is required before being able to emulate a user process. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/cpu.h | 6 ++++-- target/rx/cpu.c | 6 ------ target/rx/helper.c | 4 ---- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5ba1874bd76..349d61c4e40 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -26,6 +26,10 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" =20 +#ifdef CONFIG_USER_ONLY +#error "RX does not support user mode emulation" +#endif + /* PSW define */ REG32(PSW, 0) FIELD(PSW, C, 0, 1) @@ -129,11 +133,9 @@ struct RXCPUClass { #define CPU_RESOLVING_TYPE TYPE_RX_CPU =20 const char *rx_crname(uint8_t cr); -#ifndef CONFIG_USER_ONLY void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -#endif /* !CONFIG_USER_ONLY */ void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 8c50c7a1bc8..aa310bd6144 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -184,13 +184,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 -#ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps rx_sysemu_ops =3D { .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, }; -#endif =20 #include "hw/core/tcg-cpu-ops.h" =20 @@ -201,11 +199,9 @@ static const TCGCPUOps rx_tcg_ops =3D { .restore_state_to_opc =3D rx_restore_state_to_opc, .tlb_fill =3D rx_cpu_tlb_fill, =20 -#ifndef CONFIG_USER_ONLY .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .cpu_exec_halt =3D rx_cpu_has_work, .do_interrupt =3D rx_cpu_do_interrupt, -#endif /* !CONFIG_USER_ONLY */ }; =20 static void rx_cpu_class_init(ObjectClass *klass, void *data) @@ -227,9 +223,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->set_pc =3D rx_cpu_set_pc; cc->get_pc =3D rx_cpu_get_pc; =20 -#ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &rx_sysemu_ops; -#endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->disas_set_info =3D rx_cpu_disas_set_info; diff --git a/target/rx/helper.c b/target/rx/helper.c index 80912e8dcb4..7f28e729891 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -40,8 +40,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int= rte) env->psw_c =3D FIELD_EX32(psw, PSW, C); } =20 -#ifndef CONFIG_USER_ONLY - #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { @@ -146,5 +144,3 @@ hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr a= ddr) { return addr; } - -#endif /* !CONFIG_USER_ONLY */ --=20 2.47.1