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Tue, 21 Jan 2025 06:25:19 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 20/28] target/riscv: Move has_work() from CPUClass to SysemuCPUOps Date: Tue, 21 Jan 2025 15:23:33 +0100 Message-ID: <20250121142341.17001-21-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121142341.17001-1-philmd@linaro.org> References: <20250121142341.17001-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1737469797256019000 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 9 +++++---- target/riscv/internals.h | 3 --- target/riscv/cpu.c | 8 +++----- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97713681cbe..32e8e064f36 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -552,10 +552,6 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteAr= ray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); -uint64_t riscv_cpu_all_pending(CPURISCVState *env); -int riscv_cpu_mirq_pending(CPURISCVState *env); -int riscv_cpu_sirq_pending(CPURISCVState *env); -int riscv_cpu_vsirq_pending(CPURISCVState *env); bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); @@ -576,6 +572,11 @@ int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(const char *optname); =20 #ifndef CONFIG_USER_ONLY +bool riscv_cpu_has_work(CPUState *cs); +uint64_t riscv_cpu_all_pending(CPURISCVState *env); +int riscv_cpu_mirq_pending(CPURISCVState *env); +int riscv_cpu_sirq_pending(CPURISCVState *env); +int riscv_cpu_vsirq_pending(CPURISCVState *env); void riscv_cpu_do_interrupt(CPUState *cpu); void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 67291933f84..86def39aec2 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -142,9 +142,6 @@ static inline float16 check_nanbox_h(CPURISCVState *env= , uint64_t f) } } =20 -/* Our implementation of CPUClass::has_work */ -bool riscv_cpu_has_work(CPUState *cs); - /* Zjpm addr masking routine */ static inline target_ulong adjust_addr_body(CPURISCVState *env, target_ulong addr, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2c..4a7e02d9a99 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1010,9 +1010,9 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } =20 +#ifndef CONFIG_USER_ONLY bool riscv_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; /* @@ -1022,10 +1022,8 @@ bool riscv_cpu_has_work(CPUState *cs) return riscv_cpu_all_pending(env) !=3D 0 || riscv_cpu_sirq_pending(env) !=3D RISCV_EXCP_NONE || riscv_cpu_vsirq_pending(env) !=3D RISCV_EXCP_NONE; -#else - return true; -#endif } +#endif /* !CONFIG_USER_ONLY */ =20 static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) { @@ -2912,6 +2910,7 @@ static int64_t riscv_get_arch_id(CPUState *cs) #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .has_work =3D riscv_cpu_has_work, .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, @@ -2933,7 +2932,6 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) &mcc->parent_phases); =20 cc->class_by_name =3D riscv_cpu_class_by_name; - cc->has_work =3D riscv_cpu_has_work; cc->mmu_index =3D riscv_cpu_mmu_index; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; --=20 2.47.1