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Tue, 21 Jan 2025 06:24:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 14/28] target/loongarch: Move has_work() from CPUClass to SysemuCPUOps Date: Tue, 21 Jan 2025 15:23:27 +0100 Message-ID: <20250121142341.17001-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121142341.17001-1-philmd@linaro.org> References: <20250121142341.17001-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1737469670456019000 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d611a604704..20aba0e1fff 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -349,11 +349,9 @@ static void loongarch_restore_state_to_opc(CPUState *c= s, } #endif /* CONFIG_TCG */ =20 +#ifndef CONFIG_USER_ONLY static bool loongarch_cpu_has_work(CPUState *cs) { -#ifdef CONFIG_USER_ONLY - return true; -#else bool has_work =3D false; =20 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && @@ -362,8 +360,8 @@ static bool loongarch_cpu_has_work(CPUState *cs) } =20 return has_work; -#endif } +#endif /* !CONFIG_USER_ONLY */ =20 static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) { @@ -835,6 +833,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps loongarch_sysemu_ops =3D { + .has_work =3D loongarch_cpu_has_work, .write_elf64_note =3D loongarch_cpu_write_elf64_note, .get_phys_page_debug =3D loongarch_cpu_get_phys_page_debug, }; @@ -860,7 +859,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) &lacc->parent_phases); =20 cc->class_by_name =3D loongarch_cpu_class_by_name; - cc->has_work =3D loongarch_cpu_has_work; cc->mmu_index =3D loongarch_cpu_mmu_index; cc->dump_state =3D loongarch_cpu_dump_state; cc->set_pc =3D loongarch_cpu_set_pc; --=20 2.47.1