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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf327574asm13594085f8f.68.2025.01.21.06.24.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 06:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737469466; x=1738074266; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JiIs8YYj06822iMH2Rgg/pc1ZfogTC4R+p3YX6Af3lQ=; b=jTB3p5lDYf3+8kBtX5RyuD6LvUrcnogsIHONfQbMgRKJCV8vIcj2LxieF5U58M5dkQ fKLJ4CAztL5Tff2TetyutnsemG4C1vj4ovtpzoOJSbuV4rtpGWQsL6f9itG0ZVH12Veu ek5na5sfAyFudb+CyDRSK3imkSKN590idOVsiQOJ/79nNr1XtzmRZCR/DXgXphxc3o5M pkizCO9xoirdwf9eIvi1HY5bsLqhslx7BnKiFwUd7DOXdIn3X51WcjTtFiFQwMYnz1EX fK9bo/BeY3kRn955PM/EHYcUrM1eELUyBt5ICG7pDsNHI019zCme//J7n0mUlHq2Kr/W vJXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737469466; x=1738074266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JiIs8YYj06822iMH2Rgg/pc1ZfogTC4R+p3YX6Af3lQ=; b=GkY82AMXbUh1hC5RI+kOVS+HuymKaHCfzDGegRPnm8wFr/ClONe/Nyj/i8OkZHmsGt J653mLj+x7xqPQ1X/Mkq6nL2L85BXUzj0kchtLBBG8mG+51x2tSstzslHsFQkCdYYnWW JaIw9T59wSygH9bubCJgaPuOggcrICBk0PZLTBMFU30W+Ye1t+gHPYusFjFnSQV5HoGt AMWb/54nwAy/the5ikZ7GWzpAtqHAVpsQfSrZEH+MV+V2WRziF2B0HCL7UwJmjE72K2I Sr4tbqXyp3b1mINU3GVheb5bfpzYVRBq6czRzrbebn1TO+m+4Q+0Gp7vkxnwKmXeZpZQ vOXA== X-Gm-Message-State: AOJu0YzPI9tqLx9xWIxwHgINWkxxVpeNOOnnaigxvB51rESnf5mQ6PvO msIY2XGIIu4z/ACbjee6ahEt0hjXcPQ0OdRhYXv95morhbp5eLCmLnL6c/J71f9Bf01EFpmhF8J fy7Y= X-Gm-Gg: ASbGncvqpaIq7zcLrgaTnTLzxyPi/7WKvFAOvb4Uam0QeLVFHmVl+nuep/1hTxP5LRi QwI9zJBtC41aw5fazEMJW5H4Lh0uPZb/LMR3u9loALGu2gGiV23h+TJDgmHKV1aBC2H+SM423pQ Dag6kIua+2FkQZstPzK+ZFKN+tfLX3YjNrR45dmdX97k0xFSD90s41bPZynk8OT5qpdiZbdbi43 xLJu2WPYhjt5RejAZ+LlLvfI2jSS6w35mJtY1/atn0+OV1VjwINx7g87CZDe7Tvd0nya2oyHiYl AxDU3ly4xYrENv+Q0vLNMS5iu63Hp8R+TqSVkY+4PYU3 X-Google-Smtp-Source: AGHT+IEqU4c1vPc61VRhbpZWCkP23zax6N4SJjoafycJSvu6Z6n9Ti+CKt0NEksxbyrgsNYG7j/HIw== X-Received: by 2002:a5d:64ee:0:b0:385:f1f2:13ee with SMTP id ffacd0b85a97d-38bf57b9426mr14843696f8f.46.1737469466639; Tue, 21 Jan 2025 06:24:26 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, Paolo Bonzini , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 09/28] target/arm: Move has_work() from CPUClass to SysemuCPUOps Date: Tue, 21 Jan 2025 15:23:22 +0100 Message-ID: <20250121142341.17001-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121142341.17001-1-philmd@linaro.org> References: <20250121142341.17001-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1737469862484019000 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 048b825a006..322c95038d5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -123,6 +123,7 @@ void arm_restore_state_to_opc(CPUState *cs, } #endif /* CONFIG_TCG */ =20 +#ifndef CONFIG_USER_ONLY /* * With SCTLR_ELx.NMI =3D=3D 0, IRQ with Superpriority is masked identical= ly with * IRQ without Superpriority. Moreover, if the GIC is configured so that @@ -141,6 +142,7 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } +#endif /* !CONFIG_USER_ONLY */ =20 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) { @@ -2671,6 +2673,7 @@ static const gchar *arm_gdb_arch_name(CPUState *cs) #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps arm_sysemu_ops =3D { + .has_work =3D arm_cpu_has_work, .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, @@ -2721,7 +2724,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_phases); =20 cc->class_by_name =3D arm_cpu_class_by_name; - cc->has_work =3D arm_cpu_has_work; cc->mmu_index =3D arm_cpu_mmu_index; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; --=20 2.47.1