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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c1664e8dsm179961565e9.1.2025.01.21.03.41.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 03:41:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737459672; x=1738064472; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6+sqenivOKOaIj/HGMbrfNMWNgVlPE7OSpRM12hfj2M=; b=tTVdLzTKZmAbxkkEyQRTJd180XusWURGXeTV9v1oQF3nzcQe/9ayODKiBLtup74tFH PGJsHaC/EAytYXrLegp0xBCNT+stc8i5tSPY2kW8lTe9rkntbBA2fQjkNCb+CCSgL5Om k0H6LbkBcOzdqPfy1YQDRoy9AK6GMlRFE8N579vrAdD/xKcs/c72xcaTO9YqbBIGjjhv JEfNZkud9BtZbV8epRLjhoRp4ySTEH2DSubYSPZ5DJH0d1BMR4sSc4Irb4nRNmUCu/o/ sZfiX9dcGOOuxnvrV3qs2L5kGJSoOej1Lbr6Be7WMvPMO8Kj31UY+LQjXzsMf+EF9pwY DtIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737459672; x=1738064472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6+sqenivOKOaIj/HGMbrfNMWNgVlPE7OSpRM12hfj2M=; b=UwQSL9qBJi1Ta4cfhcmS+hQ/7Cmzhb4PckW9XpPtkFg9BWdJZtHxs+LlX3+6x/J/8F t4u7pzBNVPKXKUEjGQFOHBGNiyEYThAfCJBJbBchVABDhMJvwctczuQ4QZUr/rVoAgQe zHc9LyGfdksLhUhY7uGUq4vOOdxfhwHQCYWCdSNA8DIKkai2tIQ6ZGS7kN/kMvNWpDKs XVH9HKSQmenku2lRQanN+50HNRLf5Pvc6qUkG0mDhJn8cNeRx6kswb6glP0MifAFKA9f Umt7lfp90hWI3lkJX3iWeZScHpkTmS+KVnWgK9yFC6v1kkRVb0TB8MVhGy5oiv8BmuIS 0ewQ== X-Gm-Message-State: AOJu0YzBpuv3/r2RRl7wHKdHtCUHyy/31EuFMSuJq5SwuPsWFRybCPw9 GjqOjV8YXxiItvEWbZYWJyys47D/pydAbQobEsfT8q/sp+npBu/FsnAZSU/NrWiecFLoXgKnzNa nhsU= X-Gm-Gg: ASbGncv0WFCgBbfzcVKiv5t8BuaLd8U6JCZ8cqRVTPHsxgi4ksWneb/FFwrKw69pyeA Hyvpf+r97iNav2/4n9ujMRm3uhB9WGK1fdudzFv10vOwVZ2e0rCQu8SxFaKi/T7hP7V6LTx/oU9 V+d+/T9FiZyrOcZegv3c4hXA+Pwa2PzXmiY77U1SIp0ghogzxBhar4BAD2yUBPFkDT9YrcwGnNP gkDlPQVE2VEXSc41q/MjOXKMjhIo+INWyLjHYi9WEurbVsxcISnpfIGhEkK4EudwBd4ELNP6NLw vmr38xJAYc3cJImlSK0QVpJ4Bt4Nh0Y0p+PlLjt5TQGr X-Google-Smtp-Source: AGHT+IFAV++RtKn1KotX+3ii/fxqKc/fb8NWI3UzdXKs0eo21SJuKzQB4kr02Ht3HAyC4Lmg9PLMTg== X-Received: by 2002:a05:600c:138f:b0:436:ed50:4f8a with SMTP id 5b1f17b1804b1-438913caeb9mr178310015e9.10.1737459672025; Tue, 21 Jan 2025 03:41:12 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 03/11] accel: Prefer cached CpuClass over CPU_GET_CLASS() macro Date: Tue, 21 Jan 2025 12:40:48 +0100 Message-ID: <20250121114056.53949-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121114056.53949-1-philmd@linaro.org> References: <20250121114056.53949-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1737459727414019000 CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/accel-target.c | 12 +++++------- accel/tcg/tcg-accel-ops.c | 3 +-- accel/tcg/translate-all.c | 2 +- accel/tcg/watchpoint.c | 9 ++++----- 4 files changed, 11 insertions(+), 15 deletions(-) diff --git a/accel/accel-target.c b/accel/accel-target.c index 08626c00c2d..8a16c0c3ae0 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -112,22 +112,20 @@ void accel_init_interfaces(AccelClass *ac) =20 void accel_cpu_instance_init(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) { - cc->accel_cpu->cpu_instance_init(cpu); + if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) { + cpu->cc->accel_cpu->cpu_instance_init(cpu); } } =20 bool accel_cpu_common_realize(CPUState *cpu, Error **errp) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); AccelState *accel =3D current_accel(); AccelClass *acc =3D ACCEL_GET_CLASS(accel); =20 /* target specific realization */ - if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize - && !cc->accel_cpu->cpu_target_realize(cpu, errp)) { + if (cpu->cc->accel_cpu + && cpu->cc->accel_cpu->cpu_target_realize + && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) { return false; } =20 diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b2..299d6176cfb 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -120,10 +120,9 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdb= type) [GDB_WATCHPOINT_ACCESS] =3D BP_GDB | BP_MEM_ACCESS, }; =20 - CPUClass *cc =3D CPU_GET_CLASS(cpu); int cputype =3D xlat[gdbtype]; =20 - if (cc->gdb_stop_before_watchpoint) { + if (cpu->cc->gdb_stop_before_watchpoint) { cputype |=3D BP_STOP_BEFORE_ACCESS; } return cputype; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d56ca13cddf..5a378cb0281 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -622,7 +622,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) * to account for the re-execution of the branch. */ n =3D 1; - cc =3D CPU_GET_CLASS(cpu); + cc =3D cpu->cc; if (cc->tcg_ops->io_recompile_replay_branch && cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { cpu->neg.icount_decr.u16.low++; diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index af57d182d5b..52e550dec6b 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -69,7 +69,6 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr a= ddr, vaddr len) void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, MemTxAttrs attrs, int flags, uintptr_t ra) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); CPUWatchpoint *wp; =20 assert(tcg_enabled()); @@ -85,9 +84,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd= r len, return; } =20 - if (cc->tcg_ops->adjust_watchpoint_address) { + if (cpu->cc->tcg_ops->adjust_watchpoint_address) { /* this is currently used only by ARM BE32 */ - addr =3D cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); + addr =3D cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, le= n); } =20 assert((flags & ~BP_MEM_ACCESS) =3D=3D 0); @@ -119,8 +118,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, wp->hitattrs =3D attrs; =20 if (wp->flags & BP_CPU - && cc->tcg_ops->debug_check_watchpoint - && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { + && cpu->cc->tcg_ops->debug_check_watchpoint + && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { wp->flags &=3D ~BP_WATCHPOINT_HIT; continue; } --=20 2.47.1