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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
<leetroy@gmail.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, "Joel
Stanley" <joel@jms.id.au>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
Date: Tue, 21 Jan 2025 15:04:07 +0800
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Reply-to: Jamin Lin <jamin_lin@aspeedtech.com>
From: Jamin Lin via <qemu-devel@nongnu.org>
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The design of the INTC has significant changes in the AST2700 A1. In the
AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
The previous INTC model only supported the AST2700 A0 and was implemented f=
or
the INTC0 (CPU DIE). To support the future INTC1 (I/O DIE) model, rename IN=
TC
to INTC0.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 6 +--
hw/intc/aspeed_intc.c | 90 +++++++++++++++++------------------
include/hw/arm/aspeed_soc.h | 2 +-
include/hw/intc/aspeed_intc.h | 2 +-
4 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 4114e15ddd..ba461fcd3c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -56,7 +56,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D {
[ASPEED_DEV_ETH2] =3D 0x14060000,
[ASPEED_DEV_ETH3] =3D 0x14070000,
[ASPEED_DEV_EMMC] =3D 0x12090000,
- [ASPEED_DEV_INTC] =3D 0x12100000,
+ [ASPEED_DEV_INTC0] =3D 0x12100000,
[ASPEED_DEV_SLI] =3D 0x12C17000,
[ASPEED_DEV_SLIIO] =3D 0x14C1E000,
[ASPEED_GIC_DIST] =3D 0x12200000,
@@ -372,7 +372,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
=20
object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLII=
O);
- object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
+ object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC0);
=20
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -517,7 +517,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev=
, Error **errp)
}
=20
aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
- sc->memmap[ASPEED_DEV_INTC]);
+ sc->memmap[ASPEED_DEV_INTC0]);
=20
/* GICINT orgates -> INTC -> GIC */
for (i =3D 0; i < ic->num_ints; i++) {
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 126b711b94..df4da759e1 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -14,27 +14,27 @@
#include "hw/registerfields.h"
#include "qapi/error.h"
=20
-/* INTC Registers */
-REG32(GICINT128_EN, 0x1000)
-REG32(GICINT128_STATUS, 0x1004)
-REG32(GICINT129_EN, 0x1100)
-REG32(GICINT129_STATUS, 0x1104)
-REG32(GICINT130_EN, 0x1200)
-REG32(GICINT130_STATUS, 0x1204)
-REG32(GICINT131_EN, 0x1300)
-REG32(GICINT131_STATUS, 0x1304)
-REG32(GICINT132_EN, 0x1400)
-REG32(GICINT132_STATUS, 0x1404)
-REG32(GICINT133_EN, 0x1500)
-REG32(GICINT133_STATUS, 0x1504)
-REG32(GICINT134_EN, 0x1600)
-REG32(GICINT134_STATUS, 0x1604)
-REG32(GICINT135_EN, 0x1700)
-REG32(GICINT135_STATUS, 0x1704)
-REG32(GICINT136_EN, 0x1800)
-REG32(GICINT136_STATUS, 0x1804)
-
-#define GICINT_STATUS_BASE R_GICINT128_STATUS
+/* AST2700 INTC0 Registers */
+REG32(INTC0_GICINT128_EN, 0x1000)
+REG32(INTC0_GICINT128_STATUS, 0x1004)
+REG32(INTC0_GICINT129_EN, 0x1100)
+REG32(INTC0_GICINT129_STATUS, 0x1104)
+REG32(INTC0_GICINT130_EN, 0x1200)
+REG32(INTC0_GICINT130_STATUS, 0x1204)
+REG32(INTC0_GICINT131_EN, 0x1300)
+REG32(INTC0_GICINT131_STATUS, 0x1304)
+REG32(INTC0_GICINT132_EN, 0x1400)
+REG32(INTC0_GICINT132_STATUS, 0x1404)
+REG32(INTC0_GICINT133_EN, 0x1500)
+REG32(INTC0_GICINT133_STATUS, 0x1504)
+REG32(INTC0_GICINT134_EN, 0x1600)
+REG32(INTC0_GICINT134_STATUS, 0x1604)
+REG32(INTC0_GICINT135_EN, 0x1700)
+REG32(INTC0_GICINT135_STATUS, 0x1704)
+REG32(INTC0_GICINT136_EN, 0x1800)
+REG32(INTC0_GICINT136_STATUS, 0x1804)
+
+#define GICINT_STATUS_BASE R_INTC0_GICINT128_STATUS
=20
static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
{
@@ -153,15 +153,15 @@ static void aspeed_intc_write(void *opaque, hwaddr of=
fset, uint64_t data,
trace_aspeed_intc_write(offset, size, data);
=20
switch (addr) {
- case R_GICINT128_EN:
- case R_GICINT129_EN:
- case R_GICINT130_EN:
- case R_GICINT131_EN:
- case R_GICINT132_EN:
- case R_GICINT133_EN:
- case R_GICINT134_EN:
- case R_GICINT135_EN:
- case R_GICINT136_EN:
+ case R_INTC0_GICINT128_EN:
+ case R_INTC0_GICINT129_EN:
+ case R_INTC0_GICINT130_EN:
+ case R_INTC0_GICINT131_EN:
+ case R_INTC0_GICINT132_EN:
+ case R_INTC0_GICINT133_EN:
+ case R_INTC0_GICINT134_EN:
+ case R_INTC0_GICINT135_EN:
+ case R_INTC0_GICINT136_EN:
irq =3D (offset & 0x0f00) >> 8;
=20
if (irq >=3D aic->num_ints) {
@@ -202,15 +202,15 @@ static void aspeed_intc_write(void *opaque, hwaddr of=
fset, uint64_t data,
}
s->regs[addr] =3D data;
break;
- case R_GICINT128_STATUS:
- case R_GICINT129_STATUS:
- case R_GICINT130_STATUS:
- case R_GICINT131_STATUS:
- case R_GICINT132_STATUS:
- case R_GICINT133_STATUS:
- case R_GICINT134_STATUS:
- case R_GICINT135_STATUS:
- case R_GICINT136_STATUS:
+ case R_INTC0_GICINT128_STATUS:
+ case R_INTC0_GICINT129_STATUS:
+ case R_INTC0_GICINT130_STATUS:
+ case R_INTC0_GICINT131_STATUS:
+ case R_INTC0_GICINT132_STATUS:
+ case R_INTC0_GICINT133_STATUS:
+ case R_INTC0_GICINT134_STATUS:
+ case R_INTC0_GICINT135_STATUS:
+ case R_INTC0_GICINT136_STATUS:
irq =3D (offset & 0x0f00) >> 8;
=20
if (irq >=3D aic->num_ints) {
@@ -336,26 +336,26 @@ static const TypeInfo aspeed_intc_info =3D {
.abstract =3D true,
};
=20
-static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
+static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc =3D DEVICE_CLASS(klass);
AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass);
=20
- dc->desc =3D "ASPEED 2700 INTC Controller";
+ dc->desc =3D "ASPEED 2700 INTC 0 Controller";
aic->num_lines =3D 32;
aic->num_ints =3D 9;
}
=20
-static const TypeInfo aspeed_2700_intc_info =3D {
- .name =3D TYPE_ASPEED_2700_INTC,
+static const TypeInfo aspeed_2700_intc0_info =3D {
+ .name =3D TYPE_ASPEED_2700_INTC0,
.parent =3D TYPE_ASPEED_INTC,
- .class_init =3D aspeed_2700_intc_class_init,
+ .class_init =3D aspeed_2700_intc0_class_init,
};
=20
static void aspeed_intc_register_types(void)
{
type_register_static(&aspeed_intc_info);
- type_register_static(&aspeed_2700_intc_info);
+ type_register_static(&aspeed_2700_intc0_info);
}
=20
type_init(aspeed_intc_register_types);
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 689f52dae8..51e585e3e4 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -194,7 +194,7 @@ enum {
ASPEED_DEV_EHCI1,
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
- ASPEED_DEV_INTC,
+ ASPEED_DEV_INTC0,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 18cb43476c..10718ed4a1 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -13,7 +13,7 @@
#include "hw/or-irq.h"
=20
#define TYPE_ASPEED_INTC "aspeed.intc"
-#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
+#define TYPE_ASPEED_2700_INTC0 TYPE_ASPEED_INTC "0" "-ast2700"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
=20
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops
Date: Tue, 21 Jan 2025 15:04:08 +0800
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From: Jamin Lin via <qemu-devel@nongnu.org>
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The previous implementation set the "aspeed_intc_ops" struct, containing re=
ad
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC0 (CPU DIE).
To support the INTC1 (I/O DIE) model, introduces a new "reg_ops" class
attribute. This allows setting different memory region operations to support
different INTC models.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 5 ++++-
include/hw/intc/aspeed_intc.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index df4da759e1..628f69ea88 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -302,7 +302,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error=
**errp)
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
int i;
=20
- memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS <<=
2);
=20
sysbus_init_mmio(sbd, &s->iomem);
@@ -319,11 +319,14 @@ static void aspeed_intc_realize(DeviceState *dev, Err=
or **errp)
static void aspeed_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass);
=20
dc->desc =3D "ASPEED INTC Controller";
dc->realize =3D aspeed_intc_realize;
device_class_set_legacy_reset(dc, aspeed_intc_reset);
dc->vmsd =3D NULL;
+
+ aic->reg_ops =3D &aspeed_intc_ops;
}
=20
static const TypeInfo aspeed_intc_info =3D {
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 10718ed4a1..9a73661403 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -39,6 +39,7 @@ struct AspeedINTCClass {
=20
uint32_t num_lines;
uint32_t num_ints;
+ const MemoryRegionOps *reg_ops;
};
=20
#endif /* ASPEED_INTC_H */
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 03/18] hw/intc/aspeed: Introduce a new
aspeed_2700_intc0_ops for INTC0
Date: Tue, 21 Jan 2025 15:04:09 +0800
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Rename "aspeed_intc_read" to "aspeed_2700_intc0_read" and "aspeed_intc_writ=
e" to
"aspeed_2700_intc0_write".
Introduce a new memory region operation, "aspeed_2700_intc0_ops", for the
AST2700 INTC0 model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 628f69ea88..219ca02940 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -114,7 +114,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, =
int level)
}
}
=20
-static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int=
size)
+static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
+ unsigned int size)
{
AspeedINTCState *s =3D ASPEED_INTC(opaque);
uint32_t addr =3D offset >> 2;
@@ -133,8 +134,8 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr o=
ffset, unsigned int size)
return value;
}
=20
-static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
- unsigned size)
+static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t =
data,
+ unsigned size)
{
AspeedINTCState *s =3D ASPEED_INTC(opaque);
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
@@ -261,8 +262,6 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
}
=20
static const MemoryRegionOps aspeed_intc_ops =3D {
- .read =3D aspeed_intc_read,
- .write =3D aspeed_intc_write,
.endianness =3D DEVICE_LITTLE_ENDIAN,
.valid =3D {
.min_access_size =3D 4,
@@ -339,6 +338,16 @@ static const TypeInfo aspeed_intc_info =3D {
.abstract =3D true,
};
=20
+static const MemoryRegionOps aspeed_2700_intc0_ops =3D {
+ .read =3D aspeed_2700_intc0_read,
+ .write =3D aspeed_2700_intc0_write,
+ .endianness =3D DEVICE_LITTLE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ }
+};
+
static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc =3D DEVICE_CLASS(klass);
@@ -347,6 +356,7 @@ static void aspeed_2700_intc0_class_init(ObjectClass *k=
lass, void *data)
dc->desc =3D "ASPEED 2700 INTC 0 Controller";
aic->num_lines =3D 32;
aic->num_ints =3D 9;
+ aic->reg_ops =3D &aspeed_2700_intc0_ops;
}
=20
static const TypeInfo aspeed_2700_intc0_info =3D {
--=20
2.34.1
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and
register size
Date: Tue, 21 Jan 2025 15:04:10 +0800
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According to the AST2700 datasheet, the INTC0 (CPU DIE) controller has 16KB
(0x4000) of register space, and the INTC1 (I/O DIE) controller has 1KB (0x4=
00)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes f=
or
the INTC models in AST2700.
Introduced a new class attribute "reg_size" to set different register sizes=
for
the INTC models in AST2700.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 17 +++++++++++++----
include/hw/intc/aspeed_intc.h | 4 ++++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 219ca02940..25035c65ca 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -118,10 +118,11 @@ static uint64_t aspeed_2700_intc0_read(void *opaque, =
hwaddr offset,
unsigned int size)
{
AspeedINTCState *s =3D ASPEED_INTC(opaque);
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
uint32_t addr =3D offset >> 2;
uint32_t value =3D 0;
=20
- if (addr >=3D ASPEED_INTC_NR_REGS) {
+ if (offset >=3D aic->reg_size) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "=
\n",
__func__, offset);
@@ -144,7 +145,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwadd=
r offset, uint64_t data,
uint32_t change;
uint32_t irq;
=20
- if (addr >=3D ASPEED_INTC_NR_REGS) {
+ if (offset >=3D aic->reg_size) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx =
"\n",
__func__, offset);
@@ -301,10 +302,16 @@ static void aspeed_intc_realize(DeviceState *dev, Err=
or **errp)
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
int i;
=20
+ memory_region_init(&s->iomem_container, OBJECT(s),
+ TYPE_ASPEED_INTC ".container", aic->mem_size);
+
+ sysbus_init_mmio(sbd, &s->iomem_container);
+
memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
- TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS <<=
2);
+ TYPE_ASPEED_INTC ".regs", aic->reg_size);
+
+ memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
=20
- sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
=20
for (i =3D 0; i < aic->num_ints; i++) {
@@ -357,6 +364,8 @@ static void aspeed_2700_intc0_class_init(ObjectClass *k=
lass, void *data)
aic->num_lines =3D 32;
aic->num_ints =3D 9;
aic->reg_ops =3D &aspeed_2700_intc0_ops;
+ aic->mem_size =3D 0x4000;
+ aic->reg_size =3D 0x2000;
}
=20
static const TypeInfo aspeed_2700_intc0_info =3D {
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 9a73661403..d881cb7088 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -25,6 +25,8 @@ struct AspeedINTCState {
=20
/*< public >*/
MemoryRegion iomem;
+ MemoryRegion iomem_container;
+
uint32_t regs[ASPEED_INTC_NR_REGS];
OrIRQState orgates[ASPEED_INTC_NR_INTS];
qemu_irq output_pins[ASPEED_INTC_NR_INTS];
@@ -40,6 +42,8 @@ struct AspeedINTCClass {
uint32_t num_lines;
uint32_t num_ints;
const MemoryRegionOps *reg_ops;
+ uint64_t mem_size;
+ uint64_t reg_size;
};
=20
#endif /* ASPEED_INTC_H */
--=20
2.34.1
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for
enable and status registers
Date: Tue, 21 Jan 2025 15:04:11 +0800
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The behavior of the enable and status registers is almost identical between
INTC0 and INTC1. To reduce duplicated code, adds
"aspeed_2700_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_2700_intc_status_handler" functions to handle status
register write behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 189 ++++++++++++++++++++++++------------------
1 file changed, 107 insertions(+), 82 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 25035c65ca..7dff5e6039 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -114,6 +114,111 @@ static void aspeed_intc_set_irq(void *opaque, int irq=
, int level)
}
}
=20
+static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t a=
ddr,
+ uint64_t data)
+{
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
+ uint32_t offset =3D addr << 2;
+ uint32_t old_enable;
+ uint32_t change;
+ uint32_t irq;
+
+ irq =3D (offset & 0x0f00) >> 8;
+
+ if (irq >=3D aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n=
",
+ __func__, irq);
+ return;
+ }
+
+ /*
+ * The enable registers are used to enable source interrupts.
+ * They also handle masking and unmasking of source interrupts
+ * during the execution of the source ISR.
+ */
+
+ /* disable all source interrupt */
+ if (!data && !s->enable[irq]) {
+ s->regs[addr] =3D data;
+ return;
+ }
+
+ old_enable =3D s->enable[irq];
+ s->enable[irq] |=3D data;
+
+ /* enable new source interrupt */
+ if (old_enable !=3D s->enable[irq]) {
+ trace_aspeed_intc_enable(s->enable[irq]);
+ s->regs[addr] =3D data;
+ return;
+ }
+
+ /* mask and unmask source interrupt */
+ change =3D s->regs[addr] ^ data;
+ if (change & data) {
+ s->mask[irq] &=3D ~change;
+ trace_aspeed_intc_unmask(change, s->mask[irq]);
+ } else {
+ s->mask[irq] |=3D change;
+ trace_aspeed_intc_mask(change, s->mask[irq]);
+ }
+ s->regs[addr] =3D data;
+}
+
+static void aspeed_2700_intc_status_handler(AspeedINTCState *s, uint32_t a=
ddr,
+ uint64_t data)
+{
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
+ uint32_t offset =3D addr << 2;
+ uint32_t irq;
+
+ irq =3D (offset & 0x0f00) >> 8;
+
+ if (!data) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
+ return;
+ }
+
+ if (irq >=3D aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n=
",
+ __func__, irq);
+ return;
+ }
+
+ /* clear status */
+ s->regs[addr] &=3D ~data;
+
+ /*
+ * The status registers are used for notify sources ISR are executed.
+ * If one source ISR is executed, it will clear one bit.
+ * If it clear all bits, it means to initialize this register status
+ * rather than sources ISR are executed.
+ */
+ if (data =3D=3D 0xffffffff) {
+ return;
+ }
+
+ /* All source ISR execution are done */
+ if (!s->regs[addr]) {
+ trace_aspeed_intc_all_isr_done(irq);
+ if (s->pending[irq]) {
+ /*
+ * handle pending source interrupt
+ * notify firmware which source interrupt are pending
+ * by setting status register
+ */
+ s->regs[addr] =3D s->pending[irq];
+ s->pending[irq] =3D 0;
+ trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
+ aspeed_intc_update(s, irq, 1);
+ } else {
+ /* clear irq */
+ trace_aspeed_intc_clear_irq(irq, 0);
+ aspeed_intc_update(s, irq, 0);
+ }
+ }
+}
+
static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
unsigned int size)
{
@@ -141,9 +246,6 @@ static void aspeed_2700_intc0_write(void *opaque, hwadd=
r offset, uint64_t data,
AspeedINTCState *s =3D ASPEED_INTC(opaque);
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
uint32_t addr =3D offset >> 2;
- uint32_t old_enable;
- uint32_t change;
- uint32_t irq;
=20
if (offset >=3D aic->reg_size) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -164,45 +266,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwad=
dr offset, uint64_t data,
case R_INTC0_GICINT134_EN:
case R_INTC0_GICINT135_EN:
case R_INTC0_GICINT136_EN:
- irq =3D (offset & 0x0f00) >> 8;
-
- if (irq >=3D aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: =
%d\n",
- __func__, irq);
- return;
- }
-
- /*
- * These registers are used for enable sources interrupt and
- * mask and unmask source interrupt while executing source ISR.
- */
-
- /* disable all source interrupt */
- if (!data && !s->enable[irq]) {
- s->regs[addr] =3D data;
- return;
- }
-
- old_enable =3D s->enable[irq];
- s->enable[irq] |=3D data;
-
- /* enable new source interrupt */
- if (old_enable !=3D s->enable[irq]) {
- trace_aspeed_intc_enable(s->enable[irq]);
- s->regs[addr] =3D data;
- return;
- }
-
- /* mask and unmask source interrupt */
- change =3D s->regs[addr] ^ data;
- if (change & data) {
- s->mask[irq] &=3D ~change;
- trace_aspeed_intc_unmask(change, s->mask[irq]);
- } else {
- s->mask[irq] |=3D change;
- trace_aspeed_intc_mask(change, s->mask[irq]);
- }
- s->regs[addr] =3D data;
+ aspeed_2700_intc_enable_handler(s, addr, data);
break;
case R_INTC0_GICINT128_STATUS:
case R_INTC0_GICINT129_STATUS:
@@ -213,46 +277,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwad=
dr offset, uint64_t data,
case R_INTC0_GICINT134_STATUS:
case R_INTC0_GICINT135_STATUS:
case R_INTC0_GICINT136_STATUS:
- irq =3D (offset & 0x0f00) >> 8;
-
- if (irq >=3D aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: =
%d\n",
- __func__, irq);
- return;
- }
-
- /* clear status */
- s->regs[addr] &=3D ~data;
-
- /*
- * These status registers are used for notify sources ISR are exec=
uted.
- * If one source ISR is executed, it will clear one bit.
- * If it clear all bits, it means to initialize this register stat=
us
- * rather than sources ISR are executed.
- */
- if (data =3D=3D 0xffffffff) {
- return;
- }
-
- /* All source ISR execution are done */
- if (!s->regs[addr]) {
- trace_aspeed_intc_all_isr_done(irq);
- if (s->pending[irq]) {
- /*
- * handle pending source interrupt
- * notify firmware which source interrupt are pending
- * by setting status register
- */
- s->regs[addr] =3D s->pending[irq];
- s->pending[irq] =3D 0;
- trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
- aspeed_intc_update(s, irq, 1);
- } else {
- /* clear irq */
- trace_aspeed_intc_clear_irq(irq, 0);
- aspeed_intc_update(s, irq, 0);
- }
- }
+ aspeed_2700_intc_status_handler(s, addr, data);
break;
default:
s->regs[addr] =3D data;
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to
save the irq index and register address
Date: Tue, 21 Jan 2025 15:04:12 +0800
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Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org
X-ZM-MESSAGEID: 1737443308113019000
Content-Type: text/plain; charset="utf-8"
The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to input =
and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC0 controller also supports GICINT192_201, mapping 1 input =
IRQ
pin to 10 output IRQ pins. The pin numbers for input and output are differe=
nt.
Additionally, the INTC0 controller supports routing to GIC, SSP, TSP, and
BOOTMCU, making it difficult to use a formula to determine the index number=
of
INTC0 model supported input and output IRQs.
To simplify and improve readability, introduces the AspeedINTCIRQ structure=
to
save the input/output IRQ index and its enable/status register address.
Introduce the "aspeed_2700_intc0_irqs" table to store IRQ information for I=
NTC0.
Introduce the "aspeed_intc_get_irq" function to retrieve the input/output I=
RQ
pin index from the provided status/enable register address.
Update the code to use "num_inpins" and "num_outpins" instead of "num_ints".
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 2 +-
hw/intc/aspeed_intc.c | 165 ++++++++++++++++++++++------------
hw/intc/trace-events | 12 +--
include/hw/intc/aspeed_intc.h | 26 ++++--
4 files changed, 135 insertions(+), 70 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index ba461fcd3c..d5e521cd38 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -520,7 +520,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev=
, Error **errp)
sc->memmap[ASPEED_DEV_INTC0]);
=20
/* GICINT orgates -> INTC -> GIC */
- for (i =3D 0; i < ic->num_ints; i++) {
+ for (i =3D 0; i < ic->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc), i));
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 7dff5e6039..45f1c59a4b 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -34,20 +34,61 @@ REG32(INTC0_GICINT135_STATUS, 0x1704)
REG32(INTC0_GICINT136_EN, 0x1800)
REG32(INTC0_GICINT136_STATUS, 0x1804)
=20
-#define GICINT_STATUS_BASE R_INTC0_GICINT128_STATUS
+static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_MAX_INPINS] =3D {
+ {0, 0, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
+ {1, 1, 1, R_INTC0_GICINT129_EN, R_INTC0_GICINT129_STATUS},
+ {2, 2, 1, R_INTC0_GICINT130_EN, R_INTC0_GICINT130_STATUS},
+ {3, 3, 1, R_INTC0_GICINT131_EN, R_INTC0_GICINT131_STATUS},
+ {4, 4, 1, R_INTC0_GICINT132_EN, R_INTC0_GICINT132_STATUS},
+ {5, 5, 1, R_INTC0_GICINT133_EN, R_INTC0_GICINT133_STATUS},
+ {6, 6, 1, R_INTC0_GICINT134_EN, R_INTC0_GICINT134_STATUS},
+ {7, 7, 1, R_INTC0_GICINT135_EN, R_INTC0_GICINT135_STATUS},
+ {8, 8, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
+};
+
+static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
+ uint32_t addr)
+{
+ int i;
+
+ for (i =3D 0; i < aic->irq_table_count; i++) {
+ if (aic->irq_table[i].enable_addr =3D=3D addr ||
+ aic->irq_table[i].status_addr =3D=3D addr) {
+ return &aic->irq_table[i];
+ }
+ }
+
+ /*
+ * Invalid addr.
+ */
+ g_assert_not_reached();
+}
=20
-static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
+/*
+ * Update the state of an interrupt controller pin by setting
+ * the specified output pin to the given level.
+ * The input pin index should be between 0 and the number of input pins.
+ * The output pin index should be between 0 and the number of output pins.
+ */
+static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx,
+ int outpin_idx, int level)
{
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
=20
- if (irq >=3D aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n=
",
- __func__, irq);
+ if (inpin_idx >=3D aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n",
+ __func__, inpin_idx);
+ return;
+ }
+
+ if (outpin_idx >=3D aic->num_outpins) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid output pin index: %d\n=
",
+ __func__, outpin_idx);
return;
}
=20
- trace_aspeed_intc_update_irq(irq, level);
- qemu_set_irq(s->output_pins[irq], level);
+ trace_aspeed_intc_update_irq(inpin_idx, outpin_idx, level);
+ qemu_set_irq(s->output_pins[outpin_idx], level);
}
=20
/*
@@ -56,30 +97,33 @@ static void aspeed_intc_update(AspeedINTCState *s, int =
irq, int level)
* The value of irq should be 0 to num_ints.
* The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
*/
-static void aspeed_intc_set_irq(void *opaque, int irq, int level)
+static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
{
AspeedINTCState *s =3D (AspeedINTCState *)opaque;
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
- uint32_t status_addr =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
+ const AspeedINTCIRQ *irq;
uint32_t select =3D 0;
uint32_t enable;
int i;
=20
- if (irq >=3D aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n=
",
- __func__, irq);
+ if (irq_idx >=3D aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input interrupt number: %d\n",
+ __func__, irq_idx);
return;
}
=20
- trace_aspeed_intc_set_irq(irq, level);
- enable =3D s->enable[irq];
+ irq =3D &aic->irq_table[irq_idx];
+
+ trace_aspeed_intc_set_irq(irq->inpin_idx, level);
+ enable =3D s->enable[irq->inpin_idx];
=20
if (!level) {
return;
}
=20
for (i =3D 0; i < aic->num_lines; i++) {
- if (s->orgates[irq].levels[i]) {
+ if (s->orgates[irq->inpin_idx].levels[i]) {
if (enable & BIT(i)) {
select |=3D BIT(i);
}
@@ -92,7 +136,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, i=
nt level)
=20
trace_aspeed_intc_select(select);
=20
- if (s->mask[irq] || s->regs[status_addr]) {
+ if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
/*
* a. mask is not 0 means in ISR mode
* sources interrupt routine are executing.
@@ -101,16 +145,18 @@ static void aspeed_intc_set_irq(void *opaque, int irq=
, int level)
*
* save source interrupt to pending variable.
*/
- s->pending[irq] |=3D select;
- trace_aspeed_intc_pending_irq(irq, s->pending[irq]);
+ s->pending[irq->inpin_idx] |=3D select;
+ trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ s->pending[irq->inpin_idx]);
} else {
/*
* notify firmware which source interrupt are coming
* by setting status register
*/
- s->regs[status_addr] =3D select;
- trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]);
- aspeed_intc_update(s, irq, 1);
+ s->regs[irq->status_addr] =3D select;
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ s->regs[irq->status_addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
}
}
=20
@@ -118,16 +164,16 @@ static void aspeed_2700_intc_enable_handler(AspeedINT=
CState *s, uint32_t addr,
uint64_t data)
{
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
- uint32_t offset =3D addr << 2;
+ const AspeedINTCIRQ *irq;
uint32_t old_enable;
uint32_t change;
- uint32_t irq;
=20
- irq =3D (offset & 0x0f00) >> 8;
+ irq =3D aspeed_intc_get_irq(aic, addr);
=20
- if (irq >=3D aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n=
",
- __func__, irq);
+ if (irq->inpin_idx >=3D aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input pin index number: %d\n",
+ __func__, irq->inpin_idx);
return;
}
=20
@@ -138,17 +184,17 @@ static void aspeed_2700_intc_enable_handler(AspeedINT=
CState *s, uint32_t addr,
*/
=20
/* disable all source interrupt */
- if (!data && !s->enable[irq]) {
+ if (!data && !s->enable[irq->inpin_idx]) {
s->regs[addr] =3D data;
return;
}
=20
- old_enable =3D s->enable[irq];
- s->enable[irq] |=3D data;
+ old_enable =3D s->enable[irq->inpin_idx];
+ s->enable[irq->inpin_idx] |=3D data;
=20
/* enable new source interrupt */
- if (old_enable !=3D s->enable[irq]) {
- trace_aspeed_intc_enable(s->enable[irq]);
+ if (old_enable !=3D s->enable[irq->inpin_idx]) {
+ trace_aspeed_intc_enable(s->enable[irq->inpin_idx]);
s->regs[addr] =3D data;
return;
}
@@ -156,11 +202,11 @@ static void aspeed_2700_intc_enable_handler(AspeedINT=
CState *s, uint32_t addr,
/* mask and unmask source interrupt */
change =3D s->regs[addr] ^ data;
if (change & data) {
- s->mask[irq] &=3D ~change;
- trace_aspeed_intc_unmask(change, s->mask[irq]);
+ s->mask[irq->inpin_idx] &=3D ~change;
+ trace_aspeed_intc_unmask(change, s->mask[irq->inpin_idx]);
} else {
- s->mask[irq] |=3D change;
- trace_aspeed_intc_mask(change, s->mask[irq]);
+ s->mask[irq->inpin_idx] |=3D change;
+ trace_aspeed_intc_mask(change, s->mask[irq->inpin_idx]);
}
s->regs[addr] =3D data;
}
@@ -169,19 +215,19 @@ static void aspeed_2700_intc_status_handler(AspeedINT=
CState *s, uint32_t addr,
uint64_t data)
{
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
- uint32_t offset =3D addr << 2;
- uint32_t irq;
-
- irq =3D (offset & 0x0f00) >> 8;
+ const AspeedINTCIRQ *irq;
=20
if (!data) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
return;
}
=20
- if (irq >=3D aic->num_ints) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n=
",
- __func__, irq);
+ irq =3D aspeed_intc_get_irq(aic, addr);
+
+ if (irq->inpin_idx >=3D aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input pin index number: %d\n",
+ __func__, irq->inpin_idx);
return;
}
=20
@@ -200,21 +246,22 @@ static void aspeed_2700_intc_status_handler(AspeedINT=
CState *s, uint32_t addr,
=20
/* All source ISR execution are done */
if (!s->regs[addr]) {
- trace_aspeed_intc_all_isr_done(irq);
- if (s->pending[irq]) {
+ trace_aspeed_intc_all_isr_done(irq->inpin_idx);
+ if (s->pending[irq->inpin_idx]) {
/*
* handle pending source interrupt
* notify firmware which source interrupt are pending
* by setting status register
*/
- s->regs[addr] =3D s->pending[irq];
- s->pending[irq] =3D 0;
- trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
- aspeed_intc_update(s, irq, 1);
+ s->regs[addr] =3D s->pending[irq->inpin_idx];
+ s->pending[irq->inpin_idx] =3D 0;
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ s->regs[addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
} else {
/* clear irq */
- trace_aspeed_intc_clear_irq(irq, 0);
- aspeed_intc_update(s, irq, 0);
+ trace_aspeed_intc_clear_irq(irq->inpin_idx, irq->outpin_idx, 0=
);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 0);
}
}
}
@@ -301,8 +348,8 @@ static void aspeed_intc_instance_init(Object *obj)
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
int i;
=20
- assert(aic->num_ints <=3D ASPEED_INTC_NR_INTS);
- for (i =3D 0; i < aic->num_ints; i++) {
+ assert(aic->num_inpins <=3D ASPEED_INTC_MAX_INPINS);
+ for (i =3D 0; i < aic->num_inpins; i++) {
object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i],
TYPE_OR_IRQ);
object_property_set_int(OBJECT(&s->orgates[i]), "num-lines",
@@ -337,12 +384,15 @@ static void aspeed_intc_realize(DeviceState *dev, Err=
or **errp)
=20
memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
=20
- qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
+ qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins);
=20
- for (i =3D 0; i < aic->num_ints; i++) {
+ for (i =3D 0; i < aic->num_inpins; i++) {
if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
return;
}
+ }
+
+ for (i =3D 0; i < aic->num_outpins; i++) {
sysbus_init_irq(sbd, &s->output_pins[i]);
}
}
@@ -387,10 +437,13 @@ static void aspeed_2700_intc0_class_init(ObjectClass =
*klass, void *data)
=20
dc->desc =3D "ASPEED 2700 INTC 0 Controller";
aic->num_lines =3D 32;
- aic->num_ints =3D 9;
+ aic->num_inpins =3D 9;
+ aic->num_outpins =3D 9;
aic->reg_ops =3D &aspeed_2700_intc0_ops;
aic->mem_size =3D 0x4000;
aic->reg_size =3D 0x2000;
+ aic->irq_table =3D aspeed_2700_intc0_irqs;
+ aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intc0_irqs);
}
=20
static const TypeInfo aspeed_2700_intc0_info =3D {
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 3dcf147198..af9703e1b5 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -82,12 +82,12 @@ aspeed_vic_write(uint64_t offset, unsigned size, uint32=
_t data) "To 0x%" PRIx64
# aspeed_intc.c
aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%=
" PRIx64 " of size %u: 0x%" PRIx32
aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" =
PRIx64 " of size %u: 0x%" PRIx32
-aspeed_intc_set_irq(int irq, int level) "Set IRQ %d: %d"
-aspeed_intc_clear_irq(int irq, int level) "Clear IRQ %d: %d"
-aspeed_intc_update_irq(int irq, int level) "Update IRQ: %d: %d"
-aspeed_intc_pending_irq(int irq, uint32_t value) "Pending IRQ: %d: 0x%x"
-aspeed_intc_trigger_irq(int irq, uint32_t value) "Trigger IRQ: %d: 0x%x"
-aspeed_intc_all_isr_done(int irq) "All source ISR execution are done: %d"
+aspeed_intc_set_irq(int inpin_idx, int level) "Set IRQ %d: %d"
+aspeed_intc_clear_irq(int inpin_idx, int outpin_idx, int level) "Clear IRQ=
%d-%d: %d"
+aspeed_intc_update_irq(int inpin_idx, int outpin_idx, int level) "Update I=
RQ: %d-%d: %d"
+aspeed_intc_pending_irq(int inpin_idx, uint32_t value) "Pending IRQ: %d: 0=
x%x"
+aspeed_intc_trigger_irq(int inpin_idx, int outpin_idx, uint32_t value) "Tr=
igger IRQ: %d-%d: 0x%x"
+aspeed_intc_all_isr_done(int inpin_idx) "All source ISR execution are done=
: %d"
aspeed_intc_enable(uint32_t value) "Enable: 0x%x"
aspeed_intc_select(uint32_t value) "Select: 0x%x"
aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x"
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index d881cb7088..73261037ea 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,7 +17,16 @@
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
=20
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
-#define ASPEED_INTC_NR_INTS 9
+#define ASPEED_INTC_MAX_INPINS 9
+#define ASPEED_INTC_MAX_OUTPINS 9
+
+typedef struct AspeedINTCIRQ {
+ int inpin_idx;
+ int outpin_idx;
+ int num_outpins;
+ uint32_t enable_addr;
+ uint32_t status_addr;
+} AspeedINTCIRQ;
=20
struct AspeedINTCState {
/*< private >*/
@@ -28,22 +37,25 @@ struct AspeedINTCState {
MemoryRegion iomem_container;
=20
uint32_t regs[ASPEED_INTC_NR_REGS];
- OrIRQState orgates[ASPEED_INTC_NR_INTS];
- qemu_irq output_pins[ASPEED_INTC_NR_INTS];
+ OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
+ qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
=20
- uint32_t enable[ASPEED_INTC_NR_INTS];
- uint32_t mask[ASPEED_INTC_NR_INTS];
- uint32_t pending[ASPEED_INTC_NR_INTS];
+ uint32_t enable[ASPEED_INTC_MAX_INPINS];
+ uint32_t mask[ASPEED_INTC_MAX_INPINS];
+ uint32_t pending[ASPEED_INTC_MAX_INPINS];
};
=20
struct AspeedINTCClass {
SysBusDeviceClass parent_class;
=20
uint32_t num_lines;
- uint32_t num_ints;
+ uint32_t num_inpins;
+ uint32_t num_outpins;
const MemoryRegionOps *reg_ops;
uint64_t mem_size;
uint64_t reg_size;
+ const AspeedINTCIRQ *irq_table;
+ int irq_table_count;
};
=20
#endif /* ASPEED_INTC_H */
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
<leetroy@gmail.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, "Joel
Stanley" <joel@jms.id.au>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to
reduce code duplication
Date: Tue, 21 Jan 2025 15:04:13 +0800
Message-ID: <20250121070424.2465942-8-jamin_lin@aspeedtech.com>
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The behavior of the INTC set IRQ is almost identical between INTC0 and INTC=
1.
To reduce duplicated code, introduce the `aspeed_intc_set_irq_handler` func=
tion
to handle both INTC0 and INTC1 IRQ behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 56 +++++++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 45f1c59a4b..8684d41ef6 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -91,11 +91,36 @@ static void aspeed_intc_update(AspeedINTCState *s, int =
inpin_idx,
qemu_set_irq(s->output_pins[outpin_idx], level);
}
=20
+static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
+ const AspeedINTCIRQ *irq, uint32_t select)
+{
+ if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
+ /*
+ * a. mask is not 0 means in ISR mode
+ * sources interrupt routine are executing.
+ * b. status register value is not 0 means previous
+ * source interrupt does not be executed, yet.
+ *
+ * save source interrupt to pending variable.
+ */
+ s->pending[irq->inpin_idx] |=3D select;
+ trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ s->pending[irq->inpin_idx]);
+ } else {
+ /*
+ * notify firmware which source interrupt are coming
+ * by setting status register
+ */
+ s->regs[irq->status_addr] =3D select;
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ s->regs[irq->status_addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
+ }
+}
+
/*
- * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
- * Utilize "address & 0x0f00" to get the irq and irq output pin index
- * The value of irq should be 0 to num_ints.
- * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
+ * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8.
+ * The value of input IRQ should be between 0 and the number of inputs.
*/
static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
{
@@ -136,28 +161,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq_=
idx, int level)
=20
trace_aspeed_intc_select(select);
=20
- if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
- /*
- * a. mask is not 0 means in ISR mode
- * sources interrupt routine are executing.
- * b. status register value is not 0 means previous
- * source interrupt does not be executed, yet.
- *
- * save source interrupt to pending variable.
- */
- s->pending[irq->inpin_idx] |=3D select;
- trace_aspeed_intc_pending_irq(irq->inpin_idx,
- s->pending[irq->inpin_idx]);
- } else {
- /*
- * notify firmware which source interrupt are coming
- * by setting status register
- */
- s->regs[irq->status_addr] =3D select;
- trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
- s->regs[irq->status_addr]);
- aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
- }
+ aspeed_intc_set_irq_handler(s, irq, select);
}
=20
static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t a=
ddr,
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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Stanley" <joel@jms.id.au>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ
Handling
Date: Tue, 21 Jan 2025 15:04:14 +0800
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This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 =
maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_outpins" to handle IRQs with
multiple output pins. Introduced "aspeed_2700_intc_status_handler_multi_out=
pins"
for managing status registers associated with multi-output IRQs.
Added new IRQ definitions for GICINT192_201 in INTC0.
Adjusted the IRQ array to accommodate 10 input pins and 19 output pins,
aligning with the new GICINT192_201 mappings.
+------------------------------+
| INTC0 |
|inpin[0:0]--------->outpin[0] |
|inpin[0:1]|-------->outpin[1] |
|inpin[0:2]|-------->outpin[2] |
|inpin[0:3]|-------->outpin[3] |
orgates[0]+------> |inpin[0:4]|-------->outpin[4] |
|inpin[0:5]|-------->outpin[5] |
|inpin[0:6]|-------->outpin[6] |
|inpin[0:7]|-------->outpin[7] |
|inpin[0:8]|-------->outpin[8] |
|inpin[0:9]--------->outpin[9] |
| |
orgates[1]------> |inpin[1]+---------->outpin[10]|
orgates[2]|-----> |inpin[2]|---------->outpin[11]|
orgates[3]|-----> |inpin[3]|---------->outpin[12]|
orgates[4]|-----> |inpin[4]|---------->outpin[13]|
orgates[5]|-----> |inpin[5]|---------->outpin[14]|
orgates[6]|-----> |inpin[6]|---------->outpin[15]|
orgates[7]|-----> |inpin[7]|---------->outpin[16]|
orgates[8]|-----> |inpin[8]|---------->outpin[17]|
orgates[9]+-----> |inpin[9]|---------->outpin[18]|
+------------------------------+
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 137 ++++++++++++++++++++++++++++++----
hw/intc/trace-events | 1 +
include/hw/intc/aspeed_intc.h | 4 +-
3 files changed, 126 insertions(+), 16 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 8684d41ef6..2f704d6cd2 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -33,17 +33,20 @@ REG32(INTC0_GICINT135_EN, 0x1700)
REG32(INTC0_GICINT135_STATUS, 0x1704)
REG32(INTC0_GICINT136_EN, 0x1800)
REG32(INTC0_GICINT136_STATUS, 0x1804)
+REG32(INTC0_GICINT192_201_EN, 0x1B00)
+REG32(INTC0_GICINT192_201_STATUS, 0x1B04)
=20
static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_MAX_INPINS] =3D {
- {0, 0, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
- {1, 1, 1, R_INTC0_GICINT129_EN, R_INTC0_GICINT129_STATUS},
- {2, 2, 1, R_INTC0_GICINT130_EN, R_INTC0_GICINT130_STATUS},
- {3, 3, 1, R_INTC0_GICINT131_EN, R_INTC0_GICINT131_STATUS},
- {4, 4, 1, R_INTC0_GICINT132_EN, R_INTC0_GICINT132_STATUS},
- {5, 5, 1, R_INTC0_GICINT133_EN, R_INTC0_GICINT133_STATUS},
- {6, 6, 1, R_INTC0_GICINT134_EN, R_INTC0_GICINT134_STATUS},
- {7, 7, 1, R_INTC0_GICINT135_EN, R_INTC0_GICINT135_STATUS},
- {8, 8, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
+ {0, 0, 10, R_INTC0_GICINT192_201_EN, R_INTC0_GICINT192_201_STATUS},
+ {1, 10, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
+ {2, 11, 1, R_INTC0_GICINT129_EN, R_INTC0_GICINT129_STATUS},
+ {3, 12, 1, R_INTC0_GICINT130_EN, R_INTC0_GICINT130_STATUS},
+ {4, 13, 1, R_INTC0_GICINT131_EN, R_INTC0_GICINT131_STATUS},
+ {5, 14, 1, R_INTC0_GICINT132_EN, R_INTC0_GICINT132_STATUS},
+ {6, 15, 1, R_INTC0_GICINT133_EN, R_INTC0_GICINT133_STATUS},
+ {7, 16, 1, R_INTC0_GICINT134_EN, R_INTC0_GICINT134_STATUS},
+ {8, 17, 1, R_INTC0_GICINT135_EN, R_INTC0_GICINT135_STATUS},
+ {9, 18, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
};
=20
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
@@ -118,9 +121,46 @@ static void aspeed_intc_set_irq_handler(AspeedINTCStat=
e *s,
}
}
=20
+static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
+ const AspeedINTCIRQ *irq, uint32_t se=
lect)
+{
+ int i;
+
+ for (i =3D 0; i < irq->num_outpins; i++) {
+ if (select & BIT(i)) {
+ if (s->mask[irq->inpin_idx] & BIT(i) ||
+ s->regs[irq->status_addr] & BIT(i)) {
+ /*
+ * a. mask bit is not 0 means in ISR mode sources interrupt
+ * routine are executing.
+ * b. status bit is not 0 means previous source interrupt
+ * does not be executed, yet.
+ *
+ * save source interrupt to pending bit.
+ */
+ s->pending[irq->inpin_idx] |=3D BIT(i);
+ trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ s->pending[irq->inpin_idx]);
+ } else {
+ /*
+ * notify firmware which source interrupt are coming
+ * by setting status bit
+ */
+ s->regs[irq->status_addr] |=3D BIT(i);
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ irq->outpin_idx + i,
+ s->regs[irq->status_addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i,=
1);
+ }
+ }
+ }
+}
+
/*
- * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8.
- * The value of input IRQ should be between 0 and the number of inputs.
+ * GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9.
+ * GICINT128 to GICINT136 map 1:1 to input IRQs 1 to 9 and output
+ * IRQs 10 to 18. The value of input IRQ should be between 0 and
+ * the number of input pins.
*/
static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
{
@@ -161,7 +201,11 @@ static void aspeed_intc_set_irq(void *opaque, int irq_=
idx, int level)
=20
trace_aspeed_intc_select(select);
=20
- aspeed_intc_set_irq_handler(s, irq, select);
+ if (irq->num_outpins > 1) {
+ aspeed_intc_set_irq_handler_multi_outpins(s, irq, select);
+ } else {
+ aspeed_intc_set_irq_handler(s, irq, select);
+ }
}
=20
static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t a=
ddr,
@@ -270,6 +314,67 @@ static void aspeed_2700_intc_status_handler(AspeedINTC=
State *s, uint32_t addr,
}
}
=20
+static void aspeed_2700_intc_status_handler_multi_outpins(AspeedINTCState =
*s,
+ uint32_t addr, uint64_t da=
ta)
+{
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
+ const AspeedINTCIRQ *irq;
+ int i;
+
+ if (!data) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
+ return;
+ }
+
+ irq =3D aspeed_intc_get_irq(aic, addr);
+
+ if (irq->inpin_idx >=3D aic->num_inpins) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Invalid input pin index number: %d\n",
+ __func__, irq->inpin_idx);
+ return;
+ }
+
+ /* clear status */
+ s->regs[addr] &=3D ~data;
+
+ /*
+ * The status registers are used for notify sources ISR are executed.
+ * If one source ISR is executed, it will clear one bit.
+ * If it clear all bits, it means to initialize this register status
+ * rather than sources ISR are executed.
+ */
+ if (data =3D=3D 0xffffffff) {
+ return;
+ }
+
+ for (i =3D 0; i < irq->num_outpins; i++) {
+ /* All source ISR executions are done from a specific bit */
+ if (data & BIT(i)) {
+ trace_aspeed_intc_all_isr_done_bit(irq->inpin_idx, i);
+ if (s->pending[irq->inpin_idx] & BIT(i)) {
+ /*
+ * Handle pending source interrupt.
+ * Notify firmware which source interrupt is pending
+ * by setting the status bit.
+ */
+ s->regs[addr] |=3D BIT(i);
+ s->pending[irq->inpin_idx] &=3D ~BIT(i);
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ irq->outpin_idx + i,
+ s->regs[addr]);
+ aspeed_intc_update(s, irq->inpin_idx,
+ irq->outpin_idx + i, 1);
+ } else {
+ /* clear irq for the specific bit */
+ trace_aspeed_intc_clear_irq(irq->inpin_idx,
+ irq->outpin_idx + i, 0);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i,=
0);
+ }
+ }
+ }
+}
+
static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
unsigned int size)
{
@@ -317,6 +422,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwadd=
r offset, uint64_t data,
case R_INTC0_GICINT134_EN:
case R_INTC0_GICINT135_EN:
case R_INTC0_GICINT136_EN:
+ case R_INTC0_GICINT192_201_EN:
aspeed_2700_intc_enable_handler(s, addr, data);
break;
case R_INTC0_GICINT128_STATUS:
@@ -330,6 +436,9 @@ static void aspeed_2700_intc0_write(void *opaque, hwadd=
r offset, uint64_t data,
case R_INTC0_GICINT136_STATUS:
aspeed_2700_intc_status_handler(s, addr, data);
break;
+ case R_INTC0_GICINT192_201_STATUS:
+ aspeed_2700_intc_status_handler_multi_outpins(s, addr, data);
+ break;
default:
s->regs[addr] =3D data;
break;
@@ -441,8 +550,8 @@ static void aspeed_2700_intc0_class_init(ObjectClass *k=
lass, void *data)
=20
dc->desc =3D "ASPEED 2700 INTC 0 Controller";
aic->num_lines =3D 32;
- aic->num_inpins =3D 9;
- aic->num_outpins =3D 9;
+ aic->num_inpins =3D 10;
+ aic->num_outpins =3D 19;
aic->reg_ops =3D &aspeed_2700_intc0_ops;
aic->mem_size =3D 0x4000;
aic->reg_size =3D 0x2000;
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index af9703e1b5..bcea3bf1d3 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -92,6 +92,7 @@ aspeed_intc_enable(uint32_t value) "Enable: 0x%x"
aspeed_intc_select(uint32_t value) "Select: 0x%x"
aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x"
aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x"
+aspeed_intc_all_isr_done_bit(int inpin_idx, int bit) "All source ISR execu=
tion are done from specific bit: %d-%d"
=20
# arm_gic.c
gic_enable_irq(int irq) "irq %d enabled"
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 73261037ea..9280dc49d0 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,8 +17,8 @@
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
=20
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
-#define ASPEED_INTC_MAX_INPINS 9
-#define ASPEED_INTC_MAX_OUTPINS 9
+#define ASPEED_INTC_MAX_INPINS 10
+#define ASPEED_INTC_MAX_OUTPINS 19
=20
typedef struct AspeedINTCIRQ {
int inpin_idx;
--=20
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
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Subject: [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better
debugging
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Currently, it is difficult to recognize whether these trace events are from
INTC0 or INTC1. To make these trace events more readable, add an ID to the
INTC trace events.
Updated trace events to include the "id" field for better identification.
Updated the "AspeedINTCClass" structure to include an "id" field.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 45 ++++++++++++++++++++---------------
hw/intc/trace-events | 26 ++++++++++----------
include/hw/intc/aspeed_intc.h | 1 +
3 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 2f704d6cd2..c3b51cec6d 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -90,13 +90,15 @@ static void aspeed_intc_update(AspeedINTCState *s, int =
inpin_idx,
return;
}
=20
- trace_aspeed_intc_update_irq(inpin_idx, outpin_idx, level);
+ trace_aspeed_intc_update_irq(aic->id, inpin_idx, outpin_idx, level);
qemu_set_irq(s->output_pins[outpin_idx], level);
}
=20
static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
const AspeedINTCIRQ *irq, uint32_t select)
{
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
+
if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
/*
* a. mask is not 0 means in ISR mode
@@ -107,7 +109,7 @@ static void aspeed_intc_set_irq_handler(AspeedINTCState=
*s,
* save source interrupt to pending variable.
*/
s->pending[irq->inpin_idx] |=3D select;
- trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ trace_aspeed_intc_pending_irq(aic->id, irq->inpin_idx,
s->pending[irq->inpin_idx]);
} else {
/*
@@ -115,7 +117,8 @@ static void aspeed_intc_set_irq_handler(AspeedINTCState=
*s,
* by setting status register
*/
s->regs[irq->status_addr] =3D select;
- trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ trace_aspeed_intc_trigger_irq(aic->id, irq->inpin_idx,
+ irq->outpin_idx,
s->regs[irq->status_addr]);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
}
@@ -124,6 +127,7 @@ static void aspeed_intc_set_irq_handler(AspeedINTCState=
*s,
static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
const AspeedINTCIRQ *irq, uint32_t se=
lect)
{
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
int i;
=20
for (i =3D 0; i < irq->num_outpins; i++) {
@@ -139,7 +143,7 @@ static void aspeed_intc_set_irq_handler_multi_outpins(A=
speedINTCState *s,
* save source interrupt to pending bit.
*/
s->pending[irq->inpin_idx] |=3D BIT(i);
- trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ trace_aspeed_intc_pending_irq(aic->id, irq->inpin_idx,
s->pending[irq->inpin_idx]);
} else {
/*
@@ -147,7 +151,7 @@ static void aspeed_intc_set_irq_handler_multi_outpins(A=
speedINTCState *s,
* by setting status bit
*/
s->regs[irq->status_addr] |=3D BIT(i);
- trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ trace_aspeed_intc_trigger_irq(aic->id, irq->inpin_idx,
irq->outpin_idx + i,
s->regs[irq->status_addr]);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i,=
1);
@@ -180,7 +184,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq_i=
dx, int level)
=20
irq =3D &aic->irq_table[irq_idx];
=20
- trace_aspeed_intc_set_irq(irq->inpin_idx, level);
+ trace_aspeed_intc_set_irq(aic->id, irq->inpin_idx, level);
enable =3D s->enable[irq->inpin_idx];
=20
if (!level) {
@@ -199,7 +203,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq_i=
dx, int level)
return;
}
=20
- trace_aspeed_intc_select(select);
+ trace_aspeed_intc_select(aic->id, select);
=20
if (irq->num_outpins > 1) {
aspeed_intc_set_irq_handler_multi_outpins(s, irq, select);
@@ -242,7 +246,7 @@ static void aspeed_2700_intc_enable_handler(AspeedINTCS=
tate *s, uint32_t addr,
=20
/* enable new source interrupt */
if (old_enable !=3D s->enable[irq->inpin_idx]) {
- trace_aspeed_intc_enable(s->enable[irq->inpin_idx]);
+ trace_aspeed_intc_enable(aic->id, s->enable[irq->inpin_idx]);
s->regs[addr] =3D data;
return;
}
@@ -251,10 +255,10 @@ static void aspeed_2700_intc_enable_handler(AspeedINT=
CState *s, uint32_t addr,
change =3D s->regs[addr] ^ data;
if (change & data) {
s->mask[irq->inpin_idx] &=3D ~change;
- trace_aspeed_intc_unmask(change, s->mask[irq->inpin_idx]);
+ trace_aspeed_intc_unmask(aic->id, change, s->mask[irq->inpin_idx]);
} else {
s->mask[irq->inpin_idx] |=3D change;
- trace_aspeed_intc_mask(change, s->mask[irq->inpin_idx]);
+ trace_aspeed_intc_mask(aic->id, change, s->mask[irq->inpin_idx]);
}
s->regs[addr] =3D data;
}
@@ -294,7 +298,7 @@ static void aspeed_2700_intc_status_handler(AspeedINTCS=
tate *s, uint32_t addr,
=20
/* All source ISR execution are done */
if (!s->regs[addr]) {
- trace_aspeed_intc_all_isr_done(irq->inpin_idx);
+ trace_aspeed_intc_all_isr_done(aic->id, irq->inpin_idx);
if (s->pending[irq->inpin_idx]) {
/*
* handle pending source interrupt
@@ -303,12 +307,13 @@ static void aspeed_2700_intc_status_handler(AspeedINT=
CState *s, uint32_t addr,
*/
s->regs[addr] =3D s->pending[irq->inpin_idx];
s->pending[irq->inpin_idx] =3D 0;
- trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
- s->regs[addr]);
+ trace_aspeed_intc_trigger_irq(aic->id, irq->inpin_idx,
+ irq->outpin_idx, s->regs[addr]);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
} else {
/* clear irq */
- trace_aspeed_intc_clear_irq(irq->inpin_idx, irq->outpin_idx, 0=
);
+ trace_aspeed_intc_clear_irq(aic->id, irq->inpin_idx,
+ irq->outpin_idx, 0);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 0);
}
}
@@ -351,7 +356,7 @@ static void aspeed_2700_intc_status_handler_multi_outpi=
ns(AspeedINTCState *s,
for (i =3D 0; i < irq->num_outpins; i++) {
/* All source ISR executions are done from a specific bit */
if (data & BIT(i)) {
- trace_aspeed_intc_all_isr_done_bit(irq->inpin_idx, i);
+ trace_aspeed_intc_all_isr_done_bit(aic->id, irq->inpin_idx, i);
if (s->pending[irq->inpin_idx] & BIT(i)) {
/*
* Handle pending source interrupt.
@@ -360,14 +365,15 @@ static void aspeed_2700_intc_status_handler_multi_out=
pins(AspeedINTCState *s,
*/
s->regs[addr] |=3D BIT(i);
s->pending[irq->inpin_idx] &=3D ~BIT(i);
- trace_aspeed_intc_trigger_irq(irq->inpin_idx,
+ trace_aspeed_intc_trigger_irq(aic->id,
+ irq->inpin_idx,
irq->outpin_idx + i,
s->regs[addr]);
aspeed_intc_update(s, irq->inpin_idx,
irq->outpin_idx + i, 1);
} else {
/* clear irq for the specific bit */
- trace_aspeed_intc_clear_irq(irq->inpin_idx,
+ trace_aspeed_intc_clear_irq(aic->id, irq->inpin_idx,
irq->outpin_idx + i, 0);
aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx + i,=
0);
}
@@ -391,7 +397,7 @@ static uint64_t aspeed_2700_intc0_read(void *opaque, hw=
addr offset,
}
=20
value =3D s->regs[addr];
- trace_aspeed_intc_read(offset, size, value);
+ trace_aspeed_intc_read(aic->id, offset, size, value);
=20
return value;
}
@@ -410,7 +416,7 @@ static void aspeed_2700_intc0_write(void *opaque, hwadd=
r offset, uint64_t data,
return;
}
=20
- trace_aspeed_intc_write(offset, size, data);
+ trace_aspeed_intc_write(aic->id, offset, size, data);
=20
switch (addr) {
case R_INTC0_GICINT128_EN:
@@ -557,6 +563,7 @@ static void aspeed_2700_intc0_class_init(ObjectClass *k=
lass, void *data)
aic->reg_size =3D 0x2000;
aic->irq_table =3D aspeed_2700_intc0_irqs;
aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intc0_irqs);
+ aic->id =3D 0;
}
=20
static const TypeInfo aspeed_2700_intc0_info =3D {
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index bcea3bf1d3..a320b542d3 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -80,19 +80,19 @@ aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%"=
PRIx64 " of size %u: 0x%" PRIx32
aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" P=
RIx64 " of size %u: 0x%" PRIx32
# aspeed_intc.c
-aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%=
" PRIx64 " of size %u: 0x%" PRIx32
-aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" =
PRIx64 " of size %u: 0x%" PRIx32
-aspeed_intc_set_irq(int inpin_idx, int level) "Set IRQ %d: %d"
-aspeed_intc_clear_irq(int inpin_idx, int outpin_idx, int level) "Clear IRQ=
%d-%d: %d"
-aspeed_intc_update_irq(int inpin_idx, int outpin_idx, int level) "Update I=
RQ: %d-%d: %d"
-aspeed_intc_pending_irq(int inpin_idx, uint32_t value) "Pending IRQ: %d: 0=
x%x"
-aspeed_intc_trigger_irq(int inpin_idx, int outpin_idx, uint32_t value) "Tr=
igger IRQ: %d-%d: 0x%x"
-aspeed_intc_all_isr_done(int inpin_idx) "All source ISR execution are done=
: %d"
-aspeed_intc_enable(uint32_t value) "Enable: 0x%x"
-aspeed_intc_select(uint32_t value) "Select: 0x%x"
-aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x"
-aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x"
-aspeed_intc_all_isr_done_bit(int inpin_idx, int bit) "All source ISR execu=
tion are done from specific bit: %d-%d"
+aspeed_intc_read(int id, uint64_t offset, unsigned size, uint32_t value) "=
%d: From 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_intc_write(int id, uint64_t offset, unsigned size, uint32_t data) "=
%d: To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_intc_set_irq(int id, int inpin_idx, int level) "%d: Set IRQ %d: %d"
+aspeed_intc_clear_irq(int id, int inpin_idx, int outpin_idx, int level) "%=
d: Clear IRQ %d-%d: %d"
+aspeed_intc_update_irq(int id, int inpin_idx, int outpin_idx, int level) "=
%d: Update IRQ: %d-%d: %d"
+aspeed_intc_pending_irq(int id, int inpin_idx, uint32_t value) "%d: Pendin=
g IRQ: %d: 0x%x"
+aspeed_intc_trigger_irq(int id, int inpin_idx, int outpin_idx, uint32_t va=
lue) "%d: Trigger IRQ: %d-%d: 0x%x"
+aspeed_intc_all_isr_done(int id, int inpin_idx) "%d: All source ISR execut=
ion are done: %d"
+aspeed_intc_enable(int id, uint32_t value) "%d: Enable: 0x%x"
+aspeed_intc_select(int id, uint32_t value) "%d: Select: 0x%x"
+aspeed_intc_mask(int id, uint32_t change, uint32_t value) "%d: Mask: 0x%x:=
0x%x"
+aspeed_intc_unmask(int id, uint32_t change, uint32_t value) "%d: UnMask: 0=
x%x: 0x%x"
+aspeed_intc_all_isr_done_bit(int id, int inpin_idx, int bit) "%d: All sour=
ce ISR execution are done from specific bit: %d-%d"
=20
# arm_gic.c
gic_enable_irq(int irq) "irq %d enabled"
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 9280dc49d0..c2e3906d99 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -56,6 +56,7 @@ struct AspeedINTCClass {
uint64_t reg_size;
const AspeedINTCIRQ *irq_table;
int irq_table_count;
+ int id;
};
=20
#endif /* ASPEED_INTC_H */
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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"open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1
Controller
Date: Tue, 21 Jan 2025 15:04:16 +0800
Message-ID: <20250121070424.2465942-11-jamin_lin@aspeedtech.com>
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Introduce a new ast2700 INTC1 class to support AST2700 INTC1.
Added new register definitions for INTC1, including enable and status regis=
ters
for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTC1, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_2700_intc1_read" and "aspeed_2700_intc1_write" to handle
INTC1-specific register access.
+--------------------------+
| INTC1 |
| |
orgates[0]+----> |inpin[0]+------->outpin[0]|
orgates[1]|----> |inpin[1]|------->outpin[1]|
orgates[2]|----> |inpin[2]|------->outpin[2]|
orgates[3]|----> |inpin[3]|------->outpin[3]|
orgates[4]|----> |inpin[4]|------->outpin[4]|
orgates[5]+----> |inpin[5]+------->outpin[5]|
| |
+--------------------------+
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 119 ++++++++++++++++++++++++++++++++++
include/hw/intc/aspeed_intc.h | 1 +
2 files changed, 120 insertions(+)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index c3b51cec6d..1db5e5a94d 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -36,6 +36,20 @@ REG32(INTC0_GICINT136_STATUS, 0x1804)
REG32(INTC0_GICINT192_201_EN, 0x1B00)
REG32(INTC0_GICINT192_201_STATUS, 0x1B04)
=20
+/* AST2700 INTC1 Registers */
+REG32(INTC1_GICINT192_EN, 0x100)
+REG32(INTC1_GICINT192_STATUS, 0x104)
+REG32(INTC1_GICINT193_EN, 0x110)
+REG32(INTC1_GICINT193_STATUS, 0x114)
+REG32(INTC1_GICINT194_EN, 0x120)
+REG32(INTC1_GICINT194_STATUS, 0x124)
+REG32(INTC1_GICINT195_EN, 0x130)
+REG32(INTC1_GICINT195_STATUS, 0x134)
+REG32(INTC1_GICINT196_EN, 0x140)
+REG32(INTC1_GICINT196_STATUS, 0x144)
+REG32(INTC1_GICINT197_EN, 0x150)
+REG32(INTC1_GICINT197_STATUS, 0x154)
+
static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_MAX_INPINS] =3D {
{0, 0, 10, R_INTC0_GICINT192_201_EN, R_INTC0_GICINT192_201_STATUS},
{1, 10, 1, R_INTC0_GICINT128_EN, R_INTC0_GICINT128_STATUS},
@@ -49,6 +63,15 @@ static AspeedINTCIRQ aspeed_2700_intc0_irqs[ASPEED_INTC_=
MAX_INPINS] =3D {
{9, 18, 1, R_INTC0_GICINT136_EN, R_INTC0_GICINT136_STATUS},
};
=20
+static AspeedINTCIRQ aspeed_2700_intc1_irqs[ASPEED_INTC_MAX_INPINS] =3D {
+ {0, 0, 1, R_INTC1_GICINT192_EN, R_INTC1_GICINT192_STATUS},
+ {1, 1, 1, R_INTC1_GICINT193_EN, R_INTC1_GICINT193_STATUS},
+ {2, 2, 1, R_INTC1_GICINT194_EN, R_INTC1_GICINT194_STATUS},
+ {3, 3, 1, R_INTC1_GICINT195_EN, R_INTC1_GICINT195_STATUS},
+ {4, 4, 1, R_INTC1_GICINT196_EN, R_INTC1_GICINT196_STATUS},
+ {5, 5, 1, R_INTC1_GICINT197_EN, R_INTC1_GICINT197_STATUS},
+};
+
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
uint32_t addr)
{
@@ -453,6 +476,68 @@ static void aspeed_2700_intc0_write(void *opaque, hwad=
dr offset, uint64_t data,
return;
}
=20
+static uint64_t aspeed_2700_intc1_read(void *opaque, hwaddr offset,
+ unsigned int size)
+{
+ AspeedINTCState *s =3D ASPEED_INTC(opaque);
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
+ uint32_t addr =3D offset >> 2;
+ uint32_t value =3D 0;
+
+ if (offset >=3D aic->reg_size) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "=
\n",
+ __func__, offset);
+ return 0;
+ }
+
+ value =3D s->regs[addr];
+ trace_aspeed_intc_read(aic->id, offset, size, value);
+
+ return value;
+}
+
+static void aspeed_2700_intc1_write(void *opaque, hwaddr offset, uint64_t =
data,
+ unsigned size)
+{
+ AspeedINTCState *s =3D ASPEED_INTC(opaque);
+ AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
+ uint32_t addr =3D offset >> 2;
+
+ if (offset >=3D aic->reg_size) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx =
"\n",
+ __func__, offset);
+ return;
+ }
+
+ trace_aspeed_intc_write(aic->id, offset, size, data);
+
+ switch (addr) {
+ case R_INTC1_GICINT192_EN:
+ case R_INTC1_GICINT193_EN:
+ case R_INTC1_GICINT194_EN:
+ case R_INTC1_GICINT195_EN:
+ case R_INTC1_GICINT196_EN:
+ case R_INTC1_GICINT197_EN:
+ aspeed_2700_intc_enable_handler(s, addr, data);
+ break;
+ case R_INTC1_GICINT192_STATUS:
+ case R_INTC1_GICINT193_STATUS:
+ case R_INTC1_GICINT194_STATUS:
+ case R_INTC1_GICINT195_STATUS:
+ case R_INTC1_GICINT196_STATUS:
+ case R_INTC1_GICINT197_STATUS:
+ aspeed_2700_intc_status_handler(s, addr, data);
+ break;
+ default:
+ s->regs[addr] =3D data;
+ break;
+ }
+
+ return;
+}
+
static const MemoryRegionOps aspeed_intc_ops =3D {
.endianness =3D DEVICE_LITTLE_ENDIAN,
.valid =3D {
@@ -572,10 +657,44 @@ static const TypeInfo aspeed_2700_intc0_info =3D {
.class_init =3D aspeed_2700_intc0_class_init,
};
=20
+static const MemoryRegionOps aspeed_2700_intc1_ops =3D {
+ .read =3D aspeed_2700_intc1_read,
+ .write =3D aspeed_2700_intc1_write,
+ .endianness =3D DEVICE_LITTLE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ }
+};
+
+static void aspeed_2700_intc1_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass);
+
+ dc->desc =3D "ASPEED 2700 INTC 1 Controller";
+ aic->num_lines =3D 32;
+ aic->num_inpins =3D 6;
+ aic->num_outpins =3D 6;
+ aic->mem_size =3D 0x400;
+ aic->reg_size =3D 0x3d8;
+ aic->reg_ops =3D &aspeed_2700_intc1_ops;
+ aic->irq_table =3D aspeed_2700_intc1_irqs;
+ aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intc1_irqs);
+ aic->id =3D 1;
+}
+
+static const TypeInfo aspeed_2700_intc1_info =3D {
+ .name =3D TYPE_ASPEED_2700_INTC1,
+ .parent =3D TYPE_ASPEED_INTC,
+ .class_init =3D aspeed_2700_intc1_class_init,
+};
+
static void aspeed_intc_register_types(void)
{
type_register_static(&aspeed_intc_info);
type_register_static(&aspeed_2700_intc0_info);
+ type_register_static(&aspeed_2700_intc1_info);
}
=20
type_init(aspeed_intc_register_types);
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index c2e3906d99..7f500927a1 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -14,6 +14,7 @@
=20
#define TYPE_ASPEED_INTC "aspeed.intc"
#define TYPE_ASPEED_2700_INTC0 TYPE_ASPEED_INTC "0" "-ast2700"
+#define TYPE_ASPEED_2700_INTC1 TYPE_ASPEED_INTC "1" "-ast2700"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
=20
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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"open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750
A1 Silicon Revisions
Date: Tue, 21 Jan 2025 15:04:17 +0800
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Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV=
to
identify the A1 silicon revisions.
Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the SCU
registers.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 3 +++
include/hw/misc/aspeed_scu.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index bac1441b06..f049a9fd96 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -559,6 +559,8 @@ static uint32_t aspeed_silicon_revs[] =3D {
AST2700_A0_SILICON_REV,
AST2720_A0_SILICON_REV,
AST2750_A0_SILICON_REV,
+ AST2700_A1_SILICON_REV,
+ AST2750_A1_SILICON_REV,
};
=20
bool is_supported_silicon_rev(uint32_t silicon_rev)
@@ -938,6 +940,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(dev);
=20
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
+ s->regs[AST2700_SILICON_REV] =3D s->silicon_rev;
}
=20
static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 356be95e45..684b48b722 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -54,6 +54,8 @@ struct AspeedSCUState {
#define AST2700_A0_SILICON_REV 0x06000103U
#define AST2720_A0_SILICON_REV 0x06000203U
#define AST2750_A0_SILICON_REV 0x06000003U
+#define AST2700_A1_SILICON_REV 0x06010103U
+#define AST2750_A1_SILICON_REV 0x06010003U
=20
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) =3D=3D 0x=
04)
=20
--=20
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC
controllers for AST2700 A1
Date: Tue, 21 Jan 2025 15:04:18 +0800
Message-ID: <20250121070424.2465942-13-jamin_lin@aspeedtech.com>
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The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt num=
bers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged ev=
ery
32 sources for interrupt numbers greater than 127.
There are two levels of interrupt controllers, INTC0 and INTC1. The interru=
pt
sources of INTC0 are the interrupt numbers from INTC_0 to INTC_127 and
interrupts from INTC1. The interrupt sources of INTC1 are the interrupt num=
bers
greater than INTC_127. INTC1 controls the interrupts INTC_128 to INTC_319 o=
nly.
Currently, only GIC 192 to 201 are supported, and their source interrupts a=
re
from INTC1 and connected to INTC0 at input pin 0 and output pins 0 to 9 for
GIC 192-201.
To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC0.
These will be removed if we decide not to support AST2700 A0 in the future.
+--------------------------------------------------------------------------=
-------------+
| AST2700 A1 Design =
|
| =
|
| +--------------------------+ =
|
| | INTC1 | +---------------+=
|
| | | | orgates[0] |=
|
| orgates[0]+----> |inpin[0]+------->outpin[0]+------> | 0 |=
|
| orgates[1]|----> |inpin[1]|------->outpin[1]|------> | 1 0-31 bits +=
--+ |
| orgates[2]|----> |inpin[2]|------->outpin[2]|------> | 2 |=
| |
| orgates[3]|----> |inpin[3]|------->outpin[3]|------> | 3 |=
| |
| orgates[4]|----> |inpin[4]|------->outpin[4]|------> | 4 |=
| |
| orgates[5]+----> |inpin[5]+------->outpin[5]+------> | 5 |=
| |
| | | |---------------|=
| |
| +--------------------------+ =
| |
| +---------------------------------------------------------------------=
--| |
| | =
|
| | =
|
| | +------------------------------+ +---------=
--------+ |
| | | INTC0 | | GIC =
| |
| | |inpin[0:0]--------->outpin[0] +---------> |192 =
| |
| | |inpin[0:1]|-------->outpin[1] |---------> |193 =
| |
| | |inpin[0:2]|-------->outpin[2] |---------> |194 =
| |
| | |inpin[0:3]|-------->outpin[3] |---------> |195 =
| |
| >--------------> |inpin[0:4]|-------->outpin[4] |---------> |196 =
| |
| |inpin[0:5]|-------->outpin[5] |---------> |197 =
| |
| |inpin[0:6]|-------->outpin[6] |---------> |198 =
| |
| |inpin[0:7]|-------->outpin[7] |---------> |199 =
| |
| |inpin[0:8]|-------->outpin[8] |---------> |200 =
| |
| |inpin[0:9]|-------->outpin[9] |---------> |201 =
| |
+--------------------------------------------------------------------------=
-------------+
+--------------------------------------------------------------------------=
-------------+
| orgates[1]|-----> |inpin[1]|---------->outpin[10]|---------> |128 =
| |
| orgates[2]|-----> |inpin[2]|---------->outpin[11]|---------> |129 =
| |
| orgates[3]|-----> |inpin[3]|---------->outpin[12]|---------> |130 =
| |
| orgates[4]|-----> |inpin[4]|---------->outpin[13]|---------> |131 =
| |
| orgates[5]|-----> |inpin[5]|---------->outpin[14]|---------> |132 =
| |
| orgates[6]|-----> |inpin[6]|---------->outpin[15]|---------> |133 =
| |
| orgates[7]|-----> |inpin[7]|---------->outpin[16]|---------> |134 =
| |
| orgates[8]|-----> |inpin[8]|---------->outpin[17]|---------> |135 =
| |
| orgates[9]+-----> |inpin[9]|---------->outpin[18]+---------> |136 =
| |
| +------------------------------+ +---------=
--------+ |
| =
|
| AST2700 A0 Design =
|
| =
|
+--------------------------------------------------------------------------=
-------------+
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 126 +++++++++++++++++++++++++-----------
include/hw/arm/aspeed_soc.h | 3 +-
2 files changed, 92 insertions(+), 37 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d5e521cd38..a95fed30cf 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -67,6 +67,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D {
[ASPEED_DEV_RTC] =3D 0x12C0F000,
[ASPEED_DEV_SDHCI] =3D 0x14080000,
[ASPEED_DEV_TIMER1] =3D 0x12C10000,
+ [ASPEED_DEV_INTC1] =3D 0x14C18000,
};
=20
#define AST2700_MAX_IRQ 256
@@ -119,21 +120,27 @@ static const int aspeed_soc_ast2700_irqmap[] =3D {
};
=20
/* GICINT 128 */
-static const int aspeed_soc_ast2700_gic128_intcmap[] =3D {
+/* GICINT 192 */
+static const int ast2700_gic128_gic192_intcmap[] =3D {
[ASPEED_DEV_LPC] =3D 0,
[ASPEED_DEV_IBT] =3D 2,
[ASPEED_DEV_KCS] =3D 4,
};
=20
+/* GICINT 129 */
+/* GICINT 193 */
+
/* GICINT 130 */
-static const int aspeed_soc_ast2700_gic130_intcmap[] =3D {
+/* GICINT 194 */
+static const int ast2700_gic130_gic194_intcmap[] =3D {
[ASPEED_DEV_I2C] =3D 0,
[ASPEED_DEV_ADC] =3D 16,
[ASPEED_DEV_GPIO] =3D 18,
};
=20
/* GICINT 131 */
-static const int aspeed_soc_ast2700_gic131_intcmap[] =3D {
+/* GICINT 195 */
+static const int ast2700_gic131_gic195_intcmap[] =3D {
[ASPEED_DEV_I3C] =3D 0,
[ASPEED_DEV_WDT] =3D 16,
[ASPEED_DEV_FMC] =3D 25,
@@ -141,7 +148,8 @@ static const int aspeed_soc_ast2700_gic131_intcmap[] =
=3D {
};
=20
/* GICINT 132 */
-static const int aspeed_soc_ast2700_gic132_intcmap[] =3D {
+/* GICINT 196 */
+static const int ast2700_gic132_gic196_intcmap[] =3D {
[ASPEED_DEV_ETH1] =3D 0,
[ASPEED_DEV_ETH2] =3D 1,
[ASPEED_DEV_ETH3] =3D 2,
@@ -160,40 +168,58 @@ static const int aspeed_soc_ast2700_gic132_intcmap[] =
=3D {
};
=20
/* GICINT 133 */
-static const int aspeed_soc_ast2700_gic133_intcmap[] =3D {
+/* GICINT 197 */
+static const int ast2700_gic133_gic197_intcmap[] =3D {
[ASPEED_DEV_SDHCI] =3D 1,
[ASPEED_DEV_PECI] =3D 4,
};
=20
/* GICINT 128 ~ 136 */
+/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
int irq;
+ int intc_idx;
+ int orgate_idx;
const int *ptr;
};
=20
-static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] =3D=
{
- {128, aspeed_soc_ast2700_gic128_intcmap},
- {129, NULL},
- {130, aspeed_soc_ast2700_gic130_intcmap},
- {131, aspeed_soc_ast2700_gic131_intcmap},
- {132, aspeed_soc_ast2700_gic132_intcmap},
- {133, aspeed_soc_ast2700_gic133_intcmap},
- {134, NULL},
- {135, NULL},
- {136, NULL},
+static struct gic_intc_irq_info ast2700_gic_intcmap[] =3D {
+ {192, 1, 0, ast2700_gic128_gic192_intcmap},
+ {193, 1, 1, NULL},
+ {194, 1, 2, ast2700_gic130_gic194_intcmap},
+ {195, 1, 3, ast2700_gic131_gic195_intcmap},
+ {196, 1, 4, ast2700_gic132_gic196_intcmap},
+ {197, 1, 5, ast2700_gic133_gic197_intcmap},
+ {198, 1, 6, NULL},
+ {199, 1, 7, NULL},
+ {200, 1, 8, NULL},
+ {201, 1, 9, NULL},
+ {128, 0, 1, ast2700_gic128_gic192_intcmap},
+ {129, 0, 2, NULL},
+ {130, 0, 3, ast2700_gic130_gic194_intcmap},
+ {131, 0, 4, ast2700_gic131_gic195_intcmap},
+ {132, 0, 5, ast2700_gic132_gic196_intcmap},
+ {133, 0, 6, ast2700_gic133_gic197_intcmap},
+ {134, 0, 7, NULL},
+ {135, 0, 8, NULL},
+ {136, 0, 9, NULL},
};
=20
static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
{
Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(s);
AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
=20
- for (i =3D 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] =3D=3D aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
+ for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
+ or_idx =3D ast2700_gic_intcmap[i].orgate_idx;
+ idx =3D ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_gic_intcmap[i].ptr[dev]);
}
}
=20
@@ -205,13 +231,17 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspe=
edSoCState *s, int dev,
{
Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(s);
AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
=20
- for (i =3D 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
- if (sc->irqmap[dev] =3D=3D aspeed_soc_ast2700_gic_intcmap[i].irq) {
- assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
+ for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) {
+ assert(ast2700_gic_intcmap[i].ptr);
+ or_idx =3D ast2700_gic_intcmap[i].orgate_idx;
+ idx =3D ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_gic_intcmap[i].ptr[dev] + inde=
x);
}
}
=20
@@ -372,7 +402,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
=20
object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLII=
O);
- object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC0);
+ object_initialize_child(obj, "intc0", &a->intc[0], TYPE_ASPEED_2700_IN=
TC0);
+ object_initialize_child(obj, "intc1", &a->intc[1], TYPE_ASPEED_2700_IN=
TC1);
=20
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -481,7 +512,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev=
, Error **errp)
Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev);
AspeedSoCState *s =3D ASPEED_SOC(dev);
AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);
- AspeedINTCClass *ic =3D ASPEED_INTC_GET_CLASS(&a->intc);
g_autofree char *sram_name =3D NULL;
qemu_irq irq;
=20
@@ -511,21 +541,45 @@ static void aspeed_soc_ast2700_realize(DeviceState *d=
ev, Error **errp)
return;
}
=20
- /* INTC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) {
+ /* INTC0 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
=20
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC0]);
=20
- /* GICINT orgates -> INTC -> GIC */
- for (i =3D 0; i < ic->num_inpins; i++) {
- qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
- qdev_get_gpio_in(DEVICE(&a->intc), i));
- sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
+ /* INTC1 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ sc->memmap[ASPEED_DEV_INTC1]);
+
+ /* irq source orgates -> INTC0 */
+ for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++)=
{
+ qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
+ }
+ /* INTC0 -> GIC192 - GIC201 */
+ /* INTC0 -> GIC128 - GIC136 */
+ for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++=
) {
+ assert(i < ARRAY_SIZE(ast2700_gic_intcmap));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
qdev_get_gpio_in(DEVICE(&a->gic),
- aspeed_soc_ast2700_gic_intcmap[i].irq));
+ ast2700_gic_intcmap[i].irq));
+ }
+
+ /* irq source orgates -> INTC1 */
+ for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++)=
{
+ qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
+ }
+ /* INTC1 -> INTC0 */
+ for (i =3D 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++=
) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
+ qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i=
));
}
=20
/* SRAM */
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 51e585e3e4..c079225775 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -128,7 +128,7 @@ struct Aspeed27x0SoCState {
AspeedSoCState parent;
=20
ARMCPU cpu[ASPEED_CPUS_NUM];
- AspeedINTCState intc;
+ AspeedINTCState intc[2];
GICv3State gic;
MemoryRegion dram_empty;
};
@@ -195,6 +195,7 @@ enum {
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
ASPEED_DEV_INTC0,
+ ASPEED_DEV_INTC1,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
--=20
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for
AST2700 A0
Date: Tue, 21 Jan 2025 15:04:19 +0800
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Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its =
IRQ
table and machine name.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 8 ++++----
hw/arm/aspeed_ast27x0.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index ae0405c654..402d55c556 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1654,12 +1654,12 @@ static void ast2700_evb_i2c_init(AspeedMachineState=
*bmc)
TYPE_TMP105, 0x4d);
}
=20
-static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *d=
ata)
+static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, void =
*data)
{
MachineClass *mc =3D MACHINE_CLASS(oc);
AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc);
=20
- mc->desc =3D "Aspeed AST2700 EVB (Cortex-A35)";
+ mc->desc =3D "Aspeed AST2700 A0 EVB (Cortex-A35)";
amc->soc_name =3D "ast2700-a0";
amc->hw_strap1 =3D AST2700_EVB_HW_STRAP1;
amc->hw_strap2 =3D AST2700_EVB_HW_STRAP2;
@@ -1795,9 +1795,9 @@ static const TypeInfo aspeed_machine_types[] =3D {
.class_init =3D aspeed_minibmc_machine_ast1030_evb_class_init,
#ifdef TARGET_AARCH64
}, {
- .name =3D MACHINE_TYPE_NAME("ast2700-evb"),
+ .name =3D MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent =3D TYPE_ASPEED_MACHINE,
- .class_init =3D aspeed_machine_ast2700_evb_class_init,
+ .class_init =3D aspeed_machine_ast2700a0_evb_class_init,
#endif
}, {
.name =3D TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index a95fed30cf..b32c4fcc35 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -73,7 +73,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D {
#define AST2700_MAX_IRQ 256
=20
/* Shared Peripheral Interrupt values below are offset by -32 from datashe=
et */
-static const int aspeed_soc_ast2700_irqmap[] =3D {
+static const int aspeed_soc_ast2700a0_irqmap[] =3D {
[ASPEED_DEV_UART0] =3D 132,
[ASPEED_DEV_UART1] =3D 132,
[ASPEED_DEV_UART2] =3D 132,
@@ -794,7 +794,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev=
, Error **errp)
create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
}
=20
-static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
+static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
{
static const char * const valid_cpu_types[] =3D {
ARM_CPU_TYPE_NAME("cortex-a35"),
@@ -817,7 +817,7 @@ static void aspeed_soc_ast2700_class_init(ObjectClass *=
oc, void *data)
sc->uarts_num =3D 13;
sc->num_cpus =3D 4;
sc->uarts_base =3D ASPEED_DEV_UART0;
- sc->irqmap =3D aspeed_soc_ast2700_irqmap;
+ sc->irqmap =3D aspeed_soc_ast2700a0_irqmap;
sc->memmap =3D aspeed_soc_ast2700_memmap;
sc->get_irq =3D aspeed_soc_ast2700_get_irq;
}
@@ -832,7 +832,7 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D {
.name =3D "ast2700-a0",
.parent =3D TYPE_ASPEED27X0_SOC,
.instance_init =3D aspeed_soc_ast2700_init,
- .class_init =3D aspeed_soc_ast2700_class_init,
+ .class_init =3D aspeed_soc_ast2700a0_class_init,
},
};
=20
--=20
2.34.1
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for
AST2700 A1
Date: Tue, 21 Jan 2025 15:04:20 +0800
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The memory map for AST2700 A1 remains compatible with AST2700 A0.
However, the IRQ mapping has been updated for AST2700 A1, with GIC interrup=
ts
now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1.
Introduce "aspeed_machine_ast2700_evb_class_init" to initialize the AST2700=
EVB
machine. Add "aspeed_soc_ast2700_class_init" to initialize the AST2700 A1 S=
oC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 24 +++++++++++++
hw/arm/aspeed_ast27x0.c | 80 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 104 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 402d55c556..254fa5316d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1672,6 +1672,26 @@ static void aspeed_machine_ast2700a0_evb_class_init(=
ObjectClass *oc, void *data)
mc->default_ram_size =3D 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
+
+static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *d=
ata)
+{
+ MachineClass *mc =3D MACHINE_CLASS(oc);
+ AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc =3D "Aspeed AST2700 EVB (Cortex-A35)";
+ amc->soc_name =3D "ast2700-a1";
+ amc->hw_strap1 =3D AST2700_EVB_HW_STRAP1;
+ amc->hw_strap2 =3D AST2700_EVB_HW_STRAP2;
+ amc->fmc_model =3D "w25q01jvq";
+ amc->spi_model =3D "w25q512jv";
+ amc->num_cs =3D 2;
+ amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
+ amc->uart_default =3D ASPEED_DEV_UART12;
+ amc->i2c_init =3D ast2700_evb_i2c_init;
+ mc->default_ram_size =3D 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
#endif
=20
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
@@ -1798,6 +1818,10 @@ static const TypeInfo aspeed_machine_types[] =3D {
.name =3D MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent =3D TYPE_ASPEED_MACHINE,
.class_init =3D aspeed_machine_ast2700a0_evb_class_init,
+ }, {
+ .name =3D MACHINE_TYPE_NAME("ast2700-evb"),
+ .parent =3D TYPE_ASPEED_MACHINE,
+ .class_init =3D aspeed_machine_ast2700_evb_class_init,
#endif
}, {
.name =3D TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index b32c4fcc35..e0a29c9053 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -119,6 +119,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D {
[ASPEED_DEV_SDHCI] =3D 133,
};
=20
+static const int aspeed_soc_ast2700_irqmap[] =3D {
+ [ASPEED_DEV_UART0] =3D 196,
+ [ASPEED_DEV_UART1] =3D 196,
+ [ASPEED_DEV_UART2] =3D 196,
+ [ASPEED_DEV_UART3] =3D 196,
+ [ASPEED_DEV_UART4] =3D 8,
+ [ASPEED_DEV_UART5] =3D 196,
+ [ASPEED_DEV_UART6] =3D 196,
+ [ASPEED_DEV_UART7] =3D 196,
+ [ASPEED_DEV_UART8] =3D 196,
+ [ASPEED_DEV_UART9] =3D 196,
+ [ASPEED_DEV_UART10] =3D 196,
+ [ASPEED_DEV_UART11] =3D 196,
+ [ASPEED_DEV_UART12] =3D 196,
+ [ASPEED_DEV_FMC] =3D 195,
+ [ASPEED_DEV_SDMC] =3D 0,
+ [ASPEED_DEV_SCU] =3D 12,
+ [ASPEED_DEV_ADC] =3D 194,
+ [ASPEED_DEV_XDMA] =3D 5,
+ [ASPEED_DEV_EMMC] =3D 15,
+ [ASPEED_DEV_GPIO] =3D 194,
+ [ASPEED_DEV_RTC] =3D 13,
+ [ASPEED_DEV_TIMER1] =3D 16,
+ [ASPEED_DEV_TIMER2] =3D 17,
+ [ASPEED_DEV_TIMER3] =3D 18,
+ [ASPEED_DEV_TIMER4] =3D 19,
+ [ASPEED_DEV_TIMER5] =3D 20,
+ [ASPEED_DEV_TIMER6] =3D 21,
+ [ASPEED_DEV_TIMER7] =3D 22,
+ [ASPEED_DEV_TIMER8] =3D 23,
+ [ASPEED_DEV_WDT] =3D 195,
+ [ASPEED_DEV_PWM] =3D 195,
+ [ASPEED_DEV_LPC] =3D 192,
+ [ASPEED_DEV_IBT] =3D 192,
+ [ASPEED_DEV_I2C] =3D 194,
+ [ASPEED_DEV_PECI] =3D 197,
+ [ASPEED_DEV_ETH1] =3D 196,
+ [ASPEED_DEV_ETH2] =3D 196,
+ [ASPEED_DEV_ETH3] =3D 196,
+ [ASPEED_DEV_HACE] =3D 4,
+ [ASPEED_DEV_KCS] =3D 192,
+ [ASPEED_DEV_DP] =3D 28,
+ [ASPEED_DEV_I3C] =3D 195,
+ [ASPEED_DEV_SDHCI] =3D 197,
+};
+
/* GICINT 128 */
/* GICINT 192 */
static const int ast2700_gic128_gic192_intcmap[] =3D {
@@ -822,6 +868,34 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClas=
s *oc, void *data)
sc->get_irq =3D aspeed_soc_ast2700_get_irq;
}
=20
+static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
+{
+ static const char * const valid_cpu_types[] =3D {
+ ARM_CPU_TYPE_NAME("cortex-a35"),
+ NULL
+ };
+ DeviceClass *dc =3D DEVICE_CLASS(oc);
+ AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable =3D false;
+ dc->realize =3D aspeed_soc_ast2700_realize;
+
+ sc->name =3D "ast2700-a1";
+ sc->valid_cpu_types =3D valid_cpu_types;
+ sc->silicon_rev =3D AST2700_A1_SILICON_REV;
+ sc->sram_size =3D 0x20000;
+ sc->spis_num =3D 3;
+ sc->wdts_num =3D 8;
+ sc->macs_num =3D 1;
+ sc->uarts_num =3D 13;
+ sc->num_cpus =3D 4;
+ sc->uarts_base =3D ASPEED_DEV_UART0;
+ sc->irqmap =3D aspeed_soc_ast2700_irqmap;
+ sc->memmap =3D aspeed_soc_ast2700_memmap;
+ sc->get_irq =3D aspeed_soc_ast2700_get_irq;
+}
+
static const TypeInfo aspeed_soc_ast27x0_types[] =3D {
{
.name =3D TYPE_ASPEED27X0_SOC,
@@ -834,6 +908,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D {
.instance_init =3D aspeed_soc_ast2700_init,
.class_init =3D aspeed_soc_ast2700a0_class_init,
},
+ {
+ .name =3D "ast2700-a1",
+ .parent =3D TYPE_ASPEED27X0_SOC,
+ .instance_init =3D aspeed_soc_ast2700_init,
+ .class_init =3D aspeed_soc_ast2700_class_init,
+ },
};
=20
DEFINE_TYPES(aspeed_soc_ast27x0_types)
--=20
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style
Date: Tue, 21 Jan 2025 15:04:21 +0800
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Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -75,9 +75,12 @@ static const struct {
{ HASH_ALGO_SHA1, QCRYPTO_HASH_ALGO_SHA1 },
{ HASH_ALGO_SHA224, QCRYPTO_HASH_ALGO_SHA224 },
{ HASH_ALGO_SHA256, QCRYPTO_HASH_ALGO_SHA256 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512, QCRYPTO_HASH_ALGO=
_SHA512 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384, QCRYPTO_HASH_ALGO=
_SHA384 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256, QCRYPTO_HASH_ALGO=
_SHA256 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512,
+ QCRYPTO_HASH_ALGO_SHA512 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384,
+ QCRYPTO_HASH_ALGO_SHA384 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256,
+ QCRYPTO_HASH_ALGO_SHA256 },
};
=20
static int hash_algo_lookup(uint32_t reg)
@@ -201,7 +204,8 @@ static void do_hash_operation(AspeedHACEState *s, int a=
lgo, bool sg_mode,
haddr =3D address_space_map(&s->dram_as, addr, &plen, false,
MEMTXATTRS_UNSPECIFIED);
if (haddr =3D=3D NULL) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __f=
unc__);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: qcrypto failed\n", __func__);
return;
}
iov[i].iov_base =3D haddr;
--=20
2.34.1
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Subject: [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support
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Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
---
hw/misc/aspeed_hace.c | 20 ++++++++++++++++++++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 18b85081c7..86422cb3be 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -552,12 +552,32 @@ static const TypeInfo aspeed_ast1030_hace_info =3D {
.class_init =3D aspeed_ast1030_hace_class_init,
};
=20
+static void aspeed_ast2700_hace_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedHACEClass *ahc =3D ASPEED_HACE_CLASS(klass);
+
+ dc->desc =3D "AST2700 Hash and Crypto Engine";
+
+ ahc->src_mask =3D 0x7FFFFFFF;
+ ahc->dest_mask =3D 0x7FFFFFF8;
+ ahc->key_mask =3D 0x7FFFFFF8;
+ ahc->hash_mask =3D 0x00147FFF;
+}
+
+static const TypeInfo aspeed_ast2700_hace_info =3D {
+ .name =3D TYPE_ASPEED_AST2700_HACE,
+ .parent =3D TYPE_ASPEED_HACE,
+ .class_init =3D aspeed_ast2700_hace_class_init,
+};
+
static void aspeed_hace_register_types(void)
{
type_register_static(&aspeed_ast2400_hace_info);
type_register_static(&aspeed_ast2500_hace_info);
type_register_static(&aspeed_ast2600_hace_info);
type_register_static(&aspeed_ast1030_hace_info);
+ type_register_static(&aspeed_ast2700_hace_info);
type_register_static(&aspeed_hace_info);
}
=20
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h
index 4af9919195..d13fd3da07 100644
--- a/include/hw/misc/aspeed_hace.h
+++ b/include/hw/misc/aspeed_hace.h
@@ -18,6 +18,7 @@
#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"
+#define TYPE_ASPEED_AST2700_HACE TYPE_ASPEED_HACE "-ast2700"
=20
OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
=20
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700
Date: Tue, 21 Jan 2025 15:04:23 +0800
Message-ID: <20250121070424.2465942-18-jamin_lin@aspeedtech.com>
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The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_0000 and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
---
hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index e0a29c9053..0b82b2eab5 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -68,6 +68,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D {
[ASPEED_DEV_SDHCI] =3D 0x14080000,
[ASPEED_DEV_TIMER1] =3D 0x12C10000,
[ASPEED_DEV_INTC1] =3D 0x14C18000,
+ [ASPEED_DEV_HACE] =3D 0x12070000,
};
=20
#define AST2700_MAX_IRQ 256
@@ -478,6 +479,9 @@ static void aspeed_soc_ast2700_init(Object *obj)
=20
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
+ object_initialize_child(obj, "hace", &s->hace, typename);
}
=20
/*
@@ -833,6 +837,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *de=
v, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
=20
+ /* HACE */
+ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ sc->memmap[ASPEED_DEV_HACE]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
--=20
2.34.1
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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the
Crypto Manager Self Test(WORKAROUND)
Date: Tue, 21 Jan 2025 15:04:24 +0800
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Currently, it does not support the CRYPT command.
Instead, it only sends an interrupt to notify the firmware
that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in
the Crypto Manager Self Test.
Full support for the CRYPT command will be implemented in the future.
It only for reviewer testing and please drop this patch.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 86422cb3be..c3ec6179b9 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -58,6 +58,7 @@
#define HASH_HASH_THEN_CRYPT (BIT(0) | BIT(1))
/* Other cmd bits */
#define HASH_IRQ_EN BIT(9)
+#define CRYPT_IRQ_EN BIT(12)
#define HASH_SG_EN BIT(18)
/* Scatter-gather data list */
#define SG_LIST_LEN_SIZE 4
@@ -343,6 +344,13 @@ static void aspeed_hace_write(void *opaque, hwaddr add=
r, uint64_t data,
qemu_irq_lower(s->irq);
}
}
+ if (data & CRYPT_IRQ) {
+ data &=3D ~CRYPT_IRQ;
+
+ if (s->regs[addr] & CRYPT_IRQ) {
+ qemu_irq_lower(s->irq);
+ }
+ }
break;
case R_HASH_SRC:
data &=3D ahc->src_mask;
@@ -388,6 +396,10 @@ static void aspeed_hace_write(void *opaque, hwaddr add=
r, uint64_t data,
case R_CRYPT_CMD:
qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n",
__func__);
+ s->regs[R_STATUS] |=3D CRYPT_IRQ;
+ if (data & CRYPT_IRQ_EN) {
+ qemu_irq_raise(s->irq);
+ }
break;
default:
break;
--=20
2.34.1