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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1737395039573019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 530b75a9a3..3c31dc1047 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1995,9 +1995,9 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDC= ontextEntry *ce, uint32_t pasid) { dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); - uint32_t level =3D vtd_get_iova_level(s, ce, pasid); uint32_t offset; uint64_t flpte, flag_ad =3D VTD_FL_A; + *flpte_level =3D vtd_get_iova_level(s, ce, pasid); =20 if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) { error_report_once("%s: detected non canonical IOVA (iova=3D0x%" PR= Ix64 "," @@ -2006,11 +2006,11 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VT= DContextEntry *ce, } =20 while (true) { - offset =3D vtd_iova_level_offset(iova, level); + offset =3D vtd_iova_level_offset(iova, *flpte_level); flpte =3D vtd_get_pte(addr, offset); =20 if (flpte =3D=3D (uint64_t)-1) { - if (level =3D=3D vtd_get_iova_level(s, ce, pasid)) { + if (*flpte_level =3D=3D vtd_get_iova_level(s, ce, pasid)) { /* Invalid programming of pasid-entry */ return -VTD_FR_PASID_ENTRY_FSPTPTR_INV; } else { @@ -2036,15 +2036,15 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VT= DContextEntry *ce, if (is_write && !(flpte & VTD_FL_RW)) { return -VTD_FR_SM_WRITE; } - if (vtd_flpte_nonzero_rsvd(flpte, level)) { + if (vtd_flpte_nonzero_rsvd(flpte, *flpte_level)) { error_report_once("%s: detected flpte reserved non-zero " "iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 "flpte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", - __func__, iova, level, flpte, pasid); + __func__, iova, *flpte_level, flpte, pasid); return -VTD_FR_FS_PAGING_ENTRY_RSVD; } =20 - if (vtd_is_last_pte(flpte, level) && is_write) { + if (vtd_is_last_pte(flpte, *flpte_level) && is_write) { flag_ad |=3D VTD_FL_D; } =20 @@ -2052,14 +2052,13 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VT= DContextEntry *ce, return -VTD_FR_FS_BIT_UPDATE_FAILED; } =20 - if (vtd_is_last_pte(flpte, level)) { + if (vtd_is_last_pte(flpte, *flpte_level)) { *flptep =3D flpte; - *flpte_level =3D level; return 0; } =20 addr =3D vtd_get_pte_addr(flpte, aw_bits); - level--; + (*flpte_level)--; } } =20 --=20 2.47.1