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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
=?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= <cleger@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 45/50] target/riscv: Implement Smdbltrp sret,
mret and mnret behavior
Date: Sun, 19 Jan 2025 11:12:20 +1000
Message-ID: <20250119011225.11452-46-alistair.francis@wdc.com>
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From: Cl=C3=A9ment L=C3=A9ger <cleger@rivosinc.com>
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Cl=C3=A9ment L=C3=A9ger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-8-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 59c4bf28ed..ce1256f439 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -306,6 +306,9 @@ target_ulong helper_sret(CPURISCVState *env)
}
mstatus =3D set_field(mstatus, MSTATUS_SDT, 0);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >=3D PRV_M) {
+ mstatus =3D set_field(mstatus, MSTATUS_MDT, 0);
+ }
if (env->priv_ver >=3D PRIV_VERSION_1_12_0) {
mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -391,6 +394,9 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
mstatus =3D ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt);
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mstatus =3D set_field(mstatus, MSTATUS_MDT, 0);
+ }
if ((env->priv_ver >=3D PRIV_VERSION_1_12_0) && (prev_priv !=3D PRV_M)=
) {
mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0);
}
@@ -436,6 +442,12 @@ target_ulong helper_mnret(CPURISCVState *env)
env->mstatus =3D ssdbltrp_mxret(env, env->mstatus, prev_priv, prev=
_virt);
}
=20
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ if (prev_priv < PRV_M) {
+ env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 0);
+ }
+ }
+
if (riscv_has_ext(env, RVH) && prev_virt) {
riscv_cpu_swap_hypervisor_regs(env);
}
--=20
2.48.1