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From: Alistair Francis <alistair23@gmail.com>
X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Kaiwen Xue <kaiwenx@rivosinc.com>,
Atish Patra <atishp@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 34/50] target/riscv: Add select value range check for
counter delegation
Date: Sun, 19 Jan 2025 11:12:09 +1000
Message-ID: <20250119011225.11452-35-alistair.francis@wdc.com>
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From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.
Co-developed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-7-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 36 +++++++++++++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 49648ddc95..df748dffa3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2159,6 +2159,11 @@ static bool xiselect_aia_range(target_ulong isel)
(ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LAST);
}
=20
+static bool xiselect_cd_range(target_ulong isel)
+{
+ return (ISELECT_CD_FIRST <=3D isel && isel <=3D ISELECT_CD_LAST);
+}
+
static int rmw_iprio(target_ulong xlen,
target_ulong iselect, uint8_t *iprio,
target_ulong *val, target_ulong new_val,
@@ -2284,6 +2289,17 @@ done:
return RISCV_EXCP_NONE;
}
=20
+static int rmw_xireg_cd(CPURISCVState *env, int csrno,
+ target_ulong isel, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ if (!riscv_cpu_cfg(env)->ext_smcdeleg) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ /* TODO: Implement the functionality later */
+ return RISCV_EXCP_NONE;
+}
+
/*
* rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6
*
@@ -2295,7 +2311,25 @@ static int rmw_xireg_csrind(CPURISCVState *env, int =
csrno,
target_ulong isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
- return -EINVAL;
+ int ret =3D -EINVAL;
+ bool virt =3D csrno =3D=3D CSR_VSIREG ? true : false;
+
+ if (xiselect_cd_range(isel)) {
+ ret =3D rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask);
+ } else {
+ /*
+ * As per the specification, access to unimplented region is undef=
ined
+ * but recommendation is to raise illegal instruction exception.
+ */
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if (ret) {
+ return (env->virt_enabled && virt) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return RISCV_EXCP_NONE;
}
=20
static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,
--=20
2.48.1