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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249230; x=1737854030; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xeNptC+QWnpU+5NAPa8/GJLL6/97Pfg0ebpvg1NlFls=; b=h7/lkP2kJmeOFzxXVbSGiXqECDHye4SIQs288nNSzKkOiP8bFWeBJtcA++zcBLZTIk dOWOY8PNepzWxNPctx2Lq7KoEp4Hd2+a+mVzeHhRP1+vneX2mYSvT+HY2YrmC7fYoxVp oisdfcoA5nWR+E//NzAliKjiH1jAplTQU+0HaRau4bSCFY/q7UuynJXatx4ri3IVOb6c MJl0uXl4XGyf5t/euyqrxf0TMvy5an2eeqC/49tG+G8PA0tRQ8fdDm+3kCznVO/lQ0r3 YsWMMeootlAyX/tL8SVmIWJ5LlFigJPeSWctHpsjcIk8kx40P/yWyrgQA8nF5bnNTgLC ttbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249230; x=1737854030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xeNptC+QWnpU+5NAPa8/GJLL6/97Pfg0ebpvg1NlFls=; b=YEE8ZA1PZEI/IF5wmpbLvHDQ/fVNJ7hIA2MY9aWiGtMooh1bygV68A8yhMAvcg8F/7 kQrhx+9NgMbCZsdcsDfqERGeIBnNMI3EyNLllsSdkE7u+hctBF7rnaVOSrd4rgnsjZNw 53QpvD5IehjTy0Ymttmr3NvWkZXTR6wunTlPLgjxFP32fGAPkkhMJWtNcb3rzVAYDVtY 5LsTBZVC93kHhiAUzsojRZ9qfDJGed3/8RdHFTomt0pDJh7erbqUmaJutwSExMBz/oyz jOrRvSIB+3YTkx42KYmwdhwY1iFnvyveG8/Armrg9FbcfMPNuPinLdXvmquYd6URS+U5 PQiQ== X-Gm-Message-State: AOJu0YwlK/nwEwsOgVGtREs56bd4Ng6HOu3sq0Vea3BuZtA2bKZkN/fA bAsaqn9ZCpXMNSQS9d6UOQSFcNlJ8UTSSFxyEo2rvT9bOJ1YSWS7TcGhNJnG X-Gm-Gg: ASbGncvXn65iUJqZCBWBLDHZgE6Uf1Wx9yevxMK7qlSzOrhhZ9ernfJfyW/OkXPFiEK Bv3LB8h+4EIf2g6J5ymbjSYKQ7mW8VXBC4NUxLPwv5LW+b0Ui/dYoKB7Yqukm+vi53yz1c947n3 Swy1MA7OPfzd5WtX2SCJ2KKgH/RZ3KdO6bIDHvq+A/jW1aqtl1pWLvNcLDvxJ97MBmb2/Hnar36 FqZK8zp4aTFnIB0MzqDsCy4H8HHhEjCZ3YgsuHt/N05lxpP5/ofxzpupfV0hKHkX+QZnq/AMnkJ DfzcB1jVXjOI1dB6ZjqVgflBCrr5J6bkMRUK6B5GemNxnDr52MZAO9AtsAyAQs/IrAc87j3uAw= = X-Google-Smtp-Source: AGHT+IExjd3f53bSIwkEIMRGPrxSadZgTf6p4E8yJxf3ePw52UOXQi13cHjXkzB7ImV5kWNNTxG0Jw== X-Received: by 2002:a17:90a:c2c5:b0:2ee:8008:b583 with SMTP id 98e67ed59e1d1-2f782c9c88fmr12756060a91.16.1737249230473; Sat, 18 Jan 2025 17:13:50 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tommy Wu , Frank Chang , Alistair Francis Subject: [PULL v2 21/50] target/riscv: Add Smrnmi CSRs Date: Sun, 19 Jan 2025 11:11:56 +1000 Message-ID: <20250119011225.11452-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1737249249141019000 Content-Type: text/plain; charset="utf-8" From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 7 ++++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/cpu.c | 5 +++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5e7152200f..5eaf9da1f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -480,6 +480,13 @@ struct CPUArchState { uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; #endif /* CONFIG_KVM */ + + /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; + target_ulong rnmip; }; =20 /* diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 797dd6985b..ba6fc546c4 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -353,6 +353,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf =20 +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -604,6 +610,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d9eb2c04c3..66193cd2f6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1127,6 +1127,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) riscv_trigger_reset_hold(env); } =20 + if (cpu->cfg.ext_smrnmi) { + env->rnmip =3D 0; + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b8cef52fe..af9766759a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -590,6 +590,17 @@ static RISCVException debug(CPURISCVState *env, int cs= rno) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 static RISCVException seed(CPURISCVState *env, int csrno) @@ -4376,6 +4387,67 @@ static RISCVException write_mcontext(CPURISCVState *= env, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mnscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask =3D (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |=3D MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus =3D (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + #endif =20 /* Crypto Extension */ @@ -4883,6 +4955,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_sstateen_1_3, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* RNMI */ + [CSR_MNSCRATCH] =3D { "mnscratch", rnmi, read_mnscratch, write_mnscrat= ch, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNEPC] =3D { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNCAUSE] =3D { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNSTATUS] =3D { "mnstatus", rnmi, read_mnstatus, write_mnstatu= s, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, --=20 2.48.1