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Sat, 18 Jan 2025 17:13:25 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 Date: Sun, 19 Jan 2025 11:11:49 +1000 Message-ID: <20250119011225.11452-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1737249225330019000 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-3-baturo.alexey@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/pmp.h | 1 + target/riscv/csr.c | 33 +++++++++++++++++++++++++++++++-- target/riscv/pmp.c | 14 +++++++++++--- 6 files changed, 58 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c78e97af50..ad33e96ddf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -128,6 +128,14 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; =20 +/* Enum holds PMM field values for Zjpm v1.0 extension */ +typedef enum { + PMM_FIELD_DISABLED =3D 0, + PMM_FIELD_RESERVED =3D 1, + PMM_FIELD_PMLEN7 =3D 2, + PMM_FIELD_PMLEN16 =3D 3, +} RISCVPmPmm; + typedef struct riscv_cpu_implied_exts_rule { #ifndef CONFIG_USER_ONLY /* diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c5b3de6469..797dd6985b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -575,6 +575,7 @@ typedef enum { #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HUKTE 0x01000000 #define HSTATUS_VSXL 0x300000000 +#define HSTATUS_HUPMM 0x3000000000000 =20 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL @@ -735,6 +736,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_PMM (3ULL << 32) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -751,6 +753,7 @@ typedef enum RISCVException { #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE #define SENVCFG_UKTE BIT(8) +#define SENVCFG_PMM MENVCFG_PMM =20 #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_LPE MENVCFG_LPE @@ -758,6 +761,7 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PMM MENVCFG_PMM #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fe0c4173d2..a36d3fada3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -129,6 +129,9 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_ssnpm; + bool ext_smnpm; + bool ext_smmpm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index e0530a17a3..271cf24169 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -46,6 +46,7 @@ typedef enum { MSECCFG_USEED =3D 1 << 8, MSECCFG_SSEED =3D 1 << 9, MSECCFG_MLPE =3D 1 << 10, + MSECCFG_PMM =3D 3ULL << 32, } mseccfg_field_t; =20 typedef struct { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 48abcab487..6b8cef52fe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -575,6 +575,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) if (riscv_cpu_cfg(env)->ext_zkr) { return RISCV_EXCP_NONE; } + if (riscv_cpu_cfg(env)->ext_smmpm) { + return RISCV_EXCP_NONE; + } =20 return RISCV_EXCP_ILLEGAL_INST; } @@ -2379,6 +2382,12 @@ static RISCVException write_menvcfg(CPURISCVState *e= nv, int csrno, if (env_archcpu(env)->cfg.ext_zicfiss) { mask |=3D MENVCFG_SSE; } + + /* Update PMM field only if the value is valid according to Zjpm v= 1.0 */ + if (env_archcpu(env)->cfg.ext_smnpm && + get_field(val, MENVCFG_PMM) !=3D PMM_FIELD_RESERVED) { + mask |=3D MENVCFG_PMM; + } } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 @@ -2425,6 +2434,12 @@ static RISCVException write_senvcfg(CPURISCVState *e= nv, int csrno, { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; RISCVException ret; + /* Update PMM field only if the value is valid according to Zjpm v1.0 = */ + if (env_archcpu(env)->cfg.ext_ssnpm && + riscv_cpu_mxl(env) =3D=3D MXL_RV64 && + get_field(val, SENVCFG_PMM) !=3D PMM_FIELD_RESERVED) { + mask |=3D SENVCFG_PMM; + } =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); if (ret !=3D RISCV_EXCP_NONE) { @@ -2493,6 +2508,12 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, get_field(env->menvcfg, MENVCFG_SSE)) { mask |=3D HENVCFG_SSE; } + + /* Update PMM field only if the value is valid according to Zjpm v= 1.0 */ + if (env_archcpu(env)->cfg.ext_ssnpm && + get_field(val, HENVCFG_PMM) !=3D PMM_FIELD_RESERVED) { + mask |=3D HENVCFG_PMM; + } } =20 env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); @@ -3529,10 +3550,18 @@ static RISCVException read_hstatus(CPURISCVState *e= nv, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + uint64_t mask =3D (target_ulong)-1; if (!env_archcpu(env)->cfg.ext_svukte) { - val =3D val & (~HSTATUS_HUKTE); + mask &=3D ~HSTATUS_HUKTE; } - env->hstatus =3D val; + /* Update PMM field only if the value is valid according to Zjpm v1.0 = */ + if (!env_archcpu(env)->cfg.ext_ssnpm || + riscv_cpu_mxl(env) !=3D MXL_RV64 || + get_field(val, HSTATUS_HUPMM) =3D=3D PMM_FIELD_RESERVED) { + mask &=3D ~HSTATUS_HUPMM; + } + env->hstatus =3D (env->hstatus & ~mask) | (val & mask); + if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a1b36664fc..a185c246d6 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -575,6 +575,13 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint= 32_t addr_index) void mseccfg_csr_write(CPURISCVState *env, target_ulong val) { int i; + uint64_t mask =3D MSECCFG_MMWP | MSECCFG_MML; + /* Update PMM field only if the value is valid according to Zjpm v1.0 = */ + if (riscv_cpu_cfg(env)->ext_smmpm && + riscv_cpu_mxl(env) =3D=3D MXL_RV64 && + get_field(val, MSECCFG_PMM) !=3D PMM_FIELD_RESERVED) { + mask |=3D MSECCFG_PMM; + } =20 trace_mseccfg_csr_write(env->mhartid, val); =20 @@ -590,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulo= ng val) =20 if (riscv_cpu_cfg(env)->ext_smepmp) { /* Sticky bits */ - val |=3D (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { + val |=3D (env->mseccfg & mask); + if ((val ^ env->mseccfg) & mask) { tlb_flush(env_cpu(env)); } } else { - val &=3D ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); + mask |=3D MSECCFG_RLB; + val &=3D ~(mask); } =20 /* M-mode forward cfi to be enabled if cfi extension is implemented */ --=20 2.48.1