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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f776185b02sm4760314a91.21.2025.01.18.17.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 17:13:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737249191; x=1737853991; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v87WTdDQC8DDzGlvKqDnGwAE9sgIictuWkNEBi5lUJ4=; b=Ib26ORRAFkVXqBfjCsO59i5DBiX699lsoJId6+vWeUFZ2w0juOqMCwwcDs/NEs9dPj yj1fkHMZ48cKNsQfsaYpYbDRse4oHaCEW5zL6Xjn8skooy4D/YXfw/2Uk2L35Gqm7yIk tZRuKab9/jtvIuhXwyKvAwunrrPMt1JXbT/RPLodSL6jvHrVZN2/uHubiWH/JFoS4nxv b4l1uWNVPWqr3IPfuGZRnKFsPvBeIE44HtgAGcptS5bOkbFD8P/eKvfMc7Ac3Nrx6HyF Kzd/2xxUrxjJSkI2mSvTjl1OKkmixYdNiUz5HZGtZ7YgKrHHf8E6X1qaihA09lvOfpu4 BSPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737249191; x=1737853991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v87WTdDQC8DDzGlvKqDnGwAE9sgIictuWkNEBi5lUJ4=; b=f37BqHx7MZUlfphHI3e1b/A37FIcKoMMRtGyyICKbxYOReNs+ev8MiLbS5/8x6mfgp Kp7DF6zTP69YyliNXnkHaojD/ku8gqTeX4Pcg9i2gtpe6u0n/GHEV0doLkjI28n+mWuq mNQuRtOt+4k2qekh1EH219JeVa+GlhBMsth6MiN88lv7WTIuc3lHNVfZF2EcvpkjLpYP ol5sB2lo+1sKP3t4XjQlZnr0fhWkyyKKAhrJ0R828iMtEBbWHJdZBfBqg3KqM1qzTL7a WSneneqydFOzI0X2HUbl9u7A2e/UZNP3pK77G03YatYBd1Q6bzT42H9wYBtHYa5FA8LB x9JA== X-Gm-Message-State: AOJu0YzZoWV97xaKIHZQEu2Tui11N3c1afWEBa6iMe7Jet9VDM91ij8f wvH8qcMy+U5D8S56LmX/jHNLY2Mw95NQotfhYvg3BcRzjmTRSjUgUVcEbur1 X-Gm-Gg: ASbGncvcNnIvn8/cFvvLWYMSEVjbq6FrTuAXmpjUAYnTARIkmhs0DaIhxpPyiEqceZo CJp60rtUra0gQud2wMIKb7R1JIKavhMUfE2LOtMwgW2T2ofBKO0K+vgj4NRYfDgP7jB/4qV2e7v aVpNbf47xM6Py6ARSbv0uRXGJwSROKtgbX38AQ5ZlZjDDUd7eKks2MraXNDar8IixtOrCkCOXi/ MUIoF+NnieuInFv3EESQ5jDf4fV1+VO6iwkGjns+KpNX5T9D8haRFNi+p9N6bqyQqvz4ZbEs9pQ TmUJdoYWj0+cwojdWi0nax4MPerV0ClYgxgrWSHGT/rJeEiBgt2EnG6Gzvh2KPuhawoFw3VsgQ= = X-Google-Smtp-Source: AGHT+IHyNodN6VQLXrJZ2GQInNzspBuYKOUudc6JI+1WotfXgnfFWCSXTr0K4oV9Stl8gvKcdljfpw== X-Received: by 2002:a17:90b:2e41:b0:2ee:f19b:86e5 with SMTP id 98e67ed59e1d1-2f782c71ec7mr13086094a91.14.1737249191512; Sat, 18 Jan 2025 17:13:11 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 10/50] target/riscv/tcg: add sha Date: Sun, 19 Jan 2025 11:11:45 +1000 Message-ID: <20250119011225.11452-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1737249444048019000 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza 'sha' is the augmented hypervisor extension, defined in RVA22 as a set of the following extensions: - RVH - Ssstateen - Shcounterenw (always present) - Shvstvala (always present) - Shtvala (always present) - Shvstvecd (always present) - Shvsatpa (always present) - Shgatpa (always present) We can claim support for 'sha' by checking if we have RVH and ssstateen. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652352-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 8 ++++++++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index a1457ab4f4..fe0c4173d2 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -141,6 +141,7 @@ struct RISCVCPUConfig { bool ext_svade; bool ext_zic64b; bool ext_ssstateen; + bool ext_sha; =20 /* * Always 'true' booleans for named features diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3e138572d4..954425081d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1714,6 +1715,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), + MULTI_EXT_CFG_BOOL("sha", ext_sha, true), =20 { }, }; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8b89c99c0f..e03b409248 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -212,6 +212,11 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu,= uint32_t feat_offset) cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; break; + case CPU_CFG_OFFSET(ext_sha): + if (!cpu_misa_ext_is_user_set(RVH)) { + riscv_cpu_write_misa_bit(cpu, RVH, true); + } + /* fallthrough */ case CPU_CFG_OFFSET(ext_ssstateen): cpu->cfg.ext_smstateen =3D true; break; @@ -352,6 +357,9 @@ static void riscv_cpu_update_named_features(RISCVCPU *c= pu) cpu->cfg.cboz_blocksize =3D=3D 64; =20 cpu->cfg.ext_ssstateen =3D cpu->cfg.ext_smstateen; + + cpu->cfg.ext_sha =3D riscv_has_ext(&cpu->env, RVH) && + cpu->cfg.ext_ssstateen; } =20 static void riscv_cpu_validate_g(RISCVCPU *cpu) --=20 2.48.1