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Fri, 17 Jan 2025 01:27:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVqG+RfH01JbScVMhK0hergPcEkoF02jSu7bcLe4UjTPb/cCZHpm3dL7gwCCHZiJ7iTX4U9Q== X-Received: by 2002:a17:907:7da2:b0:aa6:8a1b:8b84 with SMTP id a640c23a62f3a-ab38b5342demr211526766b.57.1737106037144; Fri, 17 Jan 2025 01:27:17 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: qemu-rust@nongnu.org Subject: [PATCH 08/10] rust: pl011: remove duplicate definitions Date: Fri, 17 Jan 2025 10:26:55 +0100 Message-ID: <20250117092657.1051233-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250117092657.1051233-1-pbonzini@redhat.com> References: <20250117092657.1051233-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737106112421019000 Content-Type: text/plain; charset="utf-8" Unify the "Interrupt" enum and the "INT_*" constants with a struct that contains the bits. The "int_level" and "int_enabled" fields could use a crate such as "bitflags". Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- rust/hw/char/pl011/src/device.rs | 36 ++++++++++++------------- rust/hw/char/pl011/src/lib.rs | 46 +++++++++++--------------------- 2 files changed, 33 insertions(+), 49 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index 1d3da59e481..6ecbfb9ac84 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -183,7 +183,7 @@ pub(self) fn read(&mut self, offset: RegisterOffset) ->= ControlFlow { self.flags.set_receive_fifo_empty(true); } if self.read_count + 1 =3D=3D self.read_trigger { - self.int_level &=3D !registers::INT_RX; + self.int_level &=3D !Interrupt::RX.0; } // Update error bits. self.receive_status_error_clear.set_from_data(c); @@ -232,7 +232,7 @@ pub(self) fn write( } // interrupts always checked let _ =3D self.loopback_tx(value); - self.int_level |=3D registers::INT_TX; + self.int_level |=3D Interrupt::TX.0; return true; } RSR =3D> { @@ -356,19 +356,19 @@ fn loopback_mdmctrl(&mut self) -> bool { // Change interrupts based on updated FR let mut il =3D self.int_level; =20 - il &=3D !Interrupt::MS; + il &=3D !Interrupt::MS.0; =20 if self.flags.data_set_ready() { - il |=3D Interrupt::DSR as u32; + il |=3D Interrupt::DSR.0; } if self.flags.data_carrier_detect() { - il |=3D Interrupt::DCD as u32; + il |=3D Interrupt::DCD.0; } if self.flags.clear_to_send() { - il |=3D Interrupt::CTS as u32; + il |=3D Interrupt::CTS.0; } if self.flags.ring_indicator() { - il |=3D Interrupt::RI as u32; + il |=3D Interrupt::RI.0; } self.int_level =3D il; true @@ -446,7 +446,7 @@ pub fn put_fifo(&mut self, value: u32) -> bool { } =20 if self.read_count =3D=3D self.read_trigger { - self.int_level |=3D registers::INT_RX; + self.int_level |=3D Interrupt::RX.0; return true; } false @@ -622,16 +622,16 @@ pub fn post_load(&self, _version_id: u32) -> Result<(= ), ()> { /// Which bits in the interrupt status matter for each outbound IRQ line ? const IRQMASK: [u32; 6] =3D [ /* combined IRQ */ - Interrupt::E - | Interrupt::MS - | Interrupt::RT as u32 - | Interrupt::TX as u32 - | Interrupt::RX as u32, - Interrupt::RX as u32, - Interrupt::TX as u32, - Interrupt::RT as u32, - Interrupt::MS, - Interrupt::E, + Interrupt::E.0 + | Interrupt::MS.0 + | Interrupt::RT.0 + | Interrupt::TX.0 + | Interrupt::RX.0, + Interrupt::RX.0, + Interrupt::TX.0, + Interrupt::RT.0, + Interrupt::MS.0, + Interrupt::E.0, ]; =20 /// # Safety diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index 2baacba2306..300c732ae1d 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -100,7 +100,6 @@ enum RegisterOffset { //Reserved =3D 0x04C, } =20 -#[allow(dead_code)] mod registers { //! Device registers exposed as typed structs which are backed by arbi= trary //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. @@ -521,38 +520,23 @@ fn default() -> Self { } =20 /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC - pub const INT_OE: u32 =3D 1 << 10; - pub const INT_BE: u32 =3D 1 << 9; - pub const INT_PE: u32 =3D 1 << 8; - pub const INT_FE: u32 =3D 1 << 7; - pub const INT_RT: u32 =3D 1 << 6; - pub const INT_TX: u32 =3D 1 << 5; - pub const INT_RX: u32 =3D 1 << 4; - pub const INT_DSR: u32 =3D 1 << 3; - pub const INT_DCD: u32 =3D 1 << 2; - pub const INT_CTS: u32 =3D 1 << 1; - pub const INT_RI: u32 =3D 1 << 0; - pub const INT_E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; - pub const INT_MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; - - #[repr(u32)] - pub enum Interrupt { - OE =3D 1 << 10, - BE =3D 1 << 9, - PE =3D 1 << 8, - FE =3D 1 << 7, - RT =3D 1 << 6, - TX =3D 1 << 5, - RX =3D 1 << 4, - DSR =3D 1 << 3, - DCD =3D 1 << 2, - CTS =3D 1 << 1, - RI =3D 1 << 0, - } + pub struct Interrupt(pub u32); =20 impl Interrupt { - pub const E: u32 =3D INT_OE | INT_BE | INT_PE | INT_FE; - pub const MS: u32 =3D INT_RI | INT_DSR | INT_DCD | INT_CTS; + pub const OE: Self =3D Self(1 << 10); + pub const BE: Self =3D Self(1 << 9); + pub const PE: Self =3D Self(1 << 8); + pub const FE: Self =3D Self(1 << 7); + pub const RT: Self =3D Self(1 << 6); + pub const TX: Self =3D Self(1 << 5); + pub const RX: Self =3D Self(1 << 4); + pub const DSR: Self =3D Self(1 << 3); + pub const DCD: Self =3D Self(1 << 2); + pub const CTS: Self =3D Self(1 << 1); + pub const RI: Self =3D Self(1 << 0); + + pub const E: Self =3D Self(Self::OE.0 | Self::BE.0 | Self::PE.0 | = Self::FE.0); + pub const MS: Self =3D Self(Self::RI.0 | Self::DSR.0 | Self::DCD.0= | Self::CTS.0); } } =20 --=20 2.47.1