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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.093, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1737106062184019000 Content-Type: text/plain; charset="utf-8" As an added bonus, this also makes the new function return u32 instead of u64, thus factoring some casts into a single place. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- rust/hw/char/pl011/src/device.rs | 114 +++++++++++++++++-------------- 1 file changed, 63 insertions(+), 51 deletions(-) diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index e85e46ba0bb..6d662865182 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -5,6 +5,7 @@ use core::ptr::{addr_of_mut, NonNull}; use std::{ ffi::CStr, + ops::ControlFlow, os::raw::{c_int, c_uint, c_void}, }; =20 @@ -214,19 +215,11 @@ fn post_init(&self) { } } =20 - pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::Con= trolFlow { + fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow { use RegisterOffset::*; =20 - let value =3D match RegisterOffset::try_from(offset) { - Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> { - let device_id =3D self.get_class().device_id; - u32::from(device_id[(offset - 0xfe0) >> 2]) - } - Err(_) =3D> { - // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); - 0 - } - Ok(DR) =3D> { + std::ops::ControlFlow::Break(match offset { + DR =3D> { self.flags.set_receive_fifo_full(false); let c =3D self.read_fifo[self.read_pos]; if self.read_count > 0 { @@ -243,39 +236,33 @@ pub fn read(&mut self, offset: hwaddr, _size: c_uint)= -> std::ops::ControlFlow u32::from(self.receive_status_error_clear), - Ok(FR) =3D> u32::from(self.flags), - Ok(FBRD) =3D> self.fbrd, - Ok(ILPR) =3D> self.ilpr, - Ok(IBRD) =3D> self.ibrd, - Ok(LCR_H) =3D> u32::from(self.line_control), - Ok(CR) =3D> u32::from(self.control), - Ok(FLS) =3D> self.ifl, - Ok(IMSC) =3D> self.int_enabled, - Ok(RIS) =3D> self.int_level, - Ok(MIS) =3D> self.int_level & self.int_enabled, - Ok(ICR) =3D> { + return ControlFlow::Continue(u32::from(c)); + }, + RSR =3D> u32::from(self.receive_status_error_clear), + FR =3D> u32::from(self.flags), + FBRD =3D> self.fbrd, + ILPR =3D> self.ilpr, + IBRD =3D> self.ibrd, + LCR_H =3D> u32::from(self.line_control), + CR =3D> u32::from(self.control), + FLS =3D> self.ifl, + IMSC =3D> self.int_enabled, + RIS =3D> self.int_level, + MIS =3D> self.int_level & self.int_enabled, + ICR =3D> { // "The UARTICR Register is the interrupt clear register a= nd is write-only" // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, = UARTICR 0 - } - Ok(DMACR) =3D> self.dmacr, - }; - std::ops::ControlFlow::Break(value.into()) + }, + DMACR =3D> self.dmacr, + }) } =20 - pub fn write(&mut self, offset: hwaddr, value: u64) { + fn regs_write(&mut self, offset: RegisterOffset, value: u32) { // eprintln!("write offset {offset} value {value}"); use RegisterOffset::*; - let value: u32 =3D value as u32; - match RegisterOffset::try_from(offset) { - Err(_bad_offset) =3D> { - eprintln!("write bad offset {offset} value {value}"); - } - Ok(DR) =3D> { + match offset { + DR =3D> { // ??? Check if transmitter is enabled. let ch: u8 =3D value as u8; // XXX this blocks entire thread. Rewrite to use @@ -290,22 +277,22 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { self.int_level |=3D registers::INT_TX; self.update(); } - Ok(RSR) =3D> { - self.receive_status_error_clear.reset(); + RSR =3D> { + self.receive_status_error_clear =3D 0.into(); } - Ok(FR) =3D> { + FR =3D> { // flag writes are ignored } - Ok(ILPR) =3D> { + ILPR =3D> { self.ilpr =3D value; } - Ok(IBRD) =3D> { + IBRD =3D> { self.ibrd =3D value; } - Ok(FBRD) =3D> { + FBRD =3D> { self.fbrd =3D value; } - Ok(LCR_H) =3D> { + LCR_H =3D> { let new_val: registers::LineControl =3D value.into(); // Reset the FIFO state on FIFO enable or disable if self.line_control.fifos_enabled() !=3D new_val.fifos_en= abled() { @@ -328,26 +315,26 @@ pub fn write(&mut self, offset: hwaddr, value: u64) { self.line_control =3D new_val; self.set_read_trigger(); } - Ok(CR) =3D> { + CR =3D> { // ??? Need to implement the enable bit. self.control =3D value.into(); self.loopback_mdmctrl(); } - Ok(FLS) =3D> { + FLS =3D> { self.ifl =3D value; self.set_read_trigger(); } - Ok(IMSC) =3D> { + IMSC =3D> { self.int_enabled =3D value; self.update(); } - Ok(RIS) =3D> {} - Ok(MIS) =3D> {} - Ok(ICR) =3D> { + RIS =3D> {} + MIS =3D> {} + ICR =3D> { self.int_level &=3D !value; self.update(); } - Ok(DMACR) =3D> { + DMACR =3D> { self.dmacr =3D value; if value & 3 > 0 { // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemente= d\n"); @@ -562,6 +549,31 @@ pub fn post_load(&mut self, _version_id: u32) -> Resul= t<(), ()> { =20 Ok(()) } + + pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow { + match RegisterOffset::try_from(offset) { + Err(v) if (0x3f8..0x400).contains(&(v >> 2)) =3D> { + let device_id =3D self.get_class().device_id; + ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >>= 2])) + } + Err(_) =3D> { + // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset = 0x%x\n", (int)offset); + ControlFlow::Break(0) + } + Ok(field) =3D> match self.regs_read(field) { + ControlFlow::Break(value) =3D> ControlFlow::Break(value.in= to()), + ControlFlow::Continue(value) =3D> ControlFlow::Continue(va= lue.into()), + } + } + } + + pub fn write(&mut self, offset: hwaddr, value: u64) { + if let Ok(field) =3D RegisterOffset::try_from(offset) { + self.regs_write(field, value as u32); + } else { + eprintln!("write bad offset {offset} value {value}"); + } + } } =20 /// Which bits in the interrupt status matter for each outbound IRQ line ? --=20 2.47.1