From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1736993957951495.91202271407644; Wed, 15 Jan 2025 18:19:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS3-0004co-PJ; Wed, 15 Jan 2025 21:17:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFRz-0004b5-GB for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRv-0006CQ-2O for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:38 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxCeE8bIhnajJkAA--.65511S3; Thu, 16 Jan 2025 10:17:32 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S3; Thu, 16 Jan 2025 10:17:31 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen , Miao Hao Subject: [PULL 1/8] target/loongarch: Add page table walker support for debugger usage Date: Thu, 16 Jan 2025 10:17:03 +0800 Message-Id: <20250116021710.251648-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993960003019000 Content-Type: text/plain; charset="utf-8" From: Miao Hao When dump memory content with gva address, software page table walker is necessary to get responding gpa address. Here page table walker is added for debugger usage. Signed-off-by: Miao Hao Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- target/loongarch/cpu_helper.c | 94 +++++++++++++++++++++++++++++-- target/loongarch/internals.h | 4 +- target/loongarch/tcg/tlb_helper.c | 4 +- 3 files changed, 94 insertions(+), 8 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 580362ac3e..930466ca48 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -141,9 +141,85 @@ bool loongarch_tlb_search(CPULoongArchState *env, targ= et_ulong vaddr, return false; } =20 +static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *phy= sical, + int *prot, target_ulong address) +{ + CPUState *cs =3D env_cpu(env); + target_ulong index, phys; + uint64_t dir_base, dir_width; + uint64_t base; + int level; + + if ((address >> 63) & 0x1) { + base =3D env->CSR_PGDH; + } else { + base =3D env->CSR_PGDL; + } + base &=3D TARGET_PHYS_MASK; + + for (level =3D 4; level > 0; level--) { + get_dir_base_width(env, &dir_base, &dir_width, level); + + if (dir_width =3D=3D 0) { + continue; + } + + /* get next level page directory */ + index =3D (address >> dir_base) & ((1 << dir_width) - 1); + phys =3D base | index << 3; + base =3D ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; + if (FIELD_EX64(base, TLBENTRY, HUGE)) { + /* base is a huge pte */ + break; + } + } + + /* pte */ + if (FIELD_EX64(base, TLBENTRY, HUGE)) { + /* Huge Page. base is pte */ + base =3D FIELD_DP64(base, TLBENTRY, LEVEL, 0); + base =3D FIELD_DP64(base, TLBENTRY, HUGE, 0); + if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) { + base =3D FIELD_DP64(base, TLBENTRY, HGLOBAL, 0); + base =3D FIELD_DP64(base, TLBENTRY, G, 1); + } + } else { + /* Normal Page. base points to pte */ + get_dir_base_width(env, &dir_base, &dir_width, 0); + index =3D (address >> dir_base) & ((1 << dir_width) - 1); + phys =3D base | index << 3; + base =3D ldq_phys(cs->as, phys); + } + + /* TODO: check plv and other bits? */ + + /* base is pte, in normal pte format */ + if (!FIELD_EX64(base, TLBENTRY, V)) { + return TLBRET_NOMATCH; + } + + if (!FIELD_EX64(base, TLBENTRY, D)) { + *prot =3D PAGE_READ; + } else { + *prot =3D PAGE_READ | PAGE_WRITE; + } + + /* get TARGET_PAGE_SIZE aligned physical address */ + base +=3D (address & TARGET_PHYS_MASK) & ((1 << dir_base) - 1); + /* mask RPLV, NX, NR bits */ + base =3D FIELD_DP64(base, TLBENTRY_64, RPLV, 0); + base =3D FIELD_DP64(base, TLBENTRY_64, NX, 0); + base =3D FIELD_DP64(base, TLBENTRY_64, NR, 0); + /* mask other attribute bits */ + *physical =3D base & TARGET_PAGE_MASK; + + return 0; +} + static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx) + MMUAccessType access_type, int mmu_idx, + int is_debug) { int index, match; =20 @@ -151,6 +227,13 @@ static int loongarch_map_address(CPULoongArchState *en= v, hwaddr *physical, if (match) { return loongarch_map_tlb_entry(env, physical, prot, address, access_type, index, mmu_id= x); + } else if (is_debug) { + /* + * For debugger memory access, we want to do the map when there is= a + * legal mapping, even if the mapping is not yet in TLB. return 0 = if + * there is a valid map, else none zero. + */ + return loongarch_page_table_walker(env, physical, prot, address); } =20 return TLBRET_NOMATCH; @@ -158,7 +241,8 @@ static int loongarch_map_address(CPULoongArchState *env= , hwaddr *physical, #else static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx) + MMUAccessType access_type, int mmu_idx, + int is_debug) { return TLBRET_NOMATCH; } @@ -178,7 +262,7 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, target_= ulong va, =20 int get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx) + MMUAccessType access_type, int mmu_idx, int is_de= bug) { int user_mode =3D mmu_idx =3D=3D MMU_USER_IDX; int kernel_mode =3D mmu_idx =3D=3D MMU_KERNEL_IDX; @@ -222,7 +306,7 @@ int get_physical_address(CPULoongArchState *env, hwaddr= *physical, =20 /* Mapped address */ return loongarch_map_address(env, physical, prot, address, - access_type, mmu_idx); + access_type, mmu_idx, is_debug); } =20 hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -232,7 +316,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) int prot; =20 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(cs, false)) !=3D 0) { + cpu_mmu_index(cs, false), 1) !=3D 0) { return -1; } return phys_addr; diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index ad9cf4fc7a..7b254c5f49 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -56,7 +56,9 @@ bool loongarch_tlb_search(CPULoongArchState *env, target_= ulong vaddr, int *index); int get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx); + MMUAccessType access_type, int mmu_idx, int is_de= bug); +void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, + uint64_t *dir_width, target_ulong level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 #ifdef CONFIG_TCG diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 8c61fe728c..a323606e5a 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -18,7 +18,7 @@ #include "exec/log.h" #include "cpu-csr.h" =20 -static void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, +void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, target_ulong level) { switch (level) { @@ -485,7 +485,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, =20 /* Data access */ ret =3D get_physical_address(env, &physical, &prot, address, - access_type, mmu_idx); + access_type, mmu_idx, 0); =20 if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, --=20 2.43.5 From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173699393414381.85368826971262; Wed, 15 Jan 2025 18:18:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS5-0004cx-Qn; Wed, 15 Jan 2025 21:17:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFS0-0004bo-N1 for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:42 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRx-0006CN-HL for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:40 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxrnM8bIhnaTJkAA--.10971S3; Thu, 16 Jan 2025 10:17:32 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S4; Thu, 16 Jan 2025 10:17:32 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen Subject: [PULL 2/8] hw/intc/loongarch_ipi: Implement realize interface Date: Thu, 16 Jan 2025 10:17:04 +0800 Message-Id: <20250116021710.251648-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993935736019000 Content-Type: text/plain; charset="utf-8" Add realize interface for loongarch ipi device. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 19 +++++++++++++++++++ include/hw/intc/loongarch_ipi.h | 1 + 2 files changed, 20 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 2ae1a42c46..4e2f9acddf 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -7,6 +7,7 @@ =20 #include "qemu/osdep.h" #include "hw/boards.h" +#include "qapi/error.h" #include "hw/intc/loongarch_ipi.h" #include "target/loongarch/cpu.h" =20 @@ -49,10 +50,26 @@ static CPUState *loongarch_cpu_by_arch_id(int64_t arch_= id) return NULL; } =20 +static void loongarch_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongarchIPIClass *lic =3D LOONGARCH_IPI_GET_CLASS(dev); + Error *local_err =3D NULL; + + lic->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } +} + static void loongarch_ipi_class_init(ObjectClass *klass, void *data) { LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); + LoongarchIPIClass *lic =3D LOONGARCH_IPI_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + device_class_set_parent_realize(dc, loongarch_ipi_realize, + &lic->parent_realize); licc->get_iocsr_as =3D get_iocsr_as; licc->cpu_by_arch_id =3D loongarch_cpu_by_arch_id; } @@ -61,6 +78,8 @@ static const TypeInfo loongarch_ipi_types[] =3D { { .name =3D TYPE_LOONGARCH_IPI, .parent =3D TYPE_LOONGSON_IPI_COMMON, + .instance_size =3D sizeof(LoongarchIPIState), + .class_size =3D sizeof(LoongarchIPIClass), .class_init =3D loongarch_ipi_class_init, } }; diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h index 276b3040a3..923bf21ecb 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -20,6 +20,7 @@ struct LoongarchIPIState { =20 struct LoongarchIPIClass { LoongsonIPICommonClass parent_class; + DeviceRealize parent_realize; }; =20 #endif --=20 2.43.5 From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1736993902509728.363109194609; Wed, 15 Jan 2025 18:18:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS2-0004cF-Js; Wed, 15 Jan 2025 21:17:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFRz-0004b7-M6 for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRv-0006Cc-VE for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxaeA9bIhnbzJkAA--.44720S3; Thu, 16 Jan 2025 10:17:33 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S5; Thu, 16 Jan 2025 10:17:32 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen Subject: [PULL 3/8] hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_common Date: Thu, 16 Jan 2025 10:17:05 +0800 Message-Id: <20250116021710.251648-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993903545019000 Content-Type: text/plain; charset="utf-8" With mips64 loongson ipi, num_cpu property is used. With loongarch ipi, num_cpu can be acquired from possible_cpu_arch_ids. Here remove num_cpu setting from loongson_ipi_common, and this piece of code is put into loongson and loongarch ipi separately. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 13 +++++++++++++ hw/intc/loongson_ipi.c | 14 +++++++++++++- hw/intc/loongson_ipi_common.c | 14 -------------- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 4e2f9acddf..e6126e4fbc 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -52,14 +52,27 @@ static CPUState *loongarch_cpu_by_arch_id(int64_t arch_= id) =20 static void loongarch_ipi_realize(DeviceState *dev, Error **errp) { + LoongsonIPICommonState *lics =3D LOONGSON_IPI_COMMON(dev); LoongarchIPIClass *lic =3D LOONGARCH_IPI_GET_CLASS(dev); Error *local_err =3D NULL; + int i; =20 lic->parent_realize(dev, &local_err); if (local_err) { error_propagate(errp, local_err); return; } + + if (lics->num_cpu =3D=3D 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + lics->cpu =3D g_new0(IPICore, lics->num_cpu); + for (i =3D 0; i < lics->num_cpu; i++) { + lics->cpu[i].ipi =3D lics; + qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1); + } } =20 static void loongarch_ipi_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 4e08f03510..1ed39b90ea 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -36,6 +36,7 @@ static void loongson_ipi_realize(DeviceState *dev, Error = **errp) LoongsonIPIClass *lic =3D LOONGSON_IPI_GET_CLASS(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); Error *local_err =3D NULL; + int i; =20 lic->parent_realize(dev, &local_err); if (local_err) { @@ -43,8 +44,19 @@ static void loongson_ipi_realize(DeviceState *dev, Error= **errp) return; } =20 + if (sc->num_cpu =3D=3D 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + sc->cpu =3D g_new0(IPICore, sc->num_cpu); + for (i =3D 0; i < sc->num_cpu; i++) { + sc->cpu[i].ipi =3D sc; + qdev_init_gpio_out(dev, &sc->cpu[i].irq, 1); + } + s->ipi_mmio_mem =3D g_new0(MemoryRegion, sc->num_cpu); - for (unsigned i =3D 0; i < sc->num_cpu; i++) { + for (i =3D 0; i < sc->num_cpu; i++) { g_autofree char *name =3D g_strdup_printf("loongson_ipi_cpu%d_mmio= ", i); =20 memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 9a081565f5..5d46679ea1 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -10,7 +10,6 @@ #include "hw/intc/loongson_ipi_common.h" #include "hw/irq.h" #include "hw/qdev-properties.h" -#include "qapi/error.h" #include "qemu/log.h" #include "migration/vmstate.h" #include "trace.h" @@ -253,12 +252,6 @@ static void loongson_ipi_common_realize(DeviceState *d= ev, Error **errp) { LoongsonIPICommonState *s =3D LOONGSON_IPI_COMMON(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu =3D=3D 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } =20 memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_iocsr_ops, @@ -273,13 +266,6 @@ static void loongson_ipi_common_realize(DeviceState *d= ev, Error **errp) &loongson_ipi64_ops, s, "loongson_ipi64_iocsr", 0x118); sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu =3D g_new0(IPICore, s->num_cpu); - for (i =3D 0; i < s->num_cpu; i++) { - s->cpu[i].ipi =3D s; - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } } =20 static void loongson_ipi_common_unrealize(DeviceState *dev) --=20 2.43.5 From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1736993932634249.16789065977628; Wed, 15 Jan 2025 18:18:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS5-0004cq-CI; Wed, 15 Jan 2025 21:17:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFRz-0004b8-NV for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRx-0006Ck-An for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axjq8+bIhnczJkAA--.41634S3; Thu, 16 Jan 2025 10:17:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S6; Thu, 16 Jan 2025 10:17:33 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen Subject: [PULL 4/8] hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_common Date: Thu, 16 Jan 2025 10:17:06 +0800 Message-Id: <20250116021710.251648-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993934107019000 Content-Type: text/plain; charset="utf-8" With mips64 loongson ipi, num_cpu property is used. With loongarch ipi, num_cpu can be acquired from possible_cpu_arch_ids. Here remove property num_cpu from loongson_ipi_common, and put it into loongson and loongarch ipi separately. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 6 ++++++ hw/intc/loongson_ipi.c | 6 ++++++ hw/intc/loongson_ipi_common.c | 6 ------ 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index e6126e4fbc..9c7636c4d6 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -9,6 +9,7 @@ #include "hw/boards.h" #include "qapi/error.h" #include "hw/intc/loongarch_ipi.h" +#include "hw/qdev-properties.h" #include "target/loongarch/cpu.h" =20 static AddressSpace *get_iocsr_as(CPUState *cpu) @@ -75,6 +76,10 @@ static void loongarch_ipi_realize(DeviceState *dev, Erro= r **errp) } } =20 +static const Property loongarch_ipi_properties[] =3D { + DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), +}; + static void loongarch_ipi_class_init(ObjectClass *klass, void *data) { LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); @@ -83,6 +88,7 @@ static void loongarch_ipi_class_init(ObjectClass *klass, = void *data) =20 device_class_set_parent_realize(dc, loongarch_ipi_realize, &lic->parent_realize); + device_class_set_props(dc, loongarch_ipi_properties); licc->get_iocsr_as =3D get_iocsr_as; licc->cpu_by_arch_id =3D loongarch_cpu_by_arch_id; } diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 1ed39b90ea..29e92d48fd 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -7,6 +7,7 @@ =20 #include "qemu/osdep.h" #include "hw/intc/loongson_ipi.h" +#include "hw/qdev-properties.h" #include "qapi/error.h" #include "target/mips/cpu.h" =20 @@ -75,6 +76,10 @@ static void loongson_ipi_unrealize(DeviceState *dev) k->parent_unrealize(dev); } =20 +static const Property loongson_ipi_properties[] =3D { + DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), +}; + static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -85,6 +90,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, v= oid *data) &lic->parent_realize); device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); + device_class_set_props(dc, loongson_ipi_properties); licc->get_iocsr_as =3D get_iocsr_as; licc->cpu_by_arch_id =3D cpu_by_arch_id; } diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 5d46679ea1..363cddc54c 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -9,7 +9,6 @@ #include "hw/sysbus.h" #include "hw/intc/loongson_ipi_common.h" #include "hw/irq.h" -#include "hw/qdev-properties.h" #include "qemu/log.h" #include "migration/vmstate.h" #include "trace.h" @@ -301,10 +300,6 @@ static const VMStateDescription vmstate_loongson_ipi_c= ommon =3D { } }; =20 -static const Property ipi_common_properties[] =3D { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), -}; - static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -314,7 +309,6 @@ static void loongson_ipi_common_class_init(ObjectClass = *klass, void *data) &licc->parent_realize); device_class_set_parent_unrealize(dc, loongson_ipi_common_unrealize, &licc->parent_unrealize); - device_class_set_props(dc, ipi_common_properties); dc->vmsd =3D &vmstate_loongson_ipi_common; } =20 --=20 2.43.5 From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17369939644831.3469975852397056; Wed, 15 Jan 2025 18:19:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS6-0004cy-5Z; Wed, 15 Jan 2025 21:17:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFRz-0004bB-Um for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRx-0006Cx-Gh for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxaeA+bIhndzJkAA--.44723S3; Thu, 16 Jan 2025 10:17:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S7; Thu, 16 Jan 2025 10:17:34 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen Subject: [PULL 5/8] hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids Date: Thu, 16 Jan 2025 10:17:07 +0800 Message-Id: <20250116021710.251648-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993965871019000 Content-Type: text/plain; charset="utf-8" Supported CPU number can be acquired from function possible_cpu_arch_ids(), cpu-num property is not necessary and can be removed. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 13 ++++++++----- include/hw/intc/loongson_ipi_common.h | 2 ++ 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 9c7636c4d6..49b4595d90 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -55,6 +55,9 @@ static void loongarch_ipi_realize(DeviceState *dev, Error= **errp) { LoongsonIPICommonState *lics =3D LOONGSON_IPI_COMMON(dev); LoongarchIPIClass *lic =3D LOONGARCH_IPI_GET_CLASS(dev); + MachineState *machine =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list; Error *local_err =3D NULL; int i; =20 @@ -64,13 +67,13 @@ static void loongarch_ipi_realize(DeviceState *dev, Err= or **errp) return; } =20 - if (lics->num_cpu =3D=3D 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - + assert(mc->possible_cpu_arch_ids); + id_list =3D mc->possible_cpu_arch_ids(machine); + lics->num_cpu =3D id_list->len; lics->cpu =3D g_new0(IPICore, lics->num_cpu); for (i =3D 0; i < lics->num_cpu; i++) { + lics->cpu[i].arch_id =3D id_list->cpus[i].arch_id; + lics->cpu[i].cpu =3D CPU(id_list->cpus[i].cpu); lics->cpu[i].ipi =3D lics; qdev_init_gpio_out(dev, &lics->cpu[i].irq, 1); } diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongs= on_ipi_common.h index df9d9c5168..4192f3d548 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -27,6 +27,8 @@ typedef struct IPICore { /* 64bit buf divide into 2 32-bit buf */ uint32_t buf[IPI_MBX_NUM * 2]; qemu_irq irq; + uint64_t arch_id; + CPUState *cpu; } IPICore; =20 struct LoongsonIPICommonState { --=20 2.43.5 From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173699392241487.85466165607124; Wed, 15 Jan 2025 18:18:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS3-0004cP-7H; Wed, 15 Jan 2025 21:17:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFRz-0004b6-I5 for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRx-0006Cv-9g for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:39 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx_3M_bIhnezJkAA--.11009S3; Thu, 16 Jan 2025 10:17:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S8; Thu, 16 Jan 2025 10:17:34 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen Subject: [PULL 6/8] hw/intc/loongarch_ipi: Remove property num-cpu Date: Thu, 16 Jan 2025 10:17:08 +0800 Message-Id: <20250116021710.251648-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993923770019000 Content-Type: text/plain; charset="utf-8" Since cpu number can be acquired from possible_cpu_arch_ids(), num-cpu property is not necessary. Here remove num-cpu property for object TYPE_LOONGARCH_IPI object. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 5 ----- hw/loongarch/virt.c | 1 - 2 files changed, 6 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 49b4595d90..41d9625dcb 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -79,10 +79,6 @@ static void loongarch_ipi_realize(DeviceState *dev, Erro= r **errp) } } =20 -static const Property loongarch_ipi_properties[] =3D { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), -}; - static void loongarch_ipi_class_init(ObjectClass *klass, void *data) { LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); @@ -91,7 +87,6 @@ static void loongarch_ipi_class_init(ObjectClass *klass, = void *data) =20 device_class_set_parent_realize(dc, loongarch_ipi_realize, &lic->parent_realize); - device_class_set_props(dc, loongarch_ipi_properties); licc->get_iocsr_as =3D get_iocsr_as; licc->cpu_by_arch_id =3D loongarch_cpu_by_arch_id; } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index db37ed6a71..63fa0f4e32 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -899,7 +899,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) =20 /* Create IPI device */ ipi =3D qdev_new(TYPE_LOONGARCH_IPI); - qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); =20 /* IPI iocsr memory region */ --=20 2.43.5 From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1736993928996933.4145547662665; Wed, 15 Jan 2025 18:18:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS6-0004d2-72; Wed, 15 Jan 2025 21:17:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFS1-0004bs-3P for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:42 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRy-0006D8-0L for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:40 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Ax6+E_bIhnfzJkAA--.64937S3; Thu, 16 Jan 2025 10:17:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S9; Thu, 16 Jan 2025 10:17:35 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen Subject: [PULL 7/8] hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id Date: Thu, 16 Jan 2025 10:17:09 +0800 Message-Id: <20250116021710.251648-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993929804019000 Content-Type: text/plain; charset="utf-8" Add logic cpu index input parameter for function cpu_by_arch_id, CPUState::cpu_index is logic cpu slot index for possible_cpus. At the same time it is logic index with LoongsonIPICommonState::IPICore, here hide access for CPUState::cpu_index directly, it comes from function cpu_by_arch_id(). Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 19 +++++++++++++++---- hw/intc/loongson_ipi.c | 23 ++++++++++++++++++++++- hw/intc/loongson_ipi_common.c | 21 ++++++++++++--------- include/hw/intc/loongson_ipi_common.h | 3 ++- 4 files changed, 51 insertions(+), 15 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 41d9625dcb..515549e8a5 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -38,17 +38,28 @@ static CPUArchId *find_cpu_by_archid(MachineState *ms, = uint32_t id) return found_cpu; } =20 -static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState = **pcs) { MachineState *machine =3D MACHINE(qdev_get_machine()); CPUArchId *archid; + CPUState *cs; =20 archid =3D find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); + if (archid && archid->cpu) { + cs =3D archid->cpu; + if (index) { + *index =3D cs->cpu_index; + } + + if (pcs) { + *pcs =3D cs; + } + + return MEMTX_OK; } =20 - return NULL; + return MEMTX_ERROR; } =20 static void loongarch_ipi_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 29e92d48fd..d2268a27f8 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -20,6 +20,27 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } =20 +static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState *= *pcs) +{ + CPUState *cs; + + cs =3D cpu_by_arch_id(arch_id); + if (cs =3D=3D NULL) { + return MEMTX_ERROR; + } + + if (index) { + *index =3D cs->cpu_index; + } + + if (pcs) { + *pcs =3D cs; + } + + return MEMTX_OK; +} + static const MemoryRegionOps loongson_ipi_core_ops =3D { .read_with_attrs =3D loongson_ipi_core_readl, .write_with_attrs =3D loongson_ipi_core_writel, @@ -92,7 +113,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, = void *data) &lic->parent_unrealize); device_class_set_props(dc, loongson_ipi_properties); licc->get_iocsr_as =3D get_iocsr_as; - licc->cpu_by_arch_id =3D cpu_by_arch_id; + licc->cpu_by_arch_id =3D loongson_cpu_by_arch_id; } =20 static const TypeInfo loongson_ipi_types[] =3D { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index 363cddc54c..f5ab5024c0 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -103,16 +103,17 @@ static MemTxResult mail_send(LoongsonIPICommonState *= ipi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; =20 cpuid =3D extract32(val, 16, 10); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { + ret =3D licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret !=3D MEMTX_OK) { return MEMTX_DECODE_ERROR; } =20 /* override requester_id */ addr =3D SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id =3D cs->cpu_index; + attrs.requester_id =3D cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } =20 @@ -123,16 +124,17 @@ static MemTxResult any_send(LoongsonIPICommonState *i= pi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; =20 cpuid =3D extract32(val, 16, 10); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { + ret =3D licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret !=3D MEMTX_OK) { return MEMTX_DECODE_ERROR; } =20 /* override requester_id */ addr =3D val & 0xffff; - attrs.requester_id =3D cs->cpu_index; + attrs.requester_id =3D cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } =20 @@ -146,6 +148,7 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwad= dr addr, uint64_t val, uint32_t cpuid; uint8_t vector; CPUState *cs; + int cpu, ret; =20 addr &=3D 0xff; trace_loongson_ipi_write(size, (uint64_t)addr, val); @@ -176,11 +179,11 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hw= addr addr, uint64_t val, cpuid =3D extract32(val, 16, 10); /* IPI status vector */ vector =3D extract8(val, 0, 5); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { + ret =3D licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret !=3D MEMTX_OK || cpu >=3D ipi->num_cpu) { return MEMTX_DECODE_ERROR; } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + loongson_ipi_core_writel(&ipi->cpu[cpu], CORE_SET_OFF, BIT(vector), 4, attrs); break; default: diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongs= on_ipi_common.h index 4192f3d548..b587f9c571 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -46,7 +46,8 @@ struct LoongsonIPICommonClass { DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; AddressSpace *(*get_iocsr_as)(CPUState *cpu); - CPUState *(*cpu_by_arch_id)(int64_t id); + int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id, + int *index, CPUState **pcs); }; =20 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *d= ata, --=20 2.43.5 From nobody Sun Apr 6 03:35:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1736993958374796.2658561821885; Wed, 15 Jan 2025 18:19:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFS3-0004cn-Mo; Wed, 15 Jan 2025 21:17:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tYFS1-0004br-33 for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:42 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tYFRy-0006DF-IA for qemu-devel@nongnu.org; Wed, 15 Jan 2025 21:17:40 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxG6xAbIhngzJkAA--.10997S3; Thu, 16 Jan 2025 10:17:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMAx+8QnbIhnhWokAA--.14648S10; Thu, 16 Jan 2025 10:17:35 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , Jiaxun Yang , Huacai Chen Subject: [PULL 8/8] hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id Date: Thu, 16 Jan 2025 10:17:10 +0800 Message-Id: <20250116021710.251648-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250116021710.251648-1-maobibo@loongson.cn> References: <20250116021710.251648-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAx+8QnbIhnhWokAA--.14648S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736993959893019000 Content-Type: text/plain; charset="utf-8" There is arch_id and CPUState pointer in IPICore object. With function cpu_by_arch_id() it can be implemented by parsing IPICore array inside, rather than possible_cpus array. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 36 +++++++++++------------------------- 1 file changed, 11 insertions(+), 25 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 515549e8a5..5376f1e084 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -17,43 +17,29 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return LOONGARCH_CPU(cpu)->env.address_space_iocsr; } =20 -static int archid_cmp(const void *a, const void *b) +static int loongarch_ipi_cmp(const void *a, const void *b) { - CPUArchId *archid_a =3D (CPUArchId *)a; - CPUArchId *archid_b =3D (CPUArchId *)b; + IPICore *ipi_a =3D (IPICore *)a; + IPICore *ipi_b =3D (IPICore *)b; =20 - return archid_a->arch_id - archid_b->arch_id; -} - -static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) -{ - CPUArchId apic_id, *found_cpu; - - apic_id.arch_id =3D id; - found_cpu =3D bsearch(&apic_id, ms->possible_cpus->cpus, - ms->possible_cpus->len, - sizeof(*ms->possible_cpus->cpus), - archid_cmp); - - return found_cpu; + return ipi_a->arch_id - ipi_b->arch_id; } =20 static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, int64_t arch_id, int *index, CPUState = **pcs) { - MachineState *machine =3D MACHINE(qdev_get_machine()); - CPUArchId *archid; - CPUState *cs; + IPICore ipi, *found; =20 - archid =3D find_cpu_by_archid(machine, arch_id); - if (archid && archid->cpu) { - cs =3D archid->cpu; + ipi.arch_id =3D arch_id; + found =3D bsearch(&ipi, lics->cpu, lics->num_cpu, sizeof(IPICore), + loongarch_ipi_cmp); + if (found && found->cpu) { if (index) { - *index =3D cs->cpu_index; + *index =3D found - lics->cpu; } =20 if (pcs) { - *pcs =3D cs; + *pcs =3D found->cpu; } =20 return MEMTX_OK; --=20 2.43.5