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d="scan'208";a="37059667" IronPort-SDR: 67884d72_5tNmTEiehvwU790Bbbo0ZCrq384n9ENOkYAUP6NOOBMGNSc SE7L0jwxhg3mAhTzpxHYg9lMNZGlAMiQtwu0/Ow== WDCIronportException: Internal To: qemu-devel@nongnu.org, qemu-block@nongnu.org Cc: alistair.francis@wdc.com, kbusch@kernel.org, its@irrelevant.dk, foss@defmacro.it, stefanha@redhat.com, fam@euphon.net, philmd@linaro.org, kwolf@redhat.com, hreitz@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com, Wilfred Mallawa Subject: [RFC v2 3/3] hw/nvme: connect SPDM over NVMe Security Send/Recv Date: Thu, 16 Jan 2025 11:08:57 +1000 Message-ID: <20250116010856.95115-5-wilfred.mallawa@wdc.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250116010856.95115-2-wilfred.mallawa@wdc.com> References: <20250116010856.95115-2-wilfred.mallawa@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=104bc4e84=wilfred.mallawa@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Wilfred Mallawa From: Wilfred Mallawa via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1736989816394019000 Content-Type: text/plain; charset="utf-8" This patch extends the existing support we have for NVMe with only DoE to also add support to SPDM over the NVMe Security Send/Recv commands. With the new definition of the `spdm-trans` argument, users can specify `spdm_trans=3Dnvme` or `spdm_trans=3Ddoe`. This allows us to select the SPDM transport respectively. SPDM over the NVMe Security Send/Recv commands are defined in the DMTF DSP0286. Signed-off-by: Wilfred Mallawa --- docs/specs/spdm.rst | 10 ++++-- hw/nvme/ctrl.c | 62 ++++++++++++++++++++++++++++++------- include/hw/pci/pci_device.h | 1 + 3 files changed, 60 insertions(+), 13 deletions(-) diff --git a/docs/specs/spdm.rst b/docs/specs/spdm.rst index f7de080ff0..dd6cfbbd68 100644 --- a/docs/specs/spdm.rst +++ b/docs/specs/spdm.rst @@ -98,7 +98,7 @@ Then you can add this to your QEMU command line: .. code-block:: shell =20 -drive file=3Dblknvme,if=3Dnone,id=3Dmynvme,format=3Draw \ - -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323 + -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323,spd= m_trans=3Ddoe =20 At which point QEMU will try to connect to the SPDM server. =20 @@ -113,7 +113,13 @@ of the default. So the entire QEMU command might look = like this -append "root=3D/dev/vda console=3DttyS0" \ -net none -nographic \ -drive file=3Dblknvme,if=3Dnone,id=3Dmynvme,format=3Draw \ - -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323 + -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323,spd= m_trans=3Ddoe + +The `spdm_trans` argument defines the underlying transport type that is em= ulated +by QEMU. For an PCIe NVMe controller, both "doe" and "nvme" are supported.= Where, +"doe" does SPDM transport over the PCIe extended capability Data Object Ex= change +(DOE), and "nvme" uses the NVMe Admin Security Send/Receive commands to +implement the SPDM transport. =20 .. _DMTF: https://www.dmtf.org/standards/SPDM diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index cc0a0f8bfb..653f364d88 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8742,6 +8742,23 @@ static DOEProtocol doe_spdm_prot[] =3D { { } }; =20 +static inline uint32_t nvme_get_spdm_trans_type(PCIDevice *pci_dev) +{ + if (!pci_dev) { + return false; + } + + if (!strcmp(pci_dev->spdm_trans, "nvme")) { + return SPDM_SOCKET_TRANSPORT_TYPE_NVME; + } + + if (!strcmp(pci_dev->spdm_trans, "doe")) { + return SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE; + } + + return 0; +} + static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { ERRP_GUARD(); @@ -8825,19 +8842,31 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev, Error **errp) =20 pcie_cap_deverr_init(pci_dev); =20 - /* DOE Initialisation */ + /* SPDM Initialisation */ if (pci_dev->spdm_port) { - uint16_t doe_offset =3D n->params.sriov_max_vfs ? - PCI_CONFIG_SPACE_SIZE + PCI_ARI_SIZEOF - : PCI_CONFIG_SPACE_SIZE; + switch (nvme_get_spdm_trans_type(pci_dev)) { + case SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE: + uint16_t doe_offset =3D n->params.sriov_max_vfs ? + PCI_CONFIG_SPACE_SIZE + PCI_ARI_SIZEOF + : PCI_CONFIG_SPACE_SIZE; =20 - pcie_doe_init(pci_dev, &pci_dev->doe_spdm, doe_offset, - doe_spdm_prot, true, 0); + pcie_doe_init(pci_dev, &pci_dev->doe_spdm, doe_offset, + doe_spdm_prot, true, 0); =20 - pci_dev->doe_spdm.spdm_socket =3D spdm_socket_connect(pci_dev->spd= m_port, - errp); + pci_dev->doe_spdm.spdm_socket =3D spdm_socket_connect( + pci_dev->spdm_port, errp); =20 - if (pci_dev->doe_spdm.spdm_socket < 0) { + if (pci_dev->doe_spdm.spdm_socket < 0) { + return false; + } + break; + case SPDM_SOCKET_TRANSPORT_TYPE_NVME: + n->spdm_socket =3D spdm_socket_connect(pci_dev->spdm_port, err= p); + if (n->spdm_socket < 0) { + return false; + } + break; + default: return false; } } @@ -9106,11 +9135,17 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cmb.buf); } =20 + /* Only one of the `spdm_socket` below would have been setup */ if (pci_dev->doe_spdm.spdm_socket > 0) { spdm_socket_close(pci_dev->doe_spdm.spdm_socket, SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE); } =20 + if (n->spdm_socket > 0) { + spdm_socket_close(pci_dev->doe_spdm.spdm_socket, + SPDM_SOCKET_TRANSPORT_TYPE_NVME); + } + if (n->pmr.dev) { host_memory_backend_set_mapped(n->pmr.dev, false); } @@ -9162,6 +9197,7 @@ static const Property nvme_props[] =3D { false), DEFINE_PROP_UINT16("mqes", NvmeCtrl, params.mqes, 0x7ff), DEFINE_PROP_UINT16("spdm_port", PCIDevice, spdm_port, 0), + DEFINE_PROP_STRING("spdm_trans", PCIDevice, spdm_trans), DEFINE_PROP_BOOL("ctratt.mem", NvmeCtrl, params.ctratt.mem, false), DEFINE_PROP_BOOL("atomic.dn", NvmeCtrl, params.atomic_dn, 0), DEFINE_PROP_UINT16("atomic.awun", NvmeCtrl, params.atomic_awun, 0), @@ -9236,7 +9272,9 @@ static void nvme_pci_write_config(PCIDevice *dev, uin= t32_t address, { uint16_t old_num_vfs =3D pcie_sriov_num_vfs(dev); =20 - if (pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + /* DOE is only initialised if SPDM over DOE is used */ + if (pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE) && + nvme_get_spdm_trans_type(dev) =3D=3D SPDM_SOCKET_TRANSPORT_TYPE_PC= I_DOE) { pcie_doe_write_config(&dev->doe_spdm, address, val, len); } pci_default_write_config(dev, address, val, len); @@ -9247,7 +9285,9 @@ static void nvme_pci_write_config(PCIDevice *dev, uin= t32_t address, static uint32_t nvme_pci_read_config(PCIDevice *dev, uint32_t address, int= len) { uint32_t val; - if (dev->spdm_port && pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + + if (dev->spdm_port && pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE) && + (nvme_get_spdm_trans_type(dev) =3D=3D SPDM_SOCKET_TRANSPORT_TYPE_P= CI_DOE)) { if (pcie_doe_read_config(&dev->doe_spdm, address, len, &val)) { return val; } diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index add208edfa..9ec66809d3 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -160,6 +160,7 @@ struct PCIDevice { =20 /* SPDM */ uint16_t spdm_port; + char *spdm_trans; =20 /* DOE */ DOECap doe_spdm; --=20 2.48.0