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d="scan'208";a="36036489" IronPort-SDR: 67884eae_KlBupYu34GYman1vMH9LAReNkN9sDIo1IgH+MR+8cKrpFUm RKqpZ5WYgvzMipG/WlsJQwKkaWc071lDa9h56Yg== WDCIronportException: Internal To: qemu-devel@nongnu.org, qemu-block@nongnu.org Cc: alistair.francis@wdc.com, kbusch@kernel.org, its@irrelevant.dk, foss@defmacro.it, stefanha@redhat.com, fam@euphon.net, philmd@linaro.org, kwolf@redhat.com, hreitz@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com, Wilfred Mallawa Subject: [RFC v2 1/3] spdm: add spdm storage transport virtual header Date: Thu, 16 Jan 2025 11:08:55 +1000 Message-ID: <20250116010856.95115-3-wilfred.mallawa@wdc.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250116010856.95115-2-wilfred.mallawa@wdc.com> References: <20250116010856.95115-2-wilfred.mallawa@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=104bc4e84=wilfred.mallawa@wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Wilfred Mallawa From: Wilfred Mallawa via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1736989811211019000 Content-Type: text/plain; charset="utf-8" This header contains the transport encoding for an SPDM message that uses the SPDM over Storage transport as defined by the DMTF DSP0286. Signed-off-by: Wilfred Mallawa --- include/system/spdm-socket.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/system/spdm-socket.h b/include/system/spdm-socket.h index 2b7d03f82d..fc007e5b48 100644 --- a/include/system/spdm-socket.h +++ b/include/system/spdm-socket.h @@ -88,6 +88,18 @@ bool spdm_socket_send(const int socket, uint32_t socket_= cmd, */ void spdm_socket_close(const int socket, uint32_t transport_type); =20 +/* + * Defines the transport encoding for SPDM, this information shall be pass= ed + * down to the SPDM server, when conforming to the SPDM over Storage stand= ard + * as defined by DSP0286. + */ +typedef struct QEMU_PACKED { + uint8_t security_protocol; + uint16_t security_protocol_specific; + bool inc_512; + uint32_t length; +} StorageSpdmTransportHeader; + #define SPDM_SOCKET_COMMAND_NORMAL 0x0001 #define SPDM_SOCKET_STORAGE_CMD_IF_SEND 0x0002 #define SPDM_SOCKET_STORAGE_CMD_IF_RECV 0x0003 --=20 2.48.0 From nobody Sun Apr 6 03:49:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="35419695" IronPort-SDR: 67884d6b_GIL4X8CjDg4+z8sMxLTKM+ZNT5nPuHFCqX4hAVVJw5rhY/5 noxfJHzTq0lfQc+s2g4o9lbjkZPFmDshT8qyPHw== WDCIronportException: Internal To: qemu-devel@nongnu.org, qemu-block@nongnu.org Cc: alistair.francis@wdc.com, kbusch@kernel.org, its@irrelevant.dk, foss@defmacro.it, stefanha@redhat.com, fam@euphon.net, philmd@linaro.org, kwolf@redhat.com, hreitz@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com, Wilfred Mallawa Subject: [RFC v2 2/3] hw/nvme: add NVMe Admin Security SPDM support Date: Thu, 16 Jan 2025 11:08:56 +1000 Message-ID: <20250116010856.95115-4-wilfred.mallawa@wdc.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250116010856.95115-2-wilfred.mallawa@wdc.com> References: <20250116010856.95115-2-wilfred.mallawa@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=104bc4e84=wilfred.mallawa@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Wilfred Mallawa From: Wilfred Mallawa via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1736989809167019000 Content-Type: text/plain; charset="utf-8" Adds the NVMe Admin Security Send/Receive command support with support for DMTFs SPDM. The transport binding for SPDM is defined in the DMTF DSP0286. Signed-off-by: Wilfred Mallawa --- hw/nvme/ctrl.c | 203 ++++++++++++++++++++++++++++++++++++++++++- hw/nvme/nvme.h | 5 ++ include/block/nvme.h | 15 ++++ 3 files changed, 222 insertions(+), 1 deletion(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 68903d1d70..cc0a0f8bfb 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -283,6 +283,8 @@ static const uint32_t nvme_cse_acs[256] =3D { [NVME_ADM_CMD_FORMAT_NVM] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, [NVME_ADM_CMD_DIRECTIVE_RECV] =3D NVME_CMD_EFF_CSUPP, [NVME_ADM_CMD_DIRECTIVE_SEND] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_SECURITY_SEND] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_SECURITY_RECV] =3D NVME_CMD_EFF_CSUPP, }; =20 static const uint32_t nvme_cse_iocs_none[256]; @@ -7182,6 +7184,201 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, cons= t NvmeRequest *req) return NVME_SUCCESS; } =20 +static uint16_t nvme_sec_prot_spdm_send(NvmeCtrl *n, NvmeRequest *req) +{ + StorageSpdmTransportHeader hdr =3D {0}; + uint8_t *sec_buf; + uint32_t transfer_len =3D le32_to_cpu(req->cmd.cdw11); + uint32_t transport_transfer_len =3D transfer_len; + uint32_t dw10 =3D le32_to_cpu(req->cmd.cdw10); + uint32_t recvd; + uint16_t nvme_cmd_status; + uint16_t ret; + uint8_t secp =3D (dw10 >> 24) & 0xFF; + uint8_t spsp1 =3D (dw10 >> 16) & 0xFF; + uint8_t spsp0 =3D (dw10 >> 8) & 0xFF; + bool spdm_res; + + transport_transfer_len +=3D sizeof(hdr); + if (transport_transfer_len > SPDM_SOCKET_MAX_MESSAGE_BUFFER_SIZE) { + return NVME_NO_COMPLETE | NVME_DNR; + } + + /* Generate the NVMe transport header */ + hdr.security_protocol =3D secp; + hdr.security_protocol_specific =3D cpu_to_le16((spsp1 << 8) | spsp0); + hdr.inc_512 =3D false; + hdr.length =3D cpu_to_le32(transport_transfer_len); + + sec_buf =3D g_malloc0(transport_transfer_len); + if (!sec_buf) { + return NVME_NO_COMPLETE | NVME_DNR; + } + + /* Attach the transport header */ + memcpy(sec_buf, &hdr, sizeof(hdr)); + ret =3D nvme_h2c(n, sec_buf + sizeof(hdr), transfer_len, req); + if (ret) { + return NVME_NO_COMPLETE | NVME_DNR; + } + + spdm_res =3D spdm_socket_send(n->spdm_socket, SPDM_SOCKET_STORAGE_CMD_= IF_SEND, + SPDM_SOCKET_TRANSPORT_TYPE_NVME, sec_buf, + transport_transfer_len); + if (!spdm_res) { + g_free(sec_buf); + return NVME_NO_COMPLETE | NVME_DNR; + } + + /* The responder shall ack with message status */ + recvd =3D spdm_socket_receive(n->spdm_socket, SPDM_SOCKET_TRANSPORT_TY= PE_NVME, + (uint8_t *)&nvme_cmd_status, + SPDM_SOCKET_MAX_MSG_STATUS_LEN); + + nvme_cmd_status =3D cpu_to_be16(nvme_cmd_status); + + if (recvd < SPDM_SOCKET_MAX_MSG_STATUS_LEN) { + g_free(sec_buf); + return NVME_NO_COMPLETE | NVME_DNR; + } + + g_free(sec_buf); + return nvme_cmd_status; +} + +/* From host to controller */ +static uint16_t nvme_security_send(NvmeCtrl *n, NvmeRequest *req) +{ + uint32_t dw10 =3D le32_to_cpu(req->cmd.cdw10); + uint8_t secp =3D (dw10 >> 24) & 0xff; + + switch (secp) { + case NVME_SEC_PROT_DMTF_SPDM: + return nvme_sec_prot_spdm_send(n, req); + default: + /* Unsupported Security Protocol Type */ + return NVME_INVALID_FIELD | NVME_DNR; + } + + return NVME_INVALID_FIELD | NVME_DNR; +} + +static uint16_t nvme_sec_prot_spdm_receive(NvmeCtrl *n, NvmeRequest *req) +{ + StorageSpdmTransportHeader hdr =3D {0}; + uint8_t *rsp_spdm_buf; + uint32_t dw10 =3D le32_to_cpu(req->cmd.cdw10); + uint32_t alloc_len =3D le32_to_cpu(req->cmd.cdw11); + uint32_t recvd, spdm_res; + uint16_t nvme_cmd_status; + uint16_t ret; + uint8_t secp =3D (dw10 >> 24) & 0xFF; + uint8_t spsp1 =3D (dw10 >> 16) & 0xFF; + uint8_t spsp0 =3D (dw10 >> 8) & 0xFF; + + if (!alloc_len) { + return NVME_INVALID_FIELD | NVME_DNR; + } + + /* Generate the NVMe transport header */ + hdr.security_protocol =3D secp; + hdr.security_protocol_specific =3D cpu_to_le16((spsp1 << 8) | spsp0); + hdr.inc_512 =3D false; + hdr.length =3D cpu_to_le32(alloc_len); + + /* Forward if_recv to the SPDM Server with SPSP0 */ + spdm_res =3D spdm_socket_send(n->spdm_socket, SPDM_SOCKET_STORAGE_CMD_= IF_RECV, + SPDM_SOCKET_TRANSPORT_TYPE_NVME, + (uint8_t *)&hdr, sizeof(hdr)); + if (!spdm_res) { + return NVME_NO_COMPLETE | NVME_DNR; + } + + /* The responder shall ack with message status */ + recvd =3D spdm_socket_receive(n->spdm_socket, SPDM_SOCKET_TRANSPORT_TY= PE_NVME, + (uint8_t *)&nvme_cmd_status, + SPDM_SOCKET_MAX_MSG_STATUS_LEN); + + nvme_cmd_status =3D cpu_to_be16(nvme_cmd_status); + + + if (recvd < SPDM_SOCKET_MAX_MSG_STATUS_LEN) { + return NVME_NO_COMPLETE | NVME_DNR; + } + + /* An error here implies the prior if_recv from requester was spurious= */ + if (nvme_cmd_status !=3D NVME_SUCCESS) { + return nvme_cmd_status; + } + + /* Clear to start receiving data from the server */ + rsp_spdm_buf =3D g_malloc0(alloc_len); + if (!rsp_spdm_buf) { + return NVME_NO_COMPLETE | NVME_DNR; + } + + recvd =3D spdm_socket_receive(n->spdm_socket, + SPDM_SOCKET_TRANSPORT_TYPE_NVME, + rsp_spdm_buf, alloc_len); + if (!recvd) { + g_free(rsp_spdm_buf); + return NVME_NO_COMPLETE | NVME_DNR; + } + + ret =3D nvme_c2h(n, rsp_spdm_buf, MIN(recvd, alloc_len), req); + g_free(rsp_spdm_buf); + + if (ret) { + return NVME_NO_COMPLETE | NVME_DNR; + } + + return NVME_SUCCESS; +} + +static uint16_t nvme_get_sec_prot_info(NvmeCtrl *n, NvmeRequest *req) +{ + uint32_t alloc_len =3D le32_to_cpu(req->cmd.cdw11); + uint8_t resp[10] =3D {0}; + + if (alloc_len < 10) { + return NVME_INVALID_FIELD | NVME_DNR; + } + + /* Support Security Protol List Length */ + resp[6] =3D 0; /* MSB */ + resp[7] =3D 2; /* LSB */ + /* Support Security Protocol List */ + resp[8] =3D SFSC_SECURITY_PROT_INFO; + resp[9] =3D NVME_SEC_PROT_DMTF_SPDM; + + return nvme_c2h(n, resp, sizeof(resp), req); +} + +/* From controller to host */ +static uint16_t nvme_security_receive(NvmeCtrl *n, NvmeRequest *req) +{ + uint32_t dw10 =3D le32_to_cpu(req->cmd.cdw10); + uint16_t spsp =3D (dw10 >> 8) & 0xFFFF; + uint8_t secp =3D (dw10 >> 24) & 0xFF; + + switch (secp) { + case SFSC_SECURITY_PROT_INFO: + switch (spsp) { + case 0: + /* Supported security protocol list */ + return nvme_get_sec_prot_info(n, req); + case 1: + /* Certificate data */ + default: + return NVME_INVALID_FIELD | NVME_DNR; + } + case NVME_SEC_PROT_DMTF_SPDM: + return nvme_sec_prot_spdm_receive(n, req); + default: + return NVME_INVALID_FIELD | NVME_DNR; + } +} + static uint16_t nvme_directive_send(NvmeCtrl *n, NvmeRequest *req) { return NVME_INVALID_FIELD | NVME_DNR; @@ -7289,6 +7486,10 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequ= est *req) return nvme_directive_send(n, req); case NVME_ADM_CMD_DIRECTIVE_RECV: return nvme_directive_receive(n, req); + case NVME_ADM_CMD_SECURITY_SEND: + return nvme_security_send(n, req); + case NVME_ADM_CMD_SECURITY_RECV: + return nvme_security_receive(n, req); default: g_assert_not_reached(); } @@ -8708,7 +8909,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) id->ver =3D cpu_to_le32(NVME_SPEC_VER); id->oacs =3D cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT | NVME_OACS_DBBUF= | - NVME_OACS_DIRECTIVES); + NVME_OACS_DIRECTIVES | NVME_OACS_SECURITY); id->cntrltype =3D 0x1; =20 /* diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 7242206910..c8ad20ee34 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -459,6 +459,8 @@ static inline const char *nvme_adm_opc_str(uint8_t opc) case NVME_ADM_CMD_DIRECTIVE_RECV: return "NVME_ADM_CMD_DIRECTIVE_REC= V"; case NVME_ADM_CMD_DBBUF_CONFIG: return "NVME_ADM_CMD_DBBUF_CONFIG"; case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM"; + case NVME_ADM_CMD_SECURITY_SEND: return "NVME_ADM_CMD_SECURITY_SEND= "; + case NVME_ADM_CMD_SECURITY_RECV: return "NVME_ADM_CMD_SECURITY_RECV= "; default: return "NVME_ADM_CMD_UNKNOWN"; } } @@ -636,6 +638,9 @@ typedef struct NvmeCtrl { } next_pri_ctrl_cap; /* These override pri_ctrl_cap after reset */ uint32_t dn; /* Disable Normal */ NvmeAtomic atomic; + + /* Socket mapping to SPDM over NVMe Security In/Out commands */ + int spdm_socket; } NvmeCtrl; =20 typedef enum NvmeResetType { diff --git a/include/block/nvme.h b/include/block/nvme.h index f4d108841b..e2352cfb1e 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -1733,6 +1733,21 @@ enum NvmeDirectiveOperations { NVME_DIRECTIVE_RETURN_PARAMS =3D 0x1, }; =20 +typedef enum SfscSecurityProtocol { + SFSC_SECURITY_PROT_INFO =3D 0x00, +} SfscSecurityProtocol; + +typedef enum NvmeSecurityProtocols { + NVME_SEC_PROT_DMTF_SPDM =3D 0xE8, +} NvmeSecurityProtocols; + +typedef enum SpdmOperationCodes { + SPDM_STORAGE_DISCOVERY =3D 0x1, /* Mandatory */ + SPDM_STORAGE_PENDING_INFO =3D 0x2, /* Optional */ + SPDM_STORAGE_MSG =3D 0x5, /* Mandatory */ + SPDM_STORAGE_SEC_MSG =3D 0x6, /* Optional */ +} SpdmOperationCodes; + typedef struct QEMU_PACKED NvmeFdpConfsHdr { uint16_t num_confs; uint8_t version; --=20 2.48.0 From nobody Sun Apr 6 03:49:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1736989814; cv=none; d=zohomail.com; s=zohoarc; b=AQIAcD8PmKtIPf3wo1UoPlvMoYSBKhNJQkAhbCpq2OkAM79AP745h4kExeypHCkhlbhgp30GUggJ3cnzy9IDFHzOUfmYxUeD3DJbmRWPMdMMpAolsQYx4Wjl6F0Kdwkju87uOPmvTljgQ2/fIC+G98GYIrXPe1XEU4c9Ko5RTog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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charset="utf-8" This patch extends the existing support we have for NVMe with only DoE to also add support to SPDM over the NVMe Security Send/Recv commands. With the new definition of the `spdm-trans` argument, users can specify `spdm_trans=3Dnvme` or `spdm_trans=3Ddoe`. This allows us to select the SPDM transport respectively. SPDM over the NVMe Security Send/Recv commands are defined in the DMTF DSP0286. Signed-off-by: Wilfred Mallawa --- docs/specs/spdm.rst | 10 ++++-- hw/nvme/ctrl.c | 62 ++++++++++++++++++++++++++++++------- include/hw/pci/pci_device.h | 1 + 3 files changed, 60 insertions(+), 13 deletions(-) diff --git a/docs/specs/spdm.rst b/docs/specs/spdm.rst index f7de080ff0..dd6cfbbd68 100644 --- a/docs/specs/spdm.rst +++ b/docs/specs/spdm.rst @@ -98,7 +98,7 @@ Then you can add this to your QEMU command line: .. code-block:: shell =20 -drive file=3Dblknvme,if=3Dnone,id=3Dmynvme,format=3Draw \ - -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323 + -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323,spd= m_trans=3Ddoe =20 At which point QEMU will try to connect to the SPDM server. =20 @@ -113,7 +113,13 @@ of the default. So the entire QEMU command might look = like this -append "root=3D/dev/vda console=3DttyS0" \ -net none -nographic \ -drive file=3Dblknvme,if=3Dnone,id=3Dmynvme,format=3Draw \ - -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323 + -device nvme,drive=3Dmynvme,serial=3Ddeadbeef,spdm_port=3D2323,spd= m_trans=3Ddoe + +The `spdm_trans` argument defines the underlying transport type that is em= ulated +by QEMU. For an PCIe NVMe controller, both "doe" and "nvme" are supported.= Where, +"doe" does SPDM transport over the PCIe extended capability Data Object Ex= change +(DOE), and "nvme" uses the NVMe Admin Security Send/Receive commands to +implement the SPDM transport. =20 .. _DMTF: https://www.dmtf.org/standards/SPDM diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index cc0a0f8bfb..653f364d88 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8742,6 +8742,23 @@ static DOEProtocol doe_spdm_prot[] =3D { { } }; =20 +static inline uint32_t nvme_get_spdm_trans_type(PCIDevice *pci_dev) +{ + if (!pci_dev) { + return false; + } + + if (!strcmp(pci_dev->spdm_trans, "nvme")) { + return SPDM_SOCKET_TRANSPORT_TYPE_NVME; + } + + if (!strcmp(pci_dev->spdm_trans, "doe")) { + return SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE; + } + + return 0; +} + static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { ERRP_GUARD(); @@ -8825,19 +8842,31 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev, Error **errp) =20 pcie_cap_deverr_init(pci_dev); =20 - /* DOE Initialisation */ + /* SPDM Initialisation */ if (pci_dev->spdm_port) { - uint16_t doe_offset =3D n->params.sriov_max_vfs ? - PCI_CONFIG_SPACE_SIZE + PCI_ARI_SIZEOF - : PCI_CONFIG_SPACE_SIZE; + switch (nvme_get_spdm_trans_type(pci_dev)) { + case SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE: + uint16_t doe_offset =3D n->params.sriov_max_vfs ? + PCI_CONFIG_SPACE_SIZE + PCI_ARI_SIZEOF + : PCI_CONFIG_SPACE_SIZE; =20 - pcie_doe_init(pci_dev, &pci_dev->doe_spdm, doe_offset, - doe_spdm_prot, true, 0); + pcie_doe_init(pci_dev, &pci_dev->doe_spdm, doe_offset, + doe_spdm_prot, true, 0); =20 - pci_dev->doe_spdm.spdm_socket =3D spdm_socket_connect(pci_dev->spd= m_port, - errp); + pci_dev->doe_spdm.spdm_socket =3D spdm_socket_connect( + pci_dev->spdm_port, errp); =20 - if (pci_dev->doe_spdm.spdm_socket < 0) { + if (pci_dev->doe_spdm.spdm_socket < 0) { + return false; + } + break; + case SPDM_SOCKET_TRANSPORT_TYPE_NVME: + n->spdm_socket =3D spdm_socket_connect(pci_dev->spdm_port, err= p); + if (n->spdm_socket < 0) { + return false; + } + break; + default: return false; } } @@ -9106,11 +9135,17 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cmb.buf); } =20 + /* Only one of the `spdm_socket` below would have been setup */ if (pci_dev->doe_spdm.spdm_socket > 0) { spdm_socket_close(pci_dev->doe_spdm.spdm_socket, SPDM_SOCKET_TRANSPORT_TYPE_PCI_DOE); } =20 + if (n->spdm_socket > 0) { + spdm_socket_close(pci_dev->doe_spdm.spdm_socket, + SPDM_SOCKET_TRANSPORT_TYPE_NVME); + } + if (n->pmr.dev) { host_memory_backend_set_mapped(n->pmr.dev, false); } @@ -9162,6 +9197,7 @@ static const Property nvme_props[] =3D { false), DEFINE_PROP_UINT16("mqes", NvmeCtrl, params.mqes, 0x7ff), DEFINE_PROP_UINT16("spdm_port", PCIDevice, spdm_port, 0), + DEFINE_PROP_STRING("spdm_trans", PCIDevice, spdm_trans), DEFINE_PROP_BOOL("ctratt.mem", NvmeCtrl, params.ctratt.mem, false), DEFINE_PROP_BOOL("atomic.dn", NvmeCtrl, params.atomic_dn, 0), DEFINE_PROP_UINT16("atomic.awun", NvmeCtrl, params.atomic_awun, 0), @@ -9236,7 +9272,9 @@ static void nvme_pci_write_config(PCIDevice *dev, uin= t32_t address, { uint16_t old_num_vfs =3D pcie_sriov_num_vfs(dev); =20 - if (pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + /* DOE is only initialised if SPDM over DOE is used */ + if (pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE) && + nvme_get_spdm_trans_type(dev) =3D=3D SPDM_SOCKET_TRANSPORT_TYPE_PC= I_DOE) { pcie_doe_write_config(&dev->doe_spdm, address, val, len); } pci_default_write_config(dev, address, val, len); @@ -9247,7 +9285,9 @@ static void nvme_pci_write_config(PCIDevice *dev, uin= t32_t address, static uint32_t nvme_pci_read_config(PCIDevice *dev, uint32_t address, int= len) { uint32_t val; - if (dev->spdm_port && pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE)) { + + if (dev->spdm_port && pcie_find_capability(dev, PCI_EXT_CAP_ID_DOE) && + (nvme_get_spdm_trans_type(dev) =3D=3D SPDM_SOCKET_TRANSPORT_TYPE_P= CI_DOE)) { if (pcie_doe_read_config(&dev->doe_spdm, address, len, &val)) { return val; } diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index add208edfa..9ec66809d3 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -160,6 +160,7 @@ struct PCIDevice { =20 /* SPDM */ uint16_t spdm_port; + char *spdm_trans; =20 /* DOE */ DOECap doe_spdm; --=20 2.48.0