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([191.202.238.10]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2ad80a5cb64sm6539196fac.47.2025.01.15.10.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 10:43:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1736966630; x=1737571430; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pwz4467PZxHOYDvJKbfek9VW1OADl098umRJuhCniXA=; b=Q2ZfY1g+SM+pjUSUUBbupGxSK3LKtEYQFx+0nFJVQDqynS2bzJAL3RCqFgDuY3P2Pd 76bEthNEXKg9yNlVFDDITjhTRwgz4kPEskjYmwQNSd3w+Vev1X7T5IRsaxKGuHRmpVYA HMojdjO+17LcJV6oUlX+4v9KJX/8A22vQc380f0Vr71+grWRKZbosCCfCUIssVZ6JG19 ffAeGLT+lrGpmjn55blJ0sOtUZCkbFbbPRRkwNr6j9N8CLNz/Hl3y0G3zle8gyTAT3w5 kjZMOKOzphKoCOILKqX13zedd7xLxnS2FPFeaV5qSHEknPe+Le1MCJwKex8EIWVPhD+v qa1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736966630; x=1737571430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pwz4467PZxHOYDvJKbfek9VW1OADl098umRJuhCniXA=; b=UqInKgdqRwE+lQKRAjWjr5ZqNkHUlhuVL/V3JrZ6ru3RCWHTHnFZpGxRpNc7D6ZTvZ +Plx83ksl78DmU632gl6Ps8k3egYljdFJc8VzbfDFhetJqREdBdzXB0QXeFiztT14VFg UWbkNnGPlLZGWI6n6d96pp0nOvgNB/qsft+8PDedb3hJLfFXR6ooK4GsNGUinO1GVJqM AmbMaj395+Zcw2WtS4Q2nD6vkV0hhDI83s8NODi9pP4G+IFKdenYWLIg4846acguJCAZ IjnkhrhRxThbHWsIpd0uclxr+1G3JxIThEJLUrzyBrWnVtI4KOtnc/BWcmPTZSfE6mBP mFFQ== X-Gm-Message-State: AOJu0YzKGLf+V1QwJ8BS77Mlltop4jokQcrIvbGLLGCPSyvClSOVVmyx hLf26frirhdMuidV5LN0PgdLKYyGmOa19ufoPCiyrK+ScuDswAlVgRGWJLkEgyE0TvivPBUMfNN xso7MUw== X-Gm-Gg: ASbGncveCZA5eZycDZ0uxP/8povkLuqftDJe3dkH5CVQLAnpQiSuJllmhy2Rj28bpxK +v4qYwxIxzcwDuH1ewtjM1caJSGlIypydYz+YBawZJUlSJm8aiepoJ03O2RTu0s8zGHvOBWK6V4 4Ob7HgDZa8YDaci5YIa8qt2ZSbmD7QL6e5ifr/gqAEu7LtIzChlDVSNMmbqhSacK5n89OwpKPwY uc7cqfalLHa3xRur4HyD9Gqyj4i6RgmKG6gJuodRYFxJU6pMKMhUAHjYv4= X-Google-Smtp-Source: AGHT+IExPfSCpjv+BifQlO2WaKYlA4Jl7zofx7iOkOjuPVFZkUbpLf8AaKlaAQp3JSsa5XIMNB3ijQ== X-Received: by 2002:a05:6870:af85:b0:297:2719:deb6 with SMTP id 586e51a60fabf-2aa0664faebmr16189172fac.1.1736966629842; Wed, 15 Jan 2025 10:43:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 6/6] target/riscv: add RVA23S64 profile Date: Wed, 15 Jan 2025 15:43:16 -0300 Message-ID: <20250115184316.2344583-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250115184316.2344583-1-dbarboza@ventanamicro.com> References: <20250115184316.2344583-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c44; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc44.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1736966706485019000 Content-Type: text/plain; charset="utf-8" Add RVA23S64 as described in [1]. This profile inherits all mandatory extensions of RVA23U64 and RVA22S64, making it a child of both profiles. A new "rva23s64" profile CPU is also added. This is the generated riscv,isa for it (taken via -M dumpdtb): rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_ zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_ zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_shcounterenw_ sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smnpm_smstateen_ssccptr_ sscofpmf_sscounterenw_ssnpm_ssstateen_sstc_sstvala_sstvecd_ssu64xl_ supm_svade_svinval_svnapot_svpbmt [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 53ead481a9..4cfdb74891 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -41,6 +41,7 @@ #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") +#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 761da41e53..adfce231a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2421,10 +2421,41 @@ static RISCVCPUProfile RVA23U64 =3D { } }; =20 +/* + * As with RVA23U64, RVA23S64 also defines 'named features'. + * + * Cache related features that we consider enabled since we don't + * implement cache: Ssccptr + * + * Other named features that we already implement: Sstvecd, Sstvala, + * Sscounterenw, Ssu64xl + * + * The remaining features/extensions comes from RVA23S64. + */ +static RISCVCPUProfile RVA23S64 =3D { + .u_parent =3D &RVA23U64, + .s_parent =3D &RVA22S64, + .name =3D "rva23s64", + .misa_ext =3D RVS, + .priv_spec =3D PRIV_VERSION_1_13_0, + .satp_mode =3D VM_1_10_SV39, + .ext_offsets =3D { + /* New in RVA23S64 */ + CPU_CFG_OFFSET(ext_svnapot), CPU_CFG_OFFSET(ext_sstc), + CPU_CFG_OFFSET(ext_sscofpmf), CPU_CFG_OFFSET(ext_ssnpm), + + /* Named features: Sha */ + CPU_CFG_OFFSET(ext_sha), + + RISCV_PROFILE_EXT_LIST_END + } +}; + RISCVCPUProfile *riscv_profiles[] =3D { &RVA22U64, &RVA22S64, &RVA23U64, + &RVA23S64, NULL, }; =20 @@ -2918,6 +2949,13 @@ static void rva23u64_profile_cpu_init(Object *obj) =20 RVA23U64.enabled =3D true; } + +static void rva23s64_profile_cpu_init(Object *obj) +{ + rv64i_bare_cpu_init(obj); + + RVA23S64.enabled =3D true; +} #endif =20 static const gchar *riscv_gdb_arch_name(CPUState *cs) @@ -3198,6 +3236,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profi= le_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profi= le_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64, rva23s64_profi= le_cpu_init), #endif /* TARGET_RISCV64 */ }; =20 --=20 2.47.1