From nobody Tue Dec 23 16:22:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1736756807715234.55956010504178; Mon, 13 Jan 2025 00:26:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tXFmW-0002ng-09; Mon, 13 Jan 2025 03:26:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tXFly-0002OI-AH for qemu-devel@nongnu.org; Mon, 13 Jan 2025 03:26:12 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tXFlu-0002TI-FQ for qemu-devel@nongnu.org; Mon, 13 Jan 2025 03:26:09 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxG+IZzoRnZ2tiAA--.61516S3; Mon, 13 Jan 2025 16:26:01 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx78cVzoRngBAgAA--.63355S7; Mon, 13 Jan 2025 16:26:00 +0800 (CST) From: Bibo Mao To: Song Gao Cc: qemu-devel@nongnu.org Subject: [PATCH 5/5] target/loongarch: Dump all generic CSR registers Date: Mon, 13 Jan 2025 16:25:57 +0800 Message-Id: <20250113082557.2926009-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250113082557.2926009-1-maobibo@loongson.cn> References: <20250113082557.2926009-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx78cVzoRngBAgAA--.63355S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1736756808337019000 Content-Type: text/plain; charset="utf-8" CSR registers is import system control registers, it had better dump all CSR registers when VM is running in system mode. Here is dump output example of CSR registers: CSR000: CRMD b4 PRMD 4 EUEN 0 MISC 0 CSR004: ECFG 71c3d ESTAT 0 ERA 9000000002e214c0 BADV 7ffff361401c CSR008: BADI 2b0000 CSR012: EENTRY 9000000005680000 CSR016: TLBIDX e0003c2 TLBEHI 7ffff3610000 TLBELO0 0 TLBELO1 40000001111d8= 01f CSR024: ASID a00ce PGDL 9000000105f1c000 PGDH 9000000005650000 PGD 0 CSR028: PWCL 5e56e PWCH 2e4 STLBPS e RVACFG 0 CSR032: CPUID 0 PRCFG1 72f8 PRCFG2 3ffff000 PRCFG3 8073f2 CSR048: SAVE0 0 SAVE1 1b504 SAVE2 7ffff34487a8 SAVE3 5e24000 CSR052: SAVE4 0 SAVE5 0 SAVE6 0 SAVE7 0 CSR056: SAVE8 0 SAVE9 0 SAVE10 0 SAVE11 0 CSR060: SAVE12 0 SAVE13 0 SAVE14 0 SAVE15 0 CSR064: TID 0 TCFG 50b06f5 TVAL 20ab7cf CNTC ffffffffce390f8f CSR068: TICLR 0 CSR096: LLBCTL 1 CSR128: IMPCTL1 0 IMPCTL2 0 CSR136: TLBRENTRY 568a000 TLBRBADV ffff8000021143f8 TLBRERA 90000000039999= 30 TLBRSAVE 9000000101684a00 CSR140: TLBRELO0 40 TLBRELO1 10942c053 TLBREHI ffff80000211400e TLBRPRMD 4 CSR144: MERRCTL 0 MERRINFO1 0 MERRINFO2 0 MERRENTRY 0 CSR148: MERRERA 0 MERRSAVE 0 CSR152: CTAG 0 CSR384: DMW0 8000000000000001 DMW1 9000000000000011 DMW2 a000000000000021 = DMW3 0 Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 58 +++++++++++++++++++++++++++++------------- target/loongarch/csr.c | 2 ++ target/loongarch/csr.h | 1 + 3 files changed, 44 insertions(+), 17 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d611a60470..31ef82cfe8 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -19,7 +19,7 @@ #include "cpu.h" #include "internals.h" #include "fpu/softfloat-helpers.h" -#include "cpu-csr.h" +#include "csr.h" #ifndef CONFIG_USER_ONLY #include "system/reset.h" #endif @@ -765,6 +765,44 @@ static ObjectClass *loongarch_cpu_class_by_name(const = char *cpu_model) return oc; } =20 +static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f) +{ +#ifndef CONFIG_USER_ONLY + int i; + CSRInfo *csr_info; + CPULoongArchState *env =3D cpu_env(cs); + unsigned long *addr; + int col =3D 0; + + qemu_fprintf(f, "\n"); + + /* Dump all generic CSR register */ + for (i =3D 0; i < LOONGARCH_CSR_DBG; i++) { + csr_info =3D get_csr(i); + if (!csr_info) { + if (i =3D=3D (col + 3)) { + qemu_fprintf(f, "\n"); + } + + continue; + } + + if ((i > (col + 3)) || (i =3D=3D col)) { + col =3D i & ~3; + qemu_fprintf(f, " CSR%03d:", col); + } + + addr =3D (void *)env + csr_info->offset; + qemu_fprintf(f, " %s %" PRIx64, csr_info->name, *addr); + + if (i =3D=3D (col + 3)) { + qemu_fprintf(f, "\n"); + } + } + qemu_fprintf(f, "\n"); +#endif +} + static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) { CPULoongArchState *env =3D cpu_env(cs); @@ -784,22 +822,8 @@ static void loongarch_cpu_dump_state(CPUState *cs, FIL= E *f, int flags) } } =20 - qemu_fprintf(f, "CRMD=3D%016" PRIx64 "\n", env->CSR_CRMD); - qemu_fprintf(f, "PRMD=3D%016" PRIx64 "\n", env->CSR_PRMD); - qemu_fprintf(f, "EUEN=3D%016" PRIx64 "\n", env->CSR_EUEN); - qemu_fprintf(f, "ESTAT=3D%016" PRIx64 "\n", env->CSR_ESTAT); - qemu_fprintf(f, "ERA=3D%016" PRIx64 "\n", env->CSR_ERA); - qemu_fprintf(f, "BADV=3D%016" PRIx64 "\n", env->CSR_BADV); - qemu_fprintf(f, "BADI=3D%016" PRIx64 "\n", env->CSR_BADI); - qemu_fprintf(f, "EENTRY=3D%016" PRIx64 "\n", env->CSR_EENTRY); - qemu_fprintf(f, "PRCFG1=3D%016" PRIx64 ", PRCFG2=3D%016" PRIx64 "," - " PRCFG3=3D%016" PRIx64 "\n", - env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3); - qemu_fprintf(f, "TLBRENTRY=3D%016" PRIx64 "\n", env->CSR_TLBRENTRY); - qemu_fprintf(f, "TLBRBADV=3D%016" PRIx64 "\n", env->CSR_TLBRBADV); - qemu_fprintf(f, "TLBRERA=3D%016" PRIx64 "\n", env->CSR_TLBRERA); - qemu_fprintf(f, "TCFG=3D%016" PRIx64 "\n", env->CSR_TCFG); - qemu_fprintf(f, "TVAL=3D%016" PRIx64 "\n", env->CSR_TVAL); + /* csr */ + loongarch_cpu_dump_csr(cs, f); =20 /* fpr */ if (flags & CPU_DUMP_FPU) { diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c index 62c1815bfb..8ad6448c69 100644 --- a/target/loongarch/csr.c +++ b/target/loongarch/csr.c @@ -9,12 +9,14 @@ =20 #define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ [LOONGARCH_CSR_##NAME] =3D { \ + .name =3D (stringify(NAME)), \ .offset =3D offsetof(CPULoongArchState, CSR_##NAME), \ .flags =3D FL, .readfn =3D RD, .writefn =3D WR \ } =20 #define CSR_OFF_ARRAY(NAME, N) \ [LOONGARCH_CSR_##NAME(N)] =3D { \ + .name =3D (stringify(NAME##N)), \ .offset =3D offsetof(CPULoongArchState, CSR_##NAME[N]), \ .flags =3D 0, .readfn =3D NULL, .writefn =3D NULL \ } diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h index d32a607975..fba48258c8 100644 --- a/target/loongarch/csr.h +++ b/target/loongarch/csr.h @@ -26,6 +26,7 @@ enum { }; =20 typedef struct { + const char *name; int offset; int flags; GenCSRRead readfn; --=20 2.39.3