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Sun, 12 Jan 2025 14:20:02 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 31/49] hw/misc/imx6_src: Convert DPRINTF() to trace events Date: Sun, 12 Jan 2025 23:17:07 +0100 Message-ID: <20250112221726.30206-32-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250112221726.30206-1-philmd@linaro.org> References: <20250112221726.30206-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1736720696805019000 From: Bernhard Beschow Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20250108092538.11474-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/imx6_src.c | 23 +++++------------------ hw/misc/trace-events | 6 ++++++ 2 files changed, 11 insertions(+), 18 deletions(-) diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index dc6a2b92ba4..06cc46292ed 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -17,18 +17,7 @@ #include "qemu/module.h" #include "target/arm/arm-powerctl.h" #include "hw/core/cpu.h" - -#ifndef DEBUG_IMX6_SRC -#define DEBUG_IMX6_SRC 0 -#endif - -#define DPRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX6_SRC) { \ - fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX6_SRC, \ - __func__, ##args); \ - } \ - } while (0) +#include "trace.h" =20 static const char *imx6_src_reg_name(uint32_t reg) { @@ -87,7 +76,7 @@ static void imx6_src_reset(DeviceState *dev) { IMX6SRCState *s =3D IMX6_SRC(dev); =20 - DPRINTF("\n"); + trace_imx6_src_reset(); =20 memset(s->regs, 0, sizeof(s->regs)); =20 @@ -111,7 +100,7 @@ static uint64_t imx6_src_read(void *opaque, hwaddr offs= et, unsigned size) =20 } =20 - DPRINTF("reg[%s] =3D> 0x%" PRIx32 "\n", imx6_src_reg_name(index), valu= e); + trace_imx6_src_read(imx6_src_reg_name(index), value); =20 return value; } @@ -134,8 +123,7 @@ static void imx6_clear_reset_bit(CPUState *cpu, run_on_= cpu_data data) assert(bql_locked()); =20 s->regs[SRC_SCR] =3D deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0); - DPRINTF("reg[%s] <=3D 0x%" PRIx32 "\n", - imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]); + trace_imx6_clear_reset_bit(imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR= ]); =20 g_free(ri); } @@ -173,8 +161,7 @@ static void imx6_src_write(void *opaque, hwaddr offset,= uint64_t value, return; } =20 - DPRINTF("reg[%s] <=3D 0x%" PRIx32 "\n", imx6_src_reg_name(index), - (uint32_t)current_value); + trace_imx6_src_write(imx6_src_reg_name(index), value); =20 change_mask =3D s->regs[index] ^ (uint32_t)current_value; =20 diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 0f5d2b56660..cf1abe69285 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -253,6 +253,12 @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = =3D %d) =3D %d" ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <=3D 0x%" PRIx= 32 ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] =3D> 0x%" PRI= x32 =20 +# imx6_src.c +imx6_src_read(const char *reg_name, uint32_t value) "reg[%s] =3D> 0x%" PRI= x32 +imx6_src_write(const char *reg_name, uint64_t value) "reg[%s] <=3D 0x%" PR= Ix64 +imx6_clear_reset_bit(const char *reg_name, uint32_t value) "reg[%s] <=3D 0= x%" PRIx32 +imx6_src_reset(void) "" + # imx7_src.c imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] =3D> 0x%" PRI= x32 imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <=3D 0x%" PR= Ix32 --=20 2.47.1