From nobody Sun Apr 6 20:51:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1736519614; cv=none; d=zohomail.com; s=zohoarc; b=lCt96K4kfQqGoHKUL8jZEUx3UT1HBz4mC0hBYUnPbMnKWFqUsY1gx0XQjWcIH0xQwyRmV7HCyZyWoQRHgQUnWlwDUCdhSz7qWVjQkCgbHQiTAz0g9XJAUwVQOFTtfLEPmDLWD1GsSRrwTfS9OCyALccD83fDaunGye8ONyEXNho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1736519614; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=C5/ZrNgYwkrA2cnegC79B2mM57gDoBEhMQB39bI6wE4=; b=JSa4XQNOwRdgItspwPePENo7Vb8HgxmJ+vIj+Or//6RfB/sWqSfAyZVt4p6soVpGOVw9BzAcI15Dnw0MLUafAFUuAU/PMKvWu0ZXFe+ak7WQJ07XM0pCxYXB83I72CqwIvfp57dneWv+e5m52/Kyse/pCA1Oll5rRooviX+Obdg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1736519614790331.86556725546836; Fri, 10 Jan 2025 06:33:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWG4U-0002Ey-Sx; Fri, 10 Jan 2025 09:33:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWG4T-0002Ed-Js for qemu-devel@nongnu.org; Fri, 10 Jan 2025 09:33:09 -0500 Received: from mgamail.intel.com ([192.198.163.7]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWG4R-0006dZ-Nv for qemu-devel@nongnu.org; Fri, 10 Jan 2025 09:33:09 -0500 Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2025 06:33:07 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa003.jf.intel.com with ESMTP; 10 Jan 2025 06:33:02 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736519587; x=1768055587; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GKO6Z3A/2gq1cK4JeQY1dLFLS2g//H2In2c4J8sWf4w=; b=EFVkm2O19ncdZrD/HQxjppW1FDy1YXXtOKS9Y1prlrnoyVayQJROB4R5 PZ4EXTxUwd3dbbW2VB8jilkrkh2HibNLxF+Y0Cx86s/q8VNlJPAfXndf+ ezhlNyRlCkc81EGgw1qMFear/DosPEm7XMAzIE+35uL4Cp3EPNzHJszKR cdGB75ViDyGKwuVx5SRm+AE+tD7cIf6MmfZs7O13CIadZiVlhLftjBBIs Mhz006l+8qQ+W/Dl8TEvC3pTxH1PFaAqNWaqjKJuok8eUWtOyhPjnePke TOp9NeUk3SoCjkQ1x40zzuUxPtKHKkmzl7rf604CE2ZsqOkK7pLdaTlaU Q==; X-CSE-ConnectionGUID: c1+747RFS72sEoE2xSsT+g== X-CSE-MsgGUID: AfmidpzqTv6yjuiFG6PnHQ== X-IronPort-AV: E=McAfee;i="6700,10204,11311"; a="62185533" X-IronPort-AV: E=Sophos;i="6.12,303,1728975600"; d="scan'208";a="62185533" X-CSE-ConnectionGUID: Y1SdWWLcSFqJKrQcQ/dT4A== X-CSE-MsgGUID: KaeEoiZoTgekpe3lth96xg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="108790913" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Markus Armbruster , Igor Mammedov , "Michael S . Tsirkin" , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v7 RESEND 4/5] i386/pc: Support cache topology in -machine for PC machine Date: Fri, 10 Jan 2025 22:51:14 +0800 Message-Id: <20250110145115.1574345-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250110145115.1574345-1-zhao1.liu@intel.com> References: <20250110145115.1574345-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.432, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1736519615743116600 Content-Type: text/plain; charset="utf-8" Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- Changes since Patch v6: * Deleted the "thread" level from the allowed topology level parameters in the doc. Changes since Patch v3: * Described the omitting cache will use "default" level and described the default cache topology model of i386 PC machine. (Daniel) --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 30 +++++++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 53a2f226d038..b9b83d1936ae 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1797,6 +1797,10 @@ static void pc_machine_class_init(ObjectClass *oc, v= oid *data) mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; mc->smp_props.modules_supported =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] =3D true; mc->default_ram_id =3D "pc.ram"; pcmc->default_smbios_ep_type =3D SMBIOS_ENTRY_POINT_TYPE_AUTO; =20 diff --git a/qemu-options.hx b/qemu-options.hx index cc694d3b890c..60894fe2b52b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=3D@var{} memory encryption object t= o use (default=3Dnone)\n" " hmat=3Don|off controls ACPI HMAT support (default=3Do= ff)\n" " memory-backend=3D'backend-id' specifies explicitly pr= ovided backend for main RAM (default=3Dnone)\n" - " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n", + " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n" + " smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3D= topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=3D]name[,prop=3Dvalue[,...]]`` @@ -159,6 +160,33 @@ SRST :: =20 -machine cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl= .1,cxl-fmw.0.size=3D128G,cxl-fmw.0.interleave-granularity=3D512 + + ``smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3Dtopologylevel`` + Define cache properties for SMP system. + + ``cache=3Dcachename`` specifies the cache that the properties will= be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=3Dtopologylevel`` sets the cache topology level. It acc= epts + CPU topology levels including ``core``, ``module``, ``cluster``, `= `die``, + ``socket``, ``book``, ``drawer`` and a special value ``default``. = If + ``default`` is set, then the cache topology will follow the archit= ecture's + default cache topology model. If another topology level is set, th= e cache + will be shared at corresponding CPU topology level. For example, + ``topology=3Dcore`` makes the cache shared by all threads within a= core. + The omitting cache will default to using the ``default`` level. + + The default cache topology model for an i386 PC machine is as foll= ows: + ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``= l3`` + cache is per ``die``. + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dcore,s= mp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dcore ERST =20 DEF("M", HAS_ARG, QEMU_OPTION_M, --=20 2.34.1