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Thu, 09 Jan 2025 08:01:53 -0800 (PST) From: Craig Blackmore To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Craig Blackmore , Richard Henderson , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Helene Chelin , Nathan Egge , Max Chou , Paolo Savini Subject: [PATCH v10 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store Date: Thu, 9 Jan 2025 16:01:22 +0000 Message-ID: <20250109160122.129409-2-craig.blackmore@embecosm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250109160122.129409-1-craig.blackmore@embecosm.com> References: <20250109160122.129409-1-craig.blackmore@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=craig.blackmore@embecosm.com; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @embecosm.com) X-ZM-MESSAGEID: 1736438598918116600 Content-Type: text/plain; charset="utf-8" Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 95 +++++++++++++++++++++++++++++++++--- 1 file changed, 87 insertions(+), 8 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a85dd1d200..f9228270b1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -206,29 +206,108 @@ vext_continus_ldst_tlb(CPURISCVState *env, vext_ldst= _elem_fn_tlb *ldst_tlb, } } =20 +#if !HOST_BIG_ENDIAN +/* Atomic operations for load/store */ + +#define GEN_VEXT_LDST_ATOMIC_HOST(SIZE, TYPE) \ +static inline QEMU_ALWAYS_INLINE void \ +vext_ldst_atom_##SIZE##_host(void *vd, uint32_t byte_offset, TYPE *host, \ + bool is_load) \ +{ \ + TYPE *vd_ptr =3D (TYPE *) (vd + byte_offset); = \ + if (is_load) { \ + *vd_ptr =3D qatomic_read__nocheck(host); = \ + } else { \ + qatomic_set__nocheck(host, *vd_ptr); \ + } \ +} \ + +GEN_VEXT_LDST_ATOMIC_HOST(2, uint16_t) +GEN_VEXT_LDST_ATOMIC_HOST(4, uint32_t) +#ifdef CONFIG_ATOMIC64 +GEN_VEXT_LDST_ATOMIC_HOST(8, uint64_t) +#endif + +static inline QEMU_ALWAYS_INLINE void +vext_ldst_atom_16_host(void *vd, uint32_t byte_offset, Int128 *host, + bool is_load) +{ + Int128 *vd_ptr =3D (Int128 *) (vd + byte_offset); + if (is_load) { + *vd_ptr =3D atomic16_read_ro(host); + } else { + atomic16_set(host, *vd_ptr); + } +} +#endif + static inline QEMU_ALWAYS_INLINE void vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_h= ost, void *vd, uint32_t evl, uint32_t reg_start, void *= host, - uint32_t esz, bool is_load) + uint32_t esz, bool is_load, uint32_t log2_esz) { #if HOST_BIG_ENDIAN for (; reg_start < evl; reg_start++, host +=3D esz) { ldst_host(vd, reg_start, host); } #else - if (esz =3D=3D 1) { - uint32_t byte_offset =3D reg_start * esz; - uint32_t size =3D (evl - reg_start) * esz; + uint32_t size =3D (evl - reg_start) * esz; + uint32_t test =3D (uintptr_t) host; =20 + /* Misaligned load/stores do not require any atomicity */ + if (esz =3D=3D 1 || unlikely(test % esz !=3D 0)) { + uint32_t byte_offset =3D reg_start * esz; if (is_load) { memcpy(vd + byte_offset, host, size); } else { memcpy(host, vd + byte_offset, size); } - } else { - for (; reg_start < evl; reg_start++, host +=3D esz) { - ldst_host(vd, reg_start, host); + return; + } + + /* + * At this point esz > 1 and host is aligned to at least esz, so the l= dst + * can be completed in atomic chunks of at least esz if the atomic ope= ration + * is available. + */ + + /* Test that both alignment and size are multiples of the atomic width= . */ + test |=3D size; + + /* + * If !HAVE_ATOMIC128_RO, then atomic16_set may be implemented with a + * 16-byte compare and store loop, which is expensive, so prefer two 8= -byte + * stores in this case. + */ + if (HAVE_ATOMIC128_RO && (is_load || HAVE_ATOMIC128_RW) + && (test % 16 =3D=3D 0)) { + for (; reg_start < evl; reg_start +=3D 16 >> log2_esz, host +=3D 1= 6) { + vext_ldst_atom_16_host(vd, reg_start * esz, host, is_load); + } + return; + } +#ifdef CONFIG_ATOMIC64 + if (test % 8 =3D=3D 0) { + for (; reg_start < evl; reg_start +=3D 8 >> log2_esz, host +=3D 8)= { + vext_ldst_atom_8_host(vd, reg_start * esz, host, is_load); + } + return; + } +#endif + if (test % 4 =3D=3D 0) { + for (; reg_start < evl; reg_start +=3D 4 >> log2_esz, host +=3D 4)= { + vext_ldst_atom_4_host(vd, reg_start * esz, host, is_load); + } + return; + } + if (test % 2 =3D=3D 0) { + for (; reg_start < evl; reg_start +=3D 2 >> log2_esz, host +=3D 2)= { + vext_ldst_atom_2_host(vd, reg_start * esz, host, is_load); } + return; + } + for (; reg_start < evl; reg_start++, host +=3D esz) { + ldst_host(vd, reg_start, host); } #endif } @@ -343,7 +422,7 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target_= ulong addr, if (flags =3D=3D 0) { if (nf =3D=3D 1) { vext_continus_ldst_host(env, ldst_host, vd, evl, env->vstart, = host, - esz, is_load); + esz, is_load, log2_esz); } else { for (i =3D env->vstart; i < evl; ++i) { k =3D 0; --=20 2.43.0