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CC: <richard.henderson@linaro.org>, <pbonzini@redhat.com>,
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Ethan Chen <ethan84@andestech.com>
Subject: [PATCH v9 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for
transaction infomation
Date: Thu, 9 Jan 2025 10:44:38 +0800
Message-ID: <20250109024441.3283671-6-ethan84@andestech.com>
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The entire valid transaction must fit within a single IOPMP entry.
However, during IOMMU translation, the transaction size is not
available. This structure defines the transaction information required
by the IOPMP.
Signed-off-by: Ethan Chen <ethan84@andestech.com>
---
include/hw/misc/riscv_iopmp_txn_info.h | 38 ++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
diff --git a/include/hw/misc/riscv_iopmp_txn_info.h b/include/hw/misc/riscv=
_iopmp_txn_info.h
new file mode 100644
index 0000000000..98bd26b68b
--- /dev/null
+++ b/include/hw/misc/riscv_iopmp_txn_info.h
@@ -0,0 +1,38 @@
+/*
+ * QEMU RISC-V IOPMP transaction information
+ *
+ * The transaction information structure provides the complete transaction
+ * length to the IOPMP device
+ *
+ * Copyright (c) 2023-2025 Andes Tech. Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f=
or
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along=
with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_IOPMP_TXN_INFO_H
+#define RISCV_IOPMP_TXN_INFO_H
+
+typedef struct {
+ /* The id of requestor */
+ uint32_t rrid:16;
+ /* The start address of transaction */
+ uint64_t start_addr;
+ /* The end address of transaction */
+ uint64_t end_addr;
+ /* The stage of cascading IOPMP */
+ uint32_t stage;
+} riscv_iopmp_txn_info;
+
+#endif
--=20
2.34.1