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charset="utf-8" Signed-off-by: Ethan Chen Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 2 ++ target/riscv/cpu_helper.c | 18 +++++++++++++++--- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8d5120106..212e522ed7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2798,6 +2798,9 @@ static const Property riscv_cpu_properties[] =3D { * it with -x and default to 'false'. */ DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), + + DEFINE_PROP_BOOL("iopmp", RISCVCPU, cfg.iopmp, false), + DEFINE_PROP_UINT32("iopmp_rrid", RISCVCPU, cfg.iopmp_rrid, 0), }; =20 #if defined(TARGET_RISCV64) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index a1457ab4f4..c5d5e1a77d 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -175,6 +175,8 @@ struct RISCVCPUConfig { bool pmp; bool debug; bool misa_w; + bool iopmp; + uint32_t iopmp_rrid; =20 bool short_isa_string; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f62b21e182..926ae38684 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1599,9 +1599,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, } =20 if (ret =3D=3D TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), - prot, mmu_idx, tlb_size); - return true; + if (cpu->cfg.iopmp) { + /* + * Do not align address on early stage because IOPMP needs ori= gin + * address for permission check. + */ + tlb_set_page_with_attrs(cs, address, pa, + (MemTxAttrs) + { + .requester_id =3D cpu->cfg.iopmp= _rrid, + }, + prot, mmu_idx, tlb_size); + } else { + tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - = 1), + prot, mmu_idx, tlb_size); + } } else if (probe) { return false; } else { --=20 2.34.1