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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
pierrick.bouvier@linaro.org
Subject: [PATCH v2 75/81] tcg/arm: Fix constraints for sub
Date: Tue, 7 Jan 2025 00:01:06 -0800
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In 7536b82d288 we lost the rI constraint that allowed the use of
RSB to perform reg =3D imm - reg. At the same time, drop support
for reg =3D reg - imm, which is now transformed generically to
addition, and need not be handled by the backend.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-con-set.h | 1 +
tcg/arm/tcg-target.c.inc | 11 ++++-------
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index 229ae258ac..f46a8444fb 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -30,6 +30,7 @@ C_O1_I2(r, r, rI)
C_O1_I2(r, r, rIK)
C_O1_I2(r, r, rIN)
C_O1_I2(r, r, ri)
+C_O1_I2(r, rI, r)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, 0, w)
C_O1_I2(w, w, w)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 8e3448c7bd..52a1ca5a4e 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2010,12 +2010,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
break;
case INDEX_op_sub_i32:
if (const_args[1]) {
- if (const_args[2]) {
- tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]);
- } else {
- tcg_out_dat_rI(s, COND_AL, ARITH_RSB,
- args[0], args[2], args[1], 1);
- }
+ tcg_out_dat_imm(s, COND_AL, ARITH_RSB,
+ args[0], args[2], encode_imm_nofail(args[1]));
} else {
tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD,
args[0], args[1], args[2], const_args[2]);
@@ -2278,10 +2274,11 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsig=
ned flags)
case INDEX_op_st_i32:
return C_O0_I2(r, r);
=20
- case INDEX_op_sub_i32:
case INDEX_op_setcond_i32:
case INDEX_op_negsetcond_i32:
return C_O1_I2(r, r, rIN);
+ case INDEX_op_sub_i32:
+ return C_O1_I2(r, rI, r);
=20
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
--=20
2.43.0