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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org,
pierrick.bouvier@linaro.org
Subject: [PATCH v2 58/81] tcg: Convert andc to TCGOutOpBinary
Date: Tue, 7 Jan 2025 00:00:49 -0800
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At the same time, drop all backend support for immediate
operands, as we now transform andc to and during optimize.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-con-set.h | 2 +-
tcg/i386/tcg-target-has.h | 2 --
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/mips/tcg-target-has.h | 2 --
tcg/ppc/tcg-target-has.h | 2 --
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target-has.h | 2 --
tcg/s390x/tcg-target-con-set.h | 1 -
tcg/s390x/tcg-target-has.h | 2 --
tcg/sparc64/tcg-target-has.h | 2 --
tcg/tcg-has.h | 1 -
tcg/tci/tcg-target-has.h | 2 --
tcg/tcg-op.c | 4 +--
tcg/tcg.c | 8 +++---
tcg/tci.c | 2 --
tcg/aarch64/tcg-target.c.inc | 24 +++++++++---------
tcg/arm/tcg-target.c.inc | 16 ++++++++----
tcg/i386/tcg-target.c.inc | 31 +++++++++++++----------
tcg/loongarch64/tcg-target.c.inc | 23 +++++++++--------
tcg/mips/tcg-target.c.inc | 4 +++
tcg/ppc/tcg-target.c.inc | 29 +++++++++-------------
tcg/riscv/tcg-target.c.inc | 27 ++++++++++++--------
tcg/s390x/tcg-target.c.inc | 42 ++++++++++++++++----------------
tcg/sparc64/tcg-target.c.inc | 16 ++++++++----
tcg/tci/tcg-target.c.inc | 14 ++++++++---
27 files changed, 134 insertions(+), 130 deletions(-)
diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
index bfd587c0fc..851f6b01b4 100644
--- a/tcg/aarch64/tcg-target-has.h
+++ b/tcg/aarch64/tcg-target-has.h
@@ -19,7 +19,6 @@
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
@@ -45,7 +44,6 @@
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_rot_i64 1
-#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 0
diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h
index 8398c80c8e..0268858a3b 100644
--- a/tcg/arm/tcg-target-has.h
+++ b/tcg/arm/tcg-target-has.h
@@ -28,7 +28,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
index 06e6521001..0ae9775944 100644
--- a/tcg/i386/tcg-target-con-set.h
+++ b/tcg/i386/tcg-target-con-set.h
@@ -42,9 +42,9 @@ C_O1_I2(r, 0, reZ)
C_O1_I2(r, 0, ri)
C_O1_I2(r, 0, rI)
C_O1_I2(r, L, L)
+C_O1_I2(r, r, r)
C_O1_I2(r, r, re)
C_O1_I2(r, r, ri)
-C_O1_I2(r, r, rI)
C_O1_I2(x, x, x)
C_N1_I2(r, r, r)
C_N1_I2(r, r, rW)
diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h
index bbf55c86b6..b29b70357a 100644
--- a/tcg/i386/tcg-target-has.h
+++ b/tcg/i386/tcg-target-has.h
@@ -31,7 +31,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_andc_i32 have_bmi1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@@ -57,7 +56,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_andc_i64 have_bmi1
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-=
has.h
index 93885a9192..76d731abad 100644
--- a/tcg/loongarch64/tcg-target-has.h
+++ b/tcg/loongarch64/tcg-target-has.h
@@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@@ -49,7 +48,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
index fd96905484..6a6d4377e7 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -43,7 +43,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nor_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@@ -63,7 +62,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nor_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
index 9acfc574c5..63bb66f446 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -23,7 +23,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
@@ -50,7 +49,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
index 3c4ef44eb0..e98add0429 100644
--- a/tcg/riscv/tcg-target-con-set.h
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -13,6 +13,7 @@ C_O0_I1(r)
C_O0_I2(rZ, r)
C_O0_I2(rZ, rZ)
C_O1_I1(r, r)
+C_O1_I2(r, r, r)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index d4cd0fbc21..8d18c4d88a 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i32 0
@@ -48,7 +47,6 @@
#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i64 0
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 370e4b1295..39903a60ad 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -31,7 +31,6 @@ C_O1_I2(r, r, rC)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
C_O1_I2(r, r, rK)
-C_O1_I2(r, r, rKR)
C_O1_I2(r, r, rNK)
C_O1_I2(r, r, rNKR)
C_O1_I2(r, rZ, r)
diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h
index aea805455f..15ec0dc2ff 100644
--- a/tcg/s390x/tcg-target-has.h
+++ b/tcg/s390x/tcg-target-has.h
@@ -34,7 +34,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3)
-#define TCG_TARGET_HAS_andc_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_orc_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i32 HAVE_FACILITY(MISC_INSN_EXT3)
@@ -59,7 +58,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3)
-#define TCG_TARGET_HAS_andc_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_orc_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i64 HAVE_FACILITY(MISC_INSN_EXT3)
diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h
index ad6f35da17..510b9e64a4 100644
--- a/tcg/sparc64/tcg-target-has.h
+++ b/tcg/sparc64/tcg-target-has.h
@@ -20,7 +20,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@@ -46,7 +45,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h
index 4ccdc6bbee..7e4301521e 100644
--- a/tcg/tcg-has.h
+++ b/tcg/tcg-has.h
@@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 0
-#define TCG_TARGET_HAS_andc_i64 0
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index cb0964c3d4..e09d366517 100644
--- a/tcg/tci/tcg-target-has.h
+++ b/tcg/tci/tcg-target-has.h
@@ -11,7 +11,6 @@
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
-#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
@@ -36,7 +35,6 @@
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
-#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 82f3ad501f..68818cbb0c 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -668,7 +668,7 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv=
_i32 arg2)
=20
void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- if (TCG_TARGET_HAS_andc_i32) {
+ if (tcg_op_supported(INDEX_op_andc_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
} else {
TCGv_i32 t0 =3D tcg_temp_ebb_new_i32();
@@ -2264,7 +2264,7 @@ void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TC=
Gv_i64 arg2)
if (TCG_TARGET_REG_BITS =3D=3D 32) {
tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
- } else if (TCG_TARGET_HAS_andc_i64) {
+ } else if (tcg_op_supported(INDEX_op_andc_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
} else {
TCGv_i64 t0 =3D tcg_temp_ebb_new_i64();
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e77a24adc7..a037295710 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -993,6 +993,8 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D {
[0 ... NB_OPS - 1] =3D &outop_notreached,
OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add),
OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
+ OUTOP(INDEX_op_andc_i32, TCGOutOpBinary, outop_andc),
+ OUTOP(INDEX_op_andc_i64, TCGOutOpBinary, outop_andc),
};
=20
#undef OUTOP
@@ -2269,8 +2271,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns=
igned flags)
return TCG_TARGET_HAS_bswap32_i32;
case INDEX_op_not_i32:
return TCG_TARGET_HAS_not_i32;
- case INDEX_op_andc_i32:
- return TCG_TARGET_HAS_andc_i32;
case INDEX_op_orc_i32:
return TCG_TARGET_HAS_orc_i32;
case INDEX_op_eqv_i32:
@@ -2346,8 +2346,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns=
igned flags)
return TCG_TARGET_HAS_bswap64_i64;
case INDEX_op_not_i64:
return TCG_TARGET_HAS_not_i64;
- case INDEX_op_andc_i64:
- return TCG_TARGET_HAS_andc_i64;
case INDEX_op_orc_i64:
return TCG_TARGET_HAS_orc_i64;
case INDEX_op_eqv_i64:
@@ -5428,6 +5426,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG=
Op *op)
=20
case INDEX_op_add:
case INDEX_op_and:
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
{
const TCGOutOpBinary *out =3D
container_of(all_outop[op->opc], TCGOutOpBinary, base);
diff --git a/tcg/tci.c b/tcg/tci.c
index ce7cbe566b..8d7fb385a5 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -557,12 +557,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt=
ate *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] =3D regs[r1] ^ regs[r2];
break;
-#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
CASE_32_64(andc)
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] =3D regs[r1] & ~regs[r2];
break;
-#endif
#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
CASE_32_64(orc)
tci_args_rrr(insn, &r0, &r1, &r2);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 8da2703bb4..06d082ffd9 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2146,6 +2146,17 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_insn(s, 3510, BIC, type, a0, a1, a2);
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, r),
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2231,17 +2242,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType ext,
tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
break;
=20
- case INDEX_op_andc_i32:
- a2 =3D (int32_t)a2;
- /* FALLTHRU */
- case INDEX_op_andc_i64:
- if (c2) {
- tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2);
- } else {
- tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2);
- }
- break;
-
case INDEX_op_or_i32:
a2 =3D (int32_t)a2;
/* FALLTHRU */
@@ -3032,8 +3032,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32:
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 87571f2621..9db2a59be1 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1896,6 +1896,17 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0));
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, r),
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1958,10 +1969,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
args[0], args[1], args[2], const_args[2]);
}
break;
- case INDEX_op_andc_i32:
- tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
- args[0], args[1], args[2], const_args[2]);
- break;
case INDEX_op_or_i32:
c =3D ARITH_ORR;
goto gen_arith;
@@ -2233,7 +2240,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_negsetcond_i32:
return C_O1_I2(r, r, rIN);
=20
- case INDEX_op_andc_i32:
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
return C_O1_I2(r, r, rIK);
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 6d8c7a8d5c..7fc4fdd9d6 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2680,6 +2680,24 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW;
+ tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
+}
+
+static TCGConstraintSetIndex cset_andc(TCGType type, unsigned flags)
+{
+ return have_bmi1 ? C_O1_I2(r, r, r) : C_NotImplemented;
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_Dynamic,
+ .base.dynamic_constraint =3D cset_andc,
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2779,15 +2797,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- OP_32_64(andc):
- if (const_a2) {
- tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
- tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0);
- } else {
- tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
- }
- break;
-
OP_32_64(mul):
if (const_a2) {
int32_t val;
@@ -3737,10 +3746,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsign=
ed flags)
case INDEX_op_xor_i64:
return C_O1_I2(r, 0, re);
=20
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
- return C_O1_I2(r, r, rI);
-
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
case INDEX_op_shr_i32:
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.=
c.inc
index a0c57dad40..7503c3f25c 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1313,6 +1313,17 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_opc_andn(s, a0, a1, a2);
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, r),
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1363,16 +1374,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
- if (c2) {
- /* guaranteed to fit due to constraint */
- tcg_out_opc_andi(s, a0, a1, ~a2);
- } else {
- tcg_out_opc_andn(s, a0, a1, a2);
- }
- break;
-
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
@@ -2286,8 +2287,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_qemu_ld_a64_i64:
return C_O1_I1(r, r);
=20
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
/*
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 2fd88b4ab8..1720ec45cd 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1731,6 +1731,10 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_NotImplemented,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 7d282bc7aa..563471497f 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2981,6 +2981,17 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out32(s, ANDC | SAB(a1, a0, a2));
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, r),
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -3084,22 +3095,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
tcg_out32(s, XOR | SAB(a1, a0, a2));
}
break;
- case INDEX_op_andc_i32:
- a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
- if (const_args[2]) {
- tcg_out_andi32(s, a0, a1, ~a2);
- } else {
- tcg_out32(s, ANDC | SAB(a1, a0, a2));
- }
- break;
- case INDEX_op_andc_i64:
- a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
- if (const_args[2]) {
- tcg_out_andi64(s, a0, a1, ~a2);
- } else {
- tcg_out32(s, ANDC | SAB(a1, a0, a2));
- }
- break;
case INDEX_op_orc_i32:
if (const_args[2]) {
tcg_out_ori32(s, args[0], args[1], ~args[2]);
@@ -4211,7 +4206,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
=20
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
- case INDEX_op_andc_i32:
case INDEX_op_orc_i32:
case INDEX_op_eqv_i32:
case INDEX_op_shl_i32:
@@ -4219,7 +4213,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_sar_i32:
case INDEX_op_rotl_i32:
case INDEX_op_rotr_i32:
- case INDEX_op_andc_i64:
case INDEX_op_shl_i64:
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 8f178a5eb7..8d56d887e0 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1999,6 +1999,23 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2);
+}
+
+static TCGConstraintSetIndex cset_zbb_rrr(TCGType type, unsigned flags)
+{
+ return cpuinfo & CPUINFO_ZBB ? C_O1_I2(r, r, r) : C_NotImplemented;
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_Dynamic,
+ .base.dynamic_constraint =3D cset_zbb_rrr,
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2095,14 +2112,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
- if (c2) {
- tcg_out_opc_imm(s, OPC_ANDI, a0, a1, ~a2);
- } else {
- tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2);
- }
- break;
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
@@ -2684,8 +2693,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_negsetcond_i64:
return C_O1_I2(r, r, rI);
=20
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32:
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 4a2661c7ff..789e68a061 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2221,6 +2221,27 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi_3,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ if (type =3D=3D TCG_TYPE_I32) {
+ tcg_out_insn(s, RRFa, NCRK, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2);
+ }
+}
+
+static TCGConstraintSetIndex cset_misc3_rrr(TCGType type, unsigned flags)
+{
+ return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I2(r, r, r) : C_NotImpleme=
nted;
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_Dynamic,
+ .base.dynamic_constraint =3D cset_misc3_rrr,
+ .out_rrr =3D tgen_andc,
+};
+
=20
# define OP_32_64(x) \
case glue(glue(INDEX_op_,x),_i32): \
@@ -2312,15 +2333,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_andc_i32:
- a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2);
- } else {
- tcg_out_insn(s, RRFa, NCRK, a0, a1, a2);
- }
- break;
case INDEX_op_orc_i32:
a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2];
if (const_args[2]) {
@@ -2574,15 +2586,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,=
TCGType type,
}
break;
=20
- case INDEX_op_andc_i64:
- a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_andi(s, TCG_TYPE_I64, a0, ~a2);
- } else {
- tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2);
- }
- break;
case INDEX_op_orc_i64:
a0 =3D args[0], a1 =3D args[1], a2 =3D args[2];
if (const_args[2]) {
@@ -3292,12 +3295,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsign=
ed flags)
case INDEX_op_xor_i64:
return C_O1_I2(r, r, rK);
=20
- case INDEX_op_andc_i32:
case INDEX_op_orc_i32:
case INDEX_op_eqv_i32:
return C_O1_I2(r, r, ri);
- case INDEX_op_andc_i64:
- return C_O1_I2(r, r, rKR);
case INDEX_op_orc_i64:
case INDEX_op_eqv_i64:
return C_O1_I2(r, r, rNK);
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 7af1f9824d..87a496f4a8 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -1325,6 +1325,17 @@ static const TCGOutOpBinary outop_and =3D {
.out_rri =3D tgen_andi,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_arith(s, a0, a1, a2, ARITH_ANDN);
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, r),
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -1382,9 +1393,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =
TCGType type,
OP_32_64(sub):
c =3D ARITH_SUB;
goto gen_arith;
- OP_32_64(andc):
- c =3D ARITH_ANDN;
- goto gen_arith;
OP_32_64(or):
c =3D ARITH_OR;
goto gen_arith;
@@ -1615,8 +1623,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigne=
d flags)
case INDEX_op_divu_i64:
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
case INDEX_op_or_i32:
case INDEX_op_or_i64:
case INDEX_op_orc_i32:
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 4830c3b24d..3a4c65fcec 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -95,8 +95,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned fl=
ags)
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
- case INDEX_op_andc_i32:
- case INDEX_op_andc_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
case INDEX_op_nand_i32:
@@ -681,6 +679,17 @@ static const TCGOutOpBinary outop_and =3D {
.out_rrr =3D tgen_and,
};
=20
+static void tgen_andc(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+ tcg_out_op_rrr(s, glue(INDEX_op_andc_i,TCG_TARGET_REG_BITS), a0, a1, a=
2);
+}
+
+static const TCGOutOpBinary outop_andc =3D {
+ .base.static_constraint =3D C_O1_I2(r, r, r),
+ .out_rrr =3D tgen_andc,
+};
+
=20
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -727,7 +736,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TC=
GType type,
CASE_32_64(mul)
CASE_32_64(or)
CASE_32_64(xor)
- CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */
CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */
CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
--=20
2.43.0