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Mon, 06 Jan 2025 02:24:22 -0800 (PST) From: baturo.alexey@gmail.com To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, frank.chang@sifive.com, Alistair Francis Subject: [PATCH v15 6/7] target/riscv: Apply pointer masking for virtualized memory accesses Date: Mon, 6 Jan 2025 13:23:45 +0300 Message-Id: <20250106102346.1100149-7-baturo.alexey@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250106102346.1100149-1-baturo.alexey@gmail.com> References: <20250106102346.1100149-1-baturo.alexey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=baturo.alexey@gmail.com; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1736159172620116600 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 19 +++++++++++++ target/riscv/internals.h | 54 ++++++++++++++++++++++++++++++++++++ target/riscv/op_helper.c | 16 +++++------ target/riscv/vector_helper.c | 21 -------------- 5 files changed, 82 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b7458c40d8..504bab31b1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -776,6 +776,7 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); =20 RISCVException riscv_csrr(CPURISCVState *env, int csrno, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8728541b99..2e307e4ea5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -263,6 +263,25 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) #endif } =20 +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + int priv_mode =3D cpu_address_mode(env); + + if (priv_mode =3D=3D PRV_U) { + return get_field(env->hstatus, HSTATUS_HUPMM); + } else { + if (get_field(env->hstatus, HSTATUS_SPVP)) { + return get_field(env->henvcfg, HENVCFG_PMM); + } else { + return get_field(env->senvcfg, SENVCFG_PMM); + } + } +#else + return PMM_FIELD_DISABLED; +#endif +} + bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 76934eaa7b..67291933f8 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -145,4 +145,58 @@ static inline float16 check_nanbox_h(CPURISCVState *en= v, uint64_t f) /* Our implementation of CPUClass::has_work */ bool riscv_cpu_has_work(CPUState *cs); =20 +/* Zjpm addr masking routine */ +static inline target_ulong adjust_addr_body(CPURISCVState *env, + target_ulong addr, + bool is_virt_addr) +{ + RISCVPmPmm pmm =3D PMM_FIELD_DISABLED; + uint32_t pmlen =3D 0; + bool signext =3D false; + + /* do nothing for rv32 mode */ + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + return addr; + } + + /* get pmm field depending on whether addr is */ + if (is_virt_addr) { + pmm =3D riscv_pm_get_virt_pmm(env); + } else { + pmm =3D riscv_pm_get_pmm(env); + } + + /* if pointer masking is disabled, return original addr */ + if (pmm =3D=3D PMM_FIELD_DISABLED) { + return addr; + } + + if (!is_virt_addr) { + signext =3D riscv_cpu_virt_mem_enabled(env); + } + addr =3D addr << pmlen; + pmlen =3D riscv_pm_get_pmlen(pmm); + + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr =3D (target_long)addr >> pmlen; + } else { + addr =3D addr >> pmlen; + } + + return addr; +} + +static inline target_ulong adjust_addr(CPURISCVState *env, + target_ulong addr) +{ + return adjust_addr_body(env, addr, false); +} + +static inline target_ulong adjust_addr_virt(CPURISCVState *env, + target_ulong addr) +{ + return adjust_addr_body(env, addr, true); +} + #endif diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eddedacf4b..20e5bd5088 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -472,7 +472,7 @@ target_ulong helper_hyp_hlv_bu(CPURISCVState *env, targ= et_ulong addr) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); =20 - return cpu_ldb_mmu(env, addr, oi, ra); + return cpu_ldb_mmu(env, adjust_addr_virt(env, addr), oi, ra); } =20 target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) @@ -481,7 +481,7 @@ target_ulong helper_hyp_hlv_hu(CPURISCVState *env, targ= et_ulong addr) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); =20 - return cpu_ldw_mmu(env, addr, oi, ra); + return cpu_ldw_mmu(env, adjust_addr_virt(env, addr), oi, ra); } =20 target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) @@ -490,7 +490,7 @@ target_ulong helper_hyp_hlv_wu(CPURISCVState *env, targ= et_ulong addr) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); =20 - return cpu_ldl_mmu(env, addr, oi, ra); + return cpu_ldl_mmu(env, adjust_addr_virt(env, addr), oi, ra); } =20 target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) @@ -499,7 +499,7 @@ target_ulong helper_hyp_hlv_d(CPURISCVState *env, targe= t_ulong addr) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); =20 - return cpu_ldq_mmu(env, addr, oi, ra); + return cpu_ldq_mmu(env, adjust_addr_virt(env, addr), oi, ra); } =20 void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong = val) @@ -508,7 +508,7 @@ void helper_hyp_hsv_b(CPURISCVState *env, target_ulong = addr, target_ulong val) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); =20 - cpu_stb_mmu(env, addr, val, oi, ra); + cpu_stb_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } =20 void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong = val) @@ -517,7 +517,7 @@ void helper_hyp_hsv_h(CPURISCVState *env, target_ulong = addr, target_ulong val) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); =20 - cpu_stw_mmu(env, addr, val, oi, ra); + cpu_stw_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } =20 void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong = val) @@ -526,7 +526,7 @@ void helper_hyp_hsv_w(CPURISCVState *env, target_ulong = addr, target_ulong val) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); =20 - cpu_stl_mmu(env, addr, val, oi, ra); + cpu_stl_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } =20 void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong = val) @@ -535,7 +535,7 @@ void helper_hyp_hsv_d(CPURISCVState *env, target_ulong = addr, target_ulong val) int mmu_idx =3D check_access_hlsv(env, false, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); =20 - cpu_stq_mmu(env, addr, val, oi, ra); + cpu_stq_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); } =20 /* diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 0eea124b66..5386e3b97c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -105,27 +105,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, u= int32_t log2_esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } =20 -static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) -{ - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - return addr; - } - RISCVPmPmm pmm =3D riscv_pm_get_pmm(env); - if (pmm =3D=3D PMM_FIELD_DISABLED) { - return addr; - } - int pmlen =3D riscv_pm_get_pmlen(pmm); - bool signext =3D riscv_cpu_virt_mem_enabled(env); - addr =3D addr << pmlen; - /* sign/zero extend masked address by N-1 bit */ - if (signext) { - addr =3D (target_long)addr >> pmlen; - } else { - addr =3D addr >> pmlen; - } - return addr; -} - /* * This function checks watchpoint before real load operation. * --=20 2.39.5