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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:00:54 +0900
Subject: [PATCH v8 1/9] hw/pci: Do not add ROM BAR for SR-IOV VF
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To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
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=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>,
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Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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A SR-IOV VF cannot have a ROM BAR.
Co-developed-by: Yui Washizu <yui.washidu@gmail.com>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
hw/pci/pci.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 8f160c0c0d8a..c4fa32dc987a 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2432,6 +2432,14 @@ static void pci_add_option_rom(PCIDevice *pdev, bool=
is_default_rom,
return;
}
=20
+ if (pci_is_vf(pdev)) {
+ if (pdev->rom_bar > 0) {
+ error_setg(errp, "ROM BAR cannot be enabled for SR-IOV VF");
+ }
+
+ return;
+ }
+
if (load_file || pdev->romsize =3D=3D UINT32_MAX) {
path =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
if (path =3D=3D NULL) {
--=20
2.47.1
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:00:55 +0900
Subject: [PATCH v8 2/9] hw/pci: Fix SR-IOV VF number calculation
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To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>,
Eduardo Habkost <eduardo@habkost.net>, Jason Wang <jasowang@redhat.com>,
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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pci_config_get_bar_addr() had a division by vf_stride. vf_stride needs
to be non-zero when there are multiple VFs, but the specification does
not prohibit to make it zero when there is only one VF.
Do not perform the division for the first VF to avoid division by zero.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
hw/pci/pci.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index c4fa32dc987a..ba53302ecc5f 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1510,7 +1510,11 @@ static pcibus_t pci_config_get_bar_addr(PCIDevice *d=
, int reg,
pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET);
uint16_t vf_stride =3D
pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE);
- uint32_t vf_num =3D (d->devfn - (pf->devfn + vf_offset)) / vf_stri=
de;
+ uint32_t vf_num =3D d->devfn - (pf->devfn + vf_offset);
+
+ if (vf_num) {
+ vf_num /=3D vf_stride;
+ }
=20
if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
new_addr =3D pci_get_quad(pf->config + bar);
--=20
2.47.1
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:00:56 +0900
Subject: [PATCH v8 3/9] pcie_sriov: Ensure PF and VF are mutually exclusive
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To: "Michael S. Tsirkin" <mst@redhat.com>,
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=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
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Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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A device cannot be a SR-IOV PF and a VF at the same time.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
hw/pci/pcie_sriov.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index 1eb4358256de..109b2ebcccba 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@ -42,6 +42,11 @@ bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
uint8_t *cfg =3D dev->config + offset;
uint8_t *wmask;
=20
+ if (pci_is_vf(dev)) {
+ error_setg(errp, "a device cannot be a SR-IOV PF and a VF at the s=
ame time");
+ return false;
+ }
+
if (total_vfs &&
(uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >=3D PCI_D=
EVFN_MAX) {
error_setg(errp, "VF addr overflows");
--=20
2.47.1
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:00:57 +0900
Subject: [PATCH v8 4/9] pcie_sriov: Check PCI Express for SR-IOV PF
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To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>,
Eduardo Habkost <eduardo@habkost.net>, Jason Wang <jasowang@redhat.com>,
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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SR-IOV requires PCI Express.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
hw/pci/pcie_sriov.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index 109b2ebcccba..a5b546abe8bb 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@ -42,6 +42,11 @@ bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
uint8_t *cfg =3D dev->config + offset;
uint8_t *wmask;
=20
+ if (!pci_is_express(dev)) {
+ error_setg(errp, "PCI Express is required for SR-IOV PF");
+ return false;
+ }
+
if (pci_is_vf(dev)) {
error_setg(errp, "a device cannot be a SR-IOV PF and a VF at the s=
ame time");
return false;
--=20
2.47.1
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:00:58 +0900
Subject: [PATCH v8 5/9] pcie_sriov: Allow user to create SR-IOV device
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References: <20250104-sriov-v8-0-56144cfdc7d9@daynix.com>
In-Reply-To: <20250104-sriov-v8-0-56144cfdc7d9@daynix.com>
To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>,
Eduardo Habkost <eduardo@habkost.net>, Jason Wang <jasowang@redhat.com>,
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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X-ZM-MESSAGEID: 1735977744288116600
A user can create a SR-IOV device by specifying the PF with the
sriov-pf property of the VFs. The VFs must be added before the PF.
A user-creatable VF must have PCIDeviceClass::sriov_vf_user_creatable
set. Such a VF cannot refer to the PF because it is created before the
PF.
A PF that user-creatable VFs can be attached calls
pcie_sriov_pf_init_from_user_created_vfs() during realization and
pcie_sriov_pf_exit() when exiting.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
include/hw/pci/pci_device.h | 6 +-
include/hw/pci/pcie_sriov.h | 18 +++
hw/pci/pci.c | 62 ++++++----
hw/pci/pcie_sriov.c | 278 +++++++++++++++++++++++++++++++++++-----=
----
4 files changed, 286 insertions(+), 78 deletions(-)
diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h
index 613f78aebf62..7af09b3202e3 100644
--- a/include/hw/pci/pci_device.h
+++ b/include/hw/pci/pci_device.h
@@ -38,6 +38,8 @@ struct PCIDeviceClass {
uint16_t subsystem_id; /* only for header type =3D 0 */
=20
const char *romfile; /* rom bar */
+
+ bool sriov_vf_user_creatable;
};
=20
enum PCIReqIDType {
@@ -174,6 +176,8 @@ struct PCIDevice {
* realizing the device.
*/
uint32_t max_bounce_buffer_size;
+
+ char *sriov_pf;
};
=20
static inline int pci_intx(PCIDevice *pci_dev)
@@ -206,7 +210,7 @@ static inline int pci_is_express_downstream_port(const =
PCIDevice *d)
=20
static inline int pci_is_vf(const PCIDevice *d)
{
- return d->exp.sriov_vf.pf !=3D NULL;
+ return d->sriov_pf || d->exp.sriov_vf.pf !=3D NULL;
}
=20
static inline uint32_t pci_config_size(const PCIDevice *d)
diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h
index c5d2d318d330..f75b8f22ee92 100644
--- a/include/hw/pci/pcie_sriov.h
+++ b/include/hw/pci/pcie_sriov.h
@@ -18,6 +18,7 @@
typedef struct PCIESriovPF {
uint8_t vf_bar_type[PCI_NUM_REGIONS]; /* Store type for each VF bar =
*/
PCIDevice **vf; /* Pointer to an array of num_vfs VF devices */
+ bool vf_user_created; /* If VFs are created by user */
} PCIESriovPF;
=20
typedef struct PCIESriovVF {
@@ -40,6 +41,23 @@ void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int regio=
n_num,
void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num,
MemoryRegion *memory);
=20
+/**
+ * pcie_sriov_pf_init_from_user_created_vfs() - Initialize PF with user-cr=
eated
+ * VFs.
+ * @dev: A PCIe device being realized.
+ * @offset: The offset of the SR-IOV capability.
+ * @errp: pointer to Error*, to store an error if it happens.
+ *
+ * Return: The size of added capability. 0 if the user did not create VFs.
+ * -1 if failed.
+ */
+int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev,
+ uint16_t offset,
+ Error **errp);
+
+bool pcie_sriov_register_device(PCIDevice *dev, Error **errp);
+void pcie_sriov_unregister_device(PCIDevice *dev);
+
/*
* Default (minimal) page size support values
* as required by the SR/IOV standard:
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index ba53302ecc5f..7e9dbab949ce 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -101,6 +101,7 @@ static const Property pci_props[] =3D {
QEMU_PCIE_ARI_NEXTFN_1_BITNR, false),
DEFINE_PROP_SIZE32("x-max-bounce-buffer-size", PCIDevice,
max_bounce_buffer_size, DEFAULT_MAX_BOUNCE_BUFFER_SIZ=
E),
+ DEFINE_PROP_STRING("sriov-pf", PCIDevice, sriov_pf),
DEFINE_PROP_BIT("x-pcie-ext-tag", PCIDevice, cap_present,
QEMU_PCIE_EXT_TAG_BITNR, true),
{ .name =3D "busnr", .info =3D &prop_pci_busnr },
@@ -1029,13 +1030,8 @@ static void pci_init_multifunction(PCIBus *bus, PCID=
evice *dev, Error **errp)
dev->config[PCI_HEADER_TYPE] |=3D PCI_HEADER_TYPE_MULTI_FUNCTION;
}
=20
- /*
- * With SR/IOV and ARI, a device at function 0 need not be a multifunc=
tion
- * device, as it may just be a VF that ended up with function 0 in
- * the legacy PCI interpretation. Avoid failing in such cases:
- */
- if (pci_is_vf(dev) &&
- dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
+ /* SR/IOV is not handled here. */
+ if (pci_is_vf(dev)) {
return;
}
=20
@@ -1068,7 +1064,8 @@ static void pci_init_multifunction(PCIBus *bus, PCIDe=
vice *dev, Error **errp)
}
/* function 0 indicates single function, so function > 0 must be NULL =
*/
for (func =3D 1; func < PCI_FUNC_MAX; ++func) {
- if (bus->devices[PCI_DEVFN(slot, func)]) {
+ PCIDevice *device =3D bus->devices[PCI_DEVFN(slot, func)];
+ if (device && !pci_is_vf(device)) {
error_setg(errp, "PCI: %x.0 indicates single function, "
"but %x.%x is already populated.",
slot, slot, func);
@@ -1356,6 +1353,7 @@ static void pci_qdev_unrealize(DeviceState *dev)
=20
pci_unregister_io_regions(pci_dev);
pci_del_option_rom(pci_dev);
+ pcie_sriov_unregister_device(pci_dev);
=20
if (pc->exit) {
pc->exit(pci_dev);
@@ -1387,7 +1385,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_=
num,
pcibus_t size =3D memory_region_size(memory);
uint8_t hdr_type;
=20
- assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_ba=
r */
assert(region_num >=3D 0);
assert(region_num < PCI_NUM_REGIONS);
assert(is_power_of_2(size));
@@ -1398,7 +1395,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_=
num,
assert(hdr_type !=3D PCI_HEADER_TYPE_BRIDGE || region_num < 2);
=20
r =3D &pci_dev->io_regions[region_num];
- r->addr =3D PCI_BAR_UNMAPPED;
r->size =3D size;
r->type =3D type;
r->memory =3D memory;
@@ -1406,22 +1402,35 @@ void pci_register_bar(PCIDevice *pci_dev, int regio=
n_num,
? pci_get_bus(pci_dev)->address_space_io
: pci_get_bus(pci_dev)->address_space_mem;
=20
- wmask =3D ~(size - 1);
- if (region_num =3D=3D PCI_ROM_SLOT) {
- /* ROM enable bit is writable */
- wmask |=3D PCI_ROM_ADDRESS_ENABLE;
- }
-
- addr =3D pci_bar(pci_dev, region_num);
- pci_set_long(pci_dev->config + addr, type);
+ if (pci_is_vf(pci_dev)) {
+ PCIDevice *pf =3D pci_dev->exp.sriov_vf.pf;
+ assert(!pf || type =3D=3D pf->exp.sriov_pf.vf_bar_type[region_num]=
);
=20
- if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
- r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- pci_set_quad(pci_dev->wmask + addr, wmask);
- pci_set_quad(pci_dev->cmask + addr, ~0ULL);
+ r->addr =3D pci_bar_address(pci_dev, region_num, r->type, r->size);
+ if (r->addr !=3D PCI_BAR_UNMAPPED) {
+ memory_region_add_subregion_overlap(r->address_space,
+ r->addr, r->memory, 1);
+ }
} else {
- pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
- pci_set_long(pci_dev->cmask + addr, 0xffffffff);
+ r->addr =3D PCI_BAR_UNMAPPED;
+
+ wmask =3D ~(size - 1);
+ if (region_num =3D=3D PCI_ROM_SLOT) {
+ /* ROM enable bit is writable */
+ wmask |=3D PCI_ROM_ADDRESS_ENABLE;
+ }
+
+ addr =3D pci_bar(pci_dev, region_num);
+ pci_set_long(pci_dev->config + addr, type);
+
+ if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
+ r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ pci_set_quad(pci_dev->wmask + addr, wmask);
+ pci_set_quad(pci_dev->cmask + addr, ~0ULL);
+ } else {
+ pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
+ pci_set_long(pci_dev->cmask + addr, 0xffffffff);
+ }
}
}
=20
@@ -2182,6 +2191,11 @@ static void pci_qdev_realize(DeviceState *qdev, Erro=
r **errp)
}
}
=20
+ if (!pcie_sriov_register_device(pci_dev, errp)) {
+ pci_qdev_unrealize(DEVICE(pci_dev));
+ return;
+ }
+
/*
* A PCIe Downstream Port that do not have ARI Forwarding enabled must
* associate only Device 0 with the device attached to the bus
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index a5b546abe8bb..08f707e847fd 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@ -15,11 +15,12 @@
#include "hw/pci/pcie.h"
#include "hw/pci/pci_bus.h"
#include "hw/qdev-properties.h"
-#include "qemu/error-report.h"
#include "qemu/range.h"
#include "qapi/error.h"
#include "trace.h"
=20
+static GHashTable *pfs;
+
static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs)
{
for (uint16_t i =3D 0; i < total_vfs; i++) {
@@ -31,13 +32,43 @@ static void unparent_vfs(PCIDevice *dev, uint16_t total=
_vfs)
dev->exp.sriov_pf.vf =3D NULL;
}
=20
-bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
- const char *vfname, uint16_t vf_dev_id,
- uint16_t init_vfs, uint16_t total_vfs,
- uint16_t vf_offset, uint16_t vf_stride,
- Error **errp)
+static void register_vfs(PCIDevice *dev)
+{
+ uint16_t num_vfs;
+ uint16_t i;
+ uint16_t sriov_cap =3D dev->exp.sriov_cap;
+
+ assert(sriov_cap > 0);
+ num_vfs =3D pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
+
+ trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn), num_vfs);
+ for (i =3D 0; i < num_vfs; i++) {
+ pci_set_enabled(dev->exp.sriov_pf.vf[i], true);
+ }
+
+ pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0);
+}
+
+static void unregister_vfs(PCIDevice *dev)
+{
+ uint8_t *cfg =3D dev->config + dev->exp.sriov_cap;
+ uint16_t i;
+
+ trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn),
+ PCI_FUNC(dev->devfn));
+ for (i =3D 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) {
+ pci_set_enabled(dev->exp.sriov_pf.vf[i], false);
+ }
+
+ pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xfff=
f);
+}
+
+static bool pcie_sriov_pf_init_common(PCIDevice *dev, uint16_t offset,
+ uint16_t vf_dev_id, uint16_t init_vf=
s,
+ uint16_t total_vfs, uint16_t vf_offs=
et,
+ uint16_t vf_stride, Error **errp)
{
- BusState *bus =3D qdev_get_parent_bus(&dev->qdev);
int32_t devfn =3D dev->devfn + vf_offset;
uint8_t *cfg =3D dev->config + offset;
uint8_t *wmask;
@@ -94,6 +125,28 @@ bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
=20
qdev_prop_set_bit(&dev->qdev, "multifunction", true);
=20
+ return true;
+}
+
+bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
+ const char *vfname, uint16_t vf_dev_id,
+ uint16_t init_vfs, uint16_t total_vfs,
+ uint16_t vf_offset, uint16_t vf_stride,
+ Error **errp)
+{
+ BusState *bus =3D qdev_get_parent_bus(&dev->qdev);
+ int32_t devfn =3D dev->devfn + vf_offset;
+
+ if (pfs && g_hash_table_contains(pfs, dev->qdev.id)) {
+ error_setg(errp, "attaching user-created SR-IOV VF unsupported");
+ return false;
+ }
+
+ if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, init_vfs,
+ total_vfs, vf_offset, vf_stride, errp))=
{
+ return false;
+ }
+
dev->exp.sriov_pf.vf =3D g_new(PCIDevice *, total_vfs);
=20
for (uint16_t i =3D 0; i < total_vfs; i++) {
@@ -123,7 +176,22 @@ void pcie_sriov_pf_exit(PCIDevice *dev)
{
uint8_t *cfg =3D dev->config + dev->exp.sriov_cap;
=20
- unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF));
+ if (dev->exp.sriov_pf.vf_user_created) {
+ uint16_t ven_id =3D pci_get_word(dev->config + PCI_VENDOR_ID);
+ uint16_t total_vfs =3D pci_get_word(dev->config + PCI_SRIOV_TOTAL_=
VF);
+ uint16_t vf_dev_id =3D pci_get_word(dev->config + PCI_SRIOV_VF_DID=
);
+
+ unregister_vfs(dev);
+
+ for (uint16_t i =3D 0; i < total_vfs; i++) {
+ dev->exp.sriov_pf.vf[i]->exp.sriov_vf.pf =3D NULL;
+
+ pci_config_set_vendor_id(dev->exp.sriov_pf.vf[i]->config, ven_=
id);
+ pci_config_set_device_id(dev->exp.sriov_pf.vf[i]->config, vf_d=
ev_id);
+ }
+ } else {
+ unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF));
+ }
}
=20
void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num,
@@ -156,69 +224,173 @@ void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int r=
egion_num,
void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num,
MemoryRegion *memory)
{
- PCIIORegion *r;
- PCIBus *bus =3D pci_get_bus(dev);
uint8_t type;
- pcibus_t size =3D memory_region_size(memory);
=20
- assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */
- assert(region_num >=3D 0);
- assert(region_num < PCI_NUM_REGIONS);
+ assert(dev->exp.sriov_vf.pf);
type =3D dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num];
=20
- if (!is_power_of_2(size)) {
- error_report("%s: PCI region size must be a power"
- " of two - type=3D0x%x, size=3D0x%"FMT_PCIBUS,
- __func__, type, size);
- exit(1);
- }
+ return pci_register_bar(dev, region_num, type, memory);
+}
=20
- r =3D &dev->io_regions[region_num];
- r->memory =3D memory;
- r->address_space =3D
- type & PCI_BASE_ADDRESS_SPACE_IO
- ? bus->address_space_io
- : bus->address_space_mem;
- r->size =3D size;
- r->type =3D type;
-
- r->addr =3D pci_bar_address(dev, region_num, r->type, r->size);
- if (r->addr !=3D PCI_BAR_UNMAPPED) {
- memory_region_add_subregion_overlap(r->address_space,
- r->addr, r->memory, 1);
- }
+static gint compare_vf_devfns(gconstpointer a, gconstpointer b)
+{
+ return (*(PCIDevice **)a)->devfn - (*(PCIDevice **)b)->devfn;
}
=20
-static void register_vfs(PCIDevice *dev)
+int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev,
+ uint16_t offset,
+ Error **errp)
{
- uint16_t num_vfs;
+ GPtrArray *pf;
+ PCIDevice **vfs;
+ BusState *bus =3D qdev_get_parent_bus(DEVICE(dev));
+ uint16_t ven_id =3D pci_get_word(dev->config + PCI_VENDOR_ID);
+ uint16_t vf_dev_id;
+ uint16_t vf_offset;
+ uint16_t vf_stride;
uint16_t i;
- uint16_t sriov_cap =3D dev->exp.sriov_cap;
=20
- assert(sriov_cap > 0);
- num_vfs =3D pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
+ if (!pfs || !dev->qdev.id) {
+ return 0;
+ }
=20
- trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn),
- PCI_FUNC(dev->devfn), num_vfs);
- for (i =3D 0; i < num_vfs; i++) {
- pci_set_enabled(dev->exp.sriov_pf.vf[i], true);
+ pf =3D g_hash_table_lookup(pfs, dev->qdev.id);
+ if (!pf) {
+ return 0;
}
=20
- pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0);
+ if (pf->len > UINT16_MAX) {
+ error_setg(errp, "too many VFs");
+ return -1;
+ }
+
+ g_ptr_array_sort(pf, compare_vf_devfns);
+ vfs =3D (void *)pf->pdata;
+
+ if (vfs[0]->devfn <=3D dev->devfn) {
+ error_setg(errp, "a VF function number is less than the PF functio=
n number");
+ return -1;
+ }
+
+ vf_dev_id =3D pci_get_word(vfs[0]->config + PCI_DEVICE_ID);
+ vf_offset =3D vfs[0]->devfn - dev->devfn;
+ vf_stride =3D pf->len < 2 ? 0 : vfs[1]->devfn - vfs[0]->devfn;
+
+ for (i =3D 0; i < pf->len; i++) {
+ if (bus !=3D qdev_get_parent_bus(&vfs[i]->qdev)) {
+ error_setg(errp, "SR-IOV VF parent bus mismatches with PF");
+ return -1;
+ }
+
+ if (ven_id !=3D pci_get_word(vfs[i]->config + PCI_VENDOR_ID)) {
+ error_setg(errp, "SR-IOV VF vendor ID mismatches with PF");
+ return -1;
+ }
+
+ if (vf_dev_id !=3D pci_get_word(vfs[i]->config + PCI_DEVICE_ID)) {
+ error_setg(errp, "inconsistent SR-IOV VF device IDs");
+ return -1;
+ }
+
+ for (size_t j =3D 0; j < PCI_NUM_REGIONS; j++) {
+ if (vfs[i]->io_regions[j].size !=3D vfs[0]->io_regions[j].size=
||
+ vfs[i]->io_regions[j].type !=3D vfs[0]->io_regions[j].type=
) {
+ error_setg(errp, "inconsistent SR-IOV BARs");
+ return -1;
+ }
+ }
+
+ if (vfs[i]->devfn - vfs[0]->devfn !=3D vf_stride * i) {
+ error_setg(errp, "inconsistent SR-IOV stride");
+ return -1;
+ }
+ }
+
+ if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, pf->len,
+ pf->len, vf_offset, vf_stride, errp)) {
+ return -1;
+ }
+
+ for (i =3D 0; i < pf->len; i++) {
+ vfs[i]->exp.sriov_vf.pf =3D dev;
+ vfs[i]->exp.sriov_vf.vf_number =3D i;
+
+ /* set vid/did according to sr/iov spec - they are not used */
+ pci_config_set_vendor_id(vfs[i]->config, 0xffff);
+ pci_config_set_device_id(vfs[i]->config, 0xffff);
+ }
+
+ dev->exp.sriov_pf.vf =3D vfs;
+ dev->exp.sriov_pf.vf_user_created =3D true;
+
+ for (i =3D 0; i < PCI_NUM_REGIONS; i++) {
+ PCIIORegion *region =3D &vfs[0]->io_regions[i];
+
+ if (region->size) {
+ pcie_sriov_pf_init_vf_bar(dev, i, region->type, region->size);
+ }
+ }
+
+ return PCI_EXT_CAP_SRIOV_SIZEOF;
}
=20
-static void unregister_vfs(PCIDevice *dev)
+bool pcie_sriov_register_device(PCIDevice *dev, Error **errp)
{
- uint8_t *cfg =3D dev->config + dev->exp.sriov_cap;
- uint16_t i;
+ if (!dev->exp.sriov_pf.vf && dev->qdev.id &&
+ pfs && g_hash_table_contains(pfs, dev->qdev.id)) {
+ error_setg(errp, "attaching user-created SR-IOV VF unsupported");
+ return false;
+ }
=20
- trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn),
- PCI_FUNC(dev->devfn));
- for (i =3D 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) {
- pci_set_enabled(dev->exp.sriov_pf.vf[i], false);
+ if (dev->sriov_pf) {
+ PCIDevice *pci_pf;
+ GPtrArray *pf;
+
+ if (!PCI_DEVICE_GET_CLASS(dev)->sriov_vf_user_creatable) {
+ error_setg(errp, "user cannot create SR-IOV VF with this devic=
e type");
+ return false;
+ }
+
+ if (!pci_is_express(dev)) {
+ error_setg(errp, "PCI Express is required for SR-IOV VF");
+ return false;
+ }
+
+ if (!pci_qdev_find_device(dev->sriov_pf, &pci_pf)) {
+ error_setg(errp, "PCI device specified as SR-IOV PF already ex=
ists");
+ return false;
+ }
+
+ if (!pfs) {
+ pfs =3D g_hash_table_new_full(g_str_hash, g_str_equal, g_free,=
NULL);
+ }
+
+ pf =3D g_hash_table_lookup(pfs, dev->sriov_pf);
+ if (!pf) {
+ pf =3D g_ptr_array_new();
+ g_hash_table_insert(pfs, g_strdup(dev->sriov_pf), pf);
+ }
+
+ g_ptr_array_add(pf, dev);
}
=20
- pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xfff=
f);
+ return true;
+}
+
+void pcie_sriov_unregister_device(PCIDevice *dev)
+{
+ if (dev->sriov_pf && pfs) {
+ GPtrArray *pf =3D g_hash_table_lookup(pfs, dev->sriov_pf);
+
+ if (pf) {
+ g_ptr_array_remove_fast(pf, dev);
+
+ if (!pf->len) {
+ g_hash_table_remove(pfs, dev->sriov_pf);
+ g_ptr_array_free(pf, FALSE);
+ }
+ }
+ }
}
=20
void pcie_sriov_config_write(PCIDevice *dev, uint32_t address,
@@ -314,7 +486,7 @@ void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint1=
6_t opt_sup_pgsize)
=20
uint16_t pcie_sriov_vf_number(PCIDevice *dev)
{
- assert(pci_is_vf(dev));
+ assert(dev->exp.sriov_vf.pf);
return dev->exp.sriov_vf.vf_number;
}
=20
--=20
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:00:59 +0900
Subject: [PATCH v8 6/9] virtio-pci: Implement SR-IOV PF
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To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
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=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>,
Eduardo Habkost <eduardo@habkost.net>, Jason Wang <jasowang@redhat.com>,
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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Allow user to attach SR-IOV VF to a virtio-pci PF.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
include/hw/virtio/virtio-pci.h | 1 +
hw/virtio/virtio-pci.c | 20 +++++++++++++++-----
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
index 971c5fabd444..b473274834e9 100644
--- a/include/hw/virtio/virtio-pci.h
+++ b/include/hw/virtio/virtio-pci.h
@@ -155,6 +155,7 @@ struct VirtIOPCIProxy {
uint32_t modern_io_bar_idx;
uint32_t modern_mem_bar_idx;
int config_cap;
+ uint16_t last_pcie_cap_offset;
uint32_t flags;
bool disable_modern;
bool ignore_backend_features;
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index c773a9130c7e..5ea8e7f6d0a8 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1962,6 +1962,7 @@ static void virtio_pci_device_plugged(DeviceState *d,=
Error **errp)
uint8_t *config;
uint32_t size;
VirtIODevice *vdev =3D virtio_bus_get_device(bus);
+ int16_t res;
=20
/*
* Virtio capabilities present without
@@ -2109,6 +2110,14 @@ static void virtio_pci_device_plugged(DeviceState *d=
, Error **errp)
pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx,
PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
}
+
+ res =3D pcie_sriov_pf_init_from_user_created_vfs(&proxy->pci_dev,
+ proxy->last_pcie_cap_of=
fset,
+ errp);
+ if (res > 0) {
+ proxy->last_pcie_cap_offset +=3D res;
+ virtio_add_feature(&vdev->host_features, VIRTIO_F_SR_IOV);
+ }
}
=20
static void virtio_pci_device_unplugged(DeviceState *d)
@@ -2199,7 +2208,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Er=
ror **errp)
=20
if (pcie_port && pci_is_express(pci_dev)) {
int pos;
- uint16_t last_pcie_cap_offset =3D PCI_CONFIG_SPACE_SIZE;
+ proxy->last_pcie_cap_offset =3D PCI_CONFIG_SPACE_SIZE;
=20
pos =3D pcie_endpoint_cap_init(pci_dev, 0);
assert(pos > 0);
@@ -2219,9 +2228,9 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Er=
ror **errp)
pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
=20
if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
- pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
+ pcie_aer_init(pci_dev, PCI_ERR_VER, proxy->last_pcie_cap_offse=
t,
PCI_ERR_SIZEOF, NULL);
- last_pcie_cap_offset +=3D PCI_ERR_SIZEOF;
+ proxy->last_pcie_cap_offset +=3D PCI_ERR_SIZEOF;
}
=20
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
@@ -2246,9 +2255,9 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Er=
ror **errp)
}
=20
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
- pcie_ats_init(pci_dev, last_pcie_cap_offset,
+ pcie_ats_init(pci_dev, proxy->last_pcie_cap_offset,
proxy->flags & VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED);
- last_pcie_cap_offset +=3D PCI_EXT_CAP_ATS_SIZEOF;
+ proxy->last_pcie_cap_offset +=3D PCI_EXT_CAP_ATS_SIZEOF;
}
=20
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
@@ -2276,6 +2285,7 @@ static void virtio_pci_exit(PCIDevice *pci_dev)
!pci_bus_is_root(pci_get_bus(pci_dev));
bool modern_pio =3D proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
=20
+ pcie_sriov_pf_exit(&proxy->pci_dev);
msix_uninit_exclusive_bar(pci_dev);
if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
pci_is_express(pci_dev)) {
--=20
2.47.1
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:01:00 +0900
Subject: [PATCH v8 7/9] virtio-net: Implement SR-IOV VF
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To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
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Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
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Akihiko Odaki <akihiko.odaki@daynix.com>
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A virtio-net device can be added as a SR-IOV VF to another virtio-pci
device that will be the PF.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
hw/virtio/virtio-net-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/virtio-net-pci.c b/hw/virtio/virtio-net-pci.c
index e18953ad674b..430b727ea3f4 100644
--- a/hw/virtio/virtio-net-pci.c
+++ b/hw/virtio/virtio-net-pci.c
@@ -74,6 +74,7 @@ static void virtio_net_pci_class_init(ObjectClass *klass,=
void *data)
k->device_id =3D PCI_DEVICE_ID_VIRTIO_NET;
k->revision =3D VIRTIO_PCI_ABI_VERSION;
k->class_id =3D PCI_CLASS_NETWORK_ETHERNET;
+ k->sriov_vf_user_creatable =3D true;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
device_class_set_props(dc, virtio_net_properties);
vpciklass->realize =3D virtio_net_pci_realize;
--=20
2.47.1
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:01:01 +0900
Subject: [PATCH v8 8/9] docs: Document composable SR-IOV device
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In-Reply-To: <20250104-sriov-v8-0-56144cfdc7d9@daynix.com>
To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>,
Eduardo Habkost <eduardo@habkost.net>, Jason Wang <jasowang@redhat.com>,
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Lei Yang <leiyang@redhat.com>
---
MAINTAINERS | 1 +
docs/system/index.rst | 1 +
docs/system/sriov.rst | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 38 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 38a290e9c2ce..b0821a17c4fa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2006,6 +2006,7 @@ F: hw/pci-bridge/*
F: qapi/pci.json
F: docs/pci*
F: docs/specs/*pci*
+F: docs/system/sriov.rst
=20
PCIE DOE
M: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
diff --git a/docs/system/index.rst b/docs/system/index.rst
index c21065e51932..718e9d3c56bb 100644
--- a/docs/system/index.rst
+++ b/docs/system/index.rst
@@ -39,3 +39,4 @@ or Hypervisor.Framework.
multi-process
confidential-guest-support
vm-templating
+ sriov
diff --git a/docs/system/sriov.rst b/docs/system/sriov.rst
new file mode 100644
index 000000000000..a851a66a4b8b
--- /dev/null
+++ b/docs/system/sriov.rst
@@ -0,0 +1,36 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Compsable SR-IOV device
+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+
+SR-IOV (Single Root I/O Virtualization) is an optional extended capability=
of a
+PCI Express device. It allows a single physical function (PF) to appear as
+multiple virtual functions (VFs) for the main purpose of eliminating softw=
are
+overhead in I/O from virtual machines.
+
+There are devices with predefined SR-IOV configurations, but it is also po=
ssible
+to compose an SR-IOV device yourself. Composing an SR-IOV device is curren=
tly
+only supported by virtio-net-pci.
+
+Users can configure an SR-IOV-capable virtio-net device by adding
+virtio-net-pci functions to a bus. Below is a command line example:
+
+.. code-block:: shell
+
+ -netdev user,id=3Dn -netdev user,id=3Do
+ -netdev user,id=3Dp -netdev user,id=3Dq
+ -device pcie-root-port,id=3Db
+ -device virtio-net-pci,bus=3Db,addr=3D0x0.0x3,netdev=3Dq,sriov-pf=3Df
+ -device virtio-net-pci,bus=3Db,addr=3D0x0.0x2,netdev=3Dp,sriov-pf=3Df
+ -device virtio-net-pci,bus=3Db,addr=3D0x0.0x1,netdev=3Do,sriov-pf=3Df
+ -device virtio-net-pci,bus=3Db,addr=3D0x0.0x0,netdev=3Dn,id=3Df
+
+The VFs specify the paired PF with ``sriov-pf`` property. The PF must be
+added after all VFs. It is the user's responsibility to ensure that VFs ha=
ve
+function numbers larger than one of the PF, and that the function numbers
+have a consistent stride.
+
+You may also need to perform additional steps to activate the SR-IOV featu=
re on
+your guest. For Linux, refer to [1]_.
+
+.. [1] https://docs.kernel.org/PCI/pci-iov-howto.html
--=20
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: Sat, 04 Jan 2025 17:01:02 +0900
Subject: [PATCH v8 9/9] pcie_sriov: Make a PCI device with user-created VF
ARI-capable
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To: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Alex Williamson <alex.williamson@redhat.com>,
=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>,
Eduardo Habkost <eduardo@habkost.net>, Jason Wang <jasowang@redhat.com>,
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>,
Keith Busch <kbusch@kernel.org>, Klaus Jensen <its@irrelevant.dk>
Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, devel@daynix.com,
Yui Washizu <yui.washidu@gmail.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>
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---
docs/system/sriov.rst | 3 ++-
include/hw/pci/pcie_sriov.h | 7 +++++--
hw/pci/pcie_sriov.c | 8 +++++++-
hw/virtio/virtio-pci.c | 16 ++++++++++------
4 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/docs/system/sriov.rst b/docs/system/sriov.rst
index a851a66a4b8b..d12178f3c319 100644
--- a/docs/system/sriov.rst
+++ b/docs/system/sriov.rst
@@ -28,7 +28,8 @@ virtio-net-pci functions to a bus. Below is a command lin=
e example:
The VFs specify the paired PF with ``sriov-pf`` property. The PF must be
added after all VFs. It is the user's responsibility to ensure that VFs ha=
ve
function numbers larger than one of the PF, and that the function numbers
-have a consistent stride.
+have a consistent stride. Both the PF and VFs are ARI-capable so you can h=
ave
+255 VFs at maximum.
=20
You may also need to perform additional steps to activate the SR-IOV featu=
re on
your guest. For Linux, refer to [1]_.
diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h
index f75b8f22ee92..aeaa38cf3456 100644
--- a/include/hw/pci/pcie_sriov.h
+++ b/include/hw/pci/pcie_sriov.h
@@ -43,12 +43,15 @@ void pcie_sriov_vf_register_bar(PCIDevice *dev, int reg=
ion_num,
=20
/**
* pcie_sriov_pf_init_from_user_created_vfs() - Initialize PF with user-cr=
eated
- * VFs.
+ * VFs, adding ARI to PF
* @dev: A PCIe device being realized.
* @offset: The offset of the SR-IOV capability.
* @errp: pointer to Error*, to store an error if it happens.
*
- * Return: The size of added capability. 0 if the user did not create VFs.
+ * Initializes a PF with user-created VFs, adding the ARI extended capabil=
ity to
+ * the PF. The VFs should call pcie_ari_init() to form an ARI device.
+ *
+ * Return: The size of added capabilities. 0 if the user did not create VF=
s.
* -1 if failed.
*/
int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev,
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index 08f707e847fd..3ad18744f4a8 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sriov.c
@@ -245,6 +245,7 @@ int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDev=
ice *dev,
PCIDevice **vfs;
BusState *bus =3D qdev_get_parent_bus(DEVICE(dev));
uint16_t ven_id =3D pci_get_word(dev->config + PCI_VENDOR_ID);
+ uint16_t size =3D PCI_EXT_CAP_SRIOV_SIZEOF;
uint16_t vf_dev_id;
uint16_t vf_offset;
uint16_t vf_stride;
@@ -311,6 +312,11 @@ int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDe=
vice *dev,
return -1;
}
=20
+ if (!pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI)) {
+ pcie_ari_init(dev, offset + size);
+ size +=3D PCI_ARI_SIZEOF;
+ }
+
for (i =3D 0; i < pf->len; i++) {
vfs[i]->exp.sriov_vf.pf =3D dev;
vfs[i]->exp.sriov_vf.vf_number =3D i;
@@ -331,7 +337,7 @@ int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDev=
ice *dev,
}
}
=20
- return PCI_EXT_CAP_SRIOV_SIZEOF;
+ return size;
}
=20
bool pcie_sriov_register_device(PCIDevice *dev, Error **errp)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 5ea8e7f6d0a8..e3ac5543195a 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -2111,12 +2111,16 @@ static void virtio_pci_device_plugged(DeviceState *=
d, Error **errp)
PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
}
=20
- res =3D pcie_sriov_pf_init_from_user_created_vfs(&proxy->pci_dev,
- proxy->last_pcie_cap_of=
fset,
- errp);
- if (res > 0) {
- proxy->last_pcie_cap_offset +=3D res;
- virtio_add_feature(&vdev->host_features, VIRTIO_F_SR_IOV);
+ if (pci_is_vf(&proxy->pci_dev)) {
+ pcie_ari_init(&proxy->pci_dev, proxy->last_pcie_cap_offset);
+ proxy->last_pcie_cap_offset +=3D PCI_ARI_SIZEOF;
+ } else {
+ res =3D pcie_sriov_pf_init_from_user_created_vfs(
+ &proxy->pci_dev, proxy->last_pcie_cap_offset, errp);
+ if (res > 0) {
+ proxy->last_pcie_cap_offset +=3D res;
+ virtio_add_feature(&vdev->host_features, VIRTIO_F_SR_IOV);
+ }
}
}
=20
--=20
2.47.1