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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c848a47sm33074712f8f.62.2024.12.31.11.06.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 31 Dec 2024 11:06:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735671992; x=1736276792; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OPnjzUL72sgItT6b5Sz5QnXH2c6Pz/4KB/mKuiBnROI=; b=vCTk8W1mwrNuq3Mfj67N/sMSrfmhOwHT8y2qJ+Yb71mIsLcB0kt81UMRyMg0IbXmP7 OAXNpMGMWRzN8dN4ndOZk367RMdcnhaJFQmI9fHwEy50K5VtdXIgTLBZjZ8UNasAuSbc SpzvFrFdCdPs90ddqJYiQPSSuR0stzfVUSyr1k0oBay4zZAjNnahLESO917lPm6zH51a xStqCG+29x6Vh+Y5DrjzU1VEu4P8WlgOrgitS0blgOVB/d/MKEy6ZGNF/6lgYz1mJcnp Vsyz4ZPrgvGJZhlTtUV8hkSui2XlIGfSt2RdHcfdNKpnA5kdsFUAXJ3YAslmHcdKIRBO VnHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735671992; x=1736276792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OPnjzUL72sgItT6b5Sz5QnXH2c6Pz/4KB/mKuiBnROI=; b=oLWo+gjPBVXXx+a/AuTbc24Eg9dZK3KtH+muRxprg5DB/N1hQQQfges8NJKALeFjMq 8yccUgxoGyJjYSw0PVOF29/W/8NnadqUEb6IVSdjklPsnMGpZ9Wyzcz8QFT/GFZQJoW0 zy1LWRCb3tU4fVdfYiOR8maZjrG8/6u3n7u7dmVxcjU6UZNVCVvLvGSmHzx84In/xwZq W196U4pt5uC/3HLQPIkArGqiDUA7PO3UG54TobOVz14ACuR8sVVdc2DDEElDo4MKL3lQ zoKNolL+T6lvPQlKVJwrWJL4OdWW1875XdeUtHdWZpqWVSquhOd9NYDiYHDwhqSYoc3z +hDw== X-Gm-Message-State: AOJu0YwVuu8TWjnaTfyLC9Sub7Kndhrgig7CJKv4k4BJxquUrPBKeEVw Uf8mnDXll/yVCpwpXhJBudUaIZOK9lvxOM8fgXhf2VpFoNAalZQkJxIBoJYJ1BkTROTqo2gI1LY ziZQ= X-Gm-Gg: ASbGncupTvC3Yw3n37Wo9D09W1TPnLEsXJC321jOxpK00TeNlO2OplQofKxo85uHgvZ DwAz8q8dkCmqVtR49XA7quchESgto4JtTXRI5U5SpyDJJzbt81NDsaRvK+9l6NFl36BkxPdXTt5 Bvt2YMfyya6Q9PXi/KQyDFFgs5oSLRQ0JmMyuvzaco62IfwCmOMccbdv4dvwwhkshGRbF4jIIzx q8pYMsQ0FRgUNwpNVYOUSUbj6PtpuJQbGx5Rsv5gw1w/hbGak7tmDYBZTu+5uqn6UQ+nUV7V0jf mzHlLj9A4qQvCtP+IowgFtAL6qY62dY= X-Google-Smtp-Source: AGHT+IGwC6Y4XguVKkslsd1B5A1dSsN166LHpmC76L+VqO3R2P2NCmUZqlRGThOA0bOfFuVJKkB5Yg== X-Received: by 2002:a5d:59ae:0:b0:385:f64e:f177 with SMTP id ffacd0b85a97d-38a22a11925mr32527923f8f.11.1735671992627; Tue, 31 Dec 2024 11:06:32 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 2/6] target/hppa: Convert hppa_cpu_init() to ResetHold handler Date: Tue, 31 Dec 2024 20:06:16 +0100 Message-ID: <20241231190620.24442-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231190620.24442-1-philmd@linaro.org> References: <20241231190620.24442-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1735672052788019100 From: Helge Deller hppa_cpu_initfn() is called once when a HPPA CPU instance is initialized, but it sets fields which should be set each time a CPU resets. Rename it as a reset handler, having it matching the ResettablePhases::hold() signature, and register it as ResettableClass handler. Since on reset the CPU registers and TLB entries are expected to be zero, add a memset() call clearing CPUHPPAState up to the &end_reset_fields marker. Signed-off-by: Helge Deller Co-developed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/cpu.h | 5 +++++ target/hppa/cpu.c | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 22a6510e087..c1d69c1a835 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -263,6 +263,9 @@ typedef struct CPUArchState { IntervalTreeRoot tlb_root; =20 HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; } CPUHPPAState; =20 /** @@ -281,6 +284,7 @@ struct ArchCPU { /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. * * An HPPA CPU model. */ @@ -288,6 +292,7 @@ struct HPPACPUClass { CPUClass parent_class; =20 DeviceRealize parent_realize; + ResettablePhases parent_phases; }; =20 #include "exec/cpu-all.h" diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 47d01609557..d784bcdd602 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -193,13 +193,20 @@ static void hppa_cpu_realizefn(DeviceState *dev, Erro= r **errp) tcg_cflags_set(cs, CF_PCREL); } =20 -static void hppa_cpu_initfn(Object *obj) +static void hppa_cpu_reset_hold(Object *obj, ResetType type) { + HPPACPUClass *scc =3D HPPA_CPU_GET_CLASS(obj); CPUState *cs =3D CPU(obj); HPPACPU *cpu =3D HPPA_CPU(obj); CPUHPPAState *env =3D &cpu->env; =20 + if (scc->parent_phases.hold) { + scc->parent_phases.hold(obj, type); + } cs->exception_index =3D -1; + + memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); + cpu_hppa_loaded_fr0(env); cpu_hppa_put_psw(env, PSW_W); } @@ -242,10 +249,14 @@ static void hppa_cpu_class_init(ObjectClass *oc, void= *data) DeviceClass *dc =3D DEVICE_CLASS(oc); CPUClass *cc =3D CPU_CLASS(oc); HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); + ResettableClass *rc =3D RESETTABLE_CLASS(oc); =20 device_class_set_parent_realize(dc, hppa_cpu_realizefn, &acc->parent_realize); =20 + resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL, + &acc->parent_phases); + cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; cc->mmu_index =3D hppa_cpu_mmu_index; @@ -269,7 +280,6 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(HPPACPU), .instance_align =3D __alignof(HPPACPU), - .instance_init =3D hppa_cpu_initfn, .abstract =3D false, .class_size =3D sizeof(HPPACPUClass), .class_init =3D hppa_cpu_class_init, --=20 2.47.1