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Tue, 31 Dec 2024 07:20:02 -0800 (PST) From: Tomita Moeko To: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: qemu-devel@nongnu.org, Tomita Moeko Subject: [PATCH 1/3] vfio/pci: declare generic quirks in a new header file Date: Tue, 31 Dec 2024 23:19:51 +0800 Message-ID: <20241231151953.59992-2-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241231151953.59992-1-tomitamoeko@gmail.com> References: <20241231151953.59992-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1735658470265019100 Content-Type: text/plain; charset="utf-8" Declare generic vfio_generic_{window_address,window_data,mirror}_quirk in newly created pci_quirks.h so that they can be used elsewhere, like igd.c. Signed-off-by: Tomita Moeko --- hw/vfio/pci-quirks.c | 59 ++++-------------------------------- hw/vfio/pci-quirks.h | 71 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 53 deletions(-) create mode 100644 hw/vfio/pci-quirks.h diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index c8e60475d5..bb2ce1d904 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -25,6 +25,7 @@ #include "hw/nvram/fw_cfg.h" #include "hw/qdev-properties.h" #include "pci.h" +#include "pci-quirks.h" #include "trace.h" =20 /* @@ -66,40 +67,6 @@ bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev) * Device specific region quirks (mostly backdoors to PCI config space) */ =20 -/* - * The generic window quirks operate on an address and data register, - * vfio_generic_window_address_quirk handles the address register and - * vfio_generic_window_data_quirk handles the data register. These ops - * pass reads and writes through to hardware until a value matching the - * stored address match/mask is written. When this occurs, the data - * register access emulated PCI config space for the device rather than - * passing through accesses. This enables devices where PCI config space - * is accessible behind a window register to maintain the virtualization - * provided through vfio. - */ -typedef struct VFIOConfigWindowMatch { - uint32_t match; - uint32_t mask; -} VFIOConfigWindowMatch; - -typedef struct VFIOConfigWindowQuirk { - struct VFIOPCIDevice *vdev; - - uint32_t address_val; - - uint32_t address_offset; - uint32_t data_offset; - - bool window_enabled; - uint8_t bar; - - MemoryRegion *addr_mem; - MemoryRegion *data_mem; - - uint32_t nr_matches; - VFIOConfigWindowMatch matches[]; -} VFIOConfigWindowQuirk; - static uint64_t vfio_generic_window_quirk_address_read(void *opaque, hwaddr addr, unsigned size) @@ -135,7 +102,7 @@ static void vfio_generic_window_quirk_address_write(voi= d *opaque, hwaddr addr, } } =20 -static const MemoryRegionOps vfio_generic_window_address_quirk =3D { +const MemoryRegionOps vfio_generic_window_address_quirk =3D { .read =3D vfio_generic_window_quirk_address_read, .write =3D vfio_generic_window_quirk_address_write, .endianness =3D DEVICE_LITTLE_ENDIAN, @@ -178,26 +145,12 @@ static void vfio_generic_window_quirk_data_write(void= *opaque, hwaddr addr, addr + window->data_offset, data, size); } =20 -static const MemoryRegionOps vfio_generic_window_data_quirk =3D { +const MemoryRegionOps vfio_generic_window_data_quirk =3D { .read =3D vfio_generic_window_quirk_data_read, .write =3D vfio_generic_window_quirk_data_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -/* - * The generic mirror quirk handles devices which expose PCI config space - * through a region within a BAR. When enabled, reads and writes are - * redirected through to emulated PCI config space. XXX if PCI config spa= ce - * used memory regions, this could just be an alias. - */ -typedef struct VFIOConfigMirrorQuirk { - struct VFIOPCIDevice *vdev; - uint32_t offset; - uint8_t bar; - MemoryRegion *mem; - uint8_t data[]; -} VFIOConfigMirrorQuirk; - static uint64_t vfio_generic_quirk_mirror_read(void *opaque, hwaddr addr, unsigned size) { @@ -228,7 +181,7 @@ static void vfio_generic_quirk_mirror_write(void *opaqu= e, hwaddr addr, addr, data); } =20 -static const MemoryRegionOps vfio_generic_mirror_quirk =3D { +const MemoryRegionOps vfio_generic_mirror_quirk =3D { .read =3D vfio_generic_quirk_mirror_read, .write =3D vfio_generic_quirk_mirror_write, .endianness =3D DEVICE_LITTLE_ENDIAN, @@ -1499,7 +1452,7 @@ static void get_nv_gpudirect_clique_id(Object *obj, V= isitor *v, const char *name, void *opaque, Error **errp) { - const Property *prop =3D opaque; + Property *prop =3D opaque; uint8_t *ptr =3D object_field_prop_ptr(obj, prop); =20 visit_type_uint8(v, name, ptr, errp); @@ -1509,7 +1462,7 @@ static void set_nv_gpudirect_clique_id(Object *obj, V= isitor *v, const char *name, void *opaque, Error **errp) { - const Property *prop =3D opaque; + Property *prop =3D opaque; uint8_t value, *ptr =3D object_field_prop_ptr(obj, prop); =20 if (!visit_type_uint8(v, name, &value, errp)) { diff --git a/hw/vfio/pci-quirks.h b/hw/vfio/pci-quirks.h new file mode 100644 index 0000000000..c0e96a01cc --- /dev/null +++ b/hw/vfio/pci-quirks.h @@ -0,0 +1,71 @@ +/* + * vfio generic region quirks (mostly backdoors to PCI config space) + * + * Copyright Red Hat, Inc. 2012-2015 + * + * Authors: + * Alex Williamson + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ +#ifndef HW_VFIO_VFIO_PCI_QUIRKS_H +#define HW_VFIO_VFIO_PCI_QUIRKS_H + +#include "qemu/osdep.h" +#include "exec/memop.h" + +/* + * The generic window quirks operate on an address and data register, + * vfio_generic_window_address_quirk handles the address register and + * vfio_generic_window_data_quirk handles the data register. These ops + * pass reads and writes through to hardware until a value matching the + * stored address match/mask is written. When this occurs, the data + * register access emulated PCI config space for the device rather than + * passing through accesses. This enables devices where PCI config space + * is accessible behind a window register to maintain the virtualization + * provided through vfio. + */ +typedef struct VFIOConfigWindowMatch { + uint32_t match; + uint32_t mask; +} VFIOConfigWindowMatch; + +typedef struct VFIOConfigWindowQuirk { + struct VFIOPCIDevice *vdev; + + uint32_t address_val; + + uint32_t address_offset; + uint32_t data_offset; + + bool window_enabled; + uint8_t bar; + + MemoryRegion *addr_mem; + MemoryRegion *data_mem; + + uint32_t nr_matches; + VFIOConfigWindowMatch matches[]; +} VFIOConfigWindowQuirk; + +extern const MemoryRegionOps vfio_generic_window_address_quirk; +extern const MemoryRegionOps vfio_generic_window_data_quirk; + +/* + * The generic mirror quirk handles devices which expose PCI config space + * through a region within a BAR. When enabled, reads and writes are + * redirected through to emulated PCI config space. XXX if PCI config spa= ce + * used memory regions, this could just be an alias. + */ +typedef struct VFIOConfigMirrorQuirk { + struct VFIOPCIDevice *vdev; + uint32_t offset; + uint8_t bar; + MemoryRegion *mem; + uint8_t data[]; +} VFIOConfigMirrorQuirk; + +extern const MemoryRegionOps vfio_generic_mirror_quirk; + +#endif /* HW_VFIO_VFIO_PCI_QUIRKS_H */ --=20 2.45.2 From nobody Tue Feb 10 04:18:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1735658481; cv=none; d=zohomail.com; s=zohoarc; b=Z3gaU67BDtkxk1OmOdwEMAnjex9W/aKJ5m4Mawn2AHAeTDP/BUoUuZSJ5SUietwq3myhFAlExgJo89SsK5IMMmnQvxajR9yLfJQi/e+IQv0/CP/2B6YBp3l079RV7x4xdy0AIfmnPSVaezkYOl157YZ9eL4MZEESV2Hd1IZhkiE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Tue, 31 Dec 2024 07:20:04 -0800 (PST) From: Tomita Moeko To: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: qemu-devel@nongnu.org, Tomita Moeko Subject: [PATCH 2/3] vfio/pci: introduce config_offset field in VFIOConfigMirrorQuirk Date: Tue, 31 Dec 2024 23:19:52 +0800 Message-ID: <20241231151953.59992-3-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241231151953.59992-1-tomitamoeko@gmail.com> References: <20241231151953.59992-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1735658482622019100 Content-Type: text/plain; charset="utf-8" Device may only expose a specific portion of PCI config space through a region in a BAR, such behavior is seen in igd GGC and BDSM mirrors in BAR0. To handle these, config_offset is introduced to allow mirroring arbitrary region in PCI config space. Signed-off-by: Tomita Moeko --- hw/vfio/pci-quirks.c | 5 +++++ hw/vfio/pci-quirks.h | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index bb2ce1d904..5a0b25a544 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -162,6 +162,7 @@ static uint64_t vfio_generic_quirk_mirror_read(void *op= aque, (void)vfio_region_read(&vdev->bars[mirror->bar].region, addr + mirror->offset, size); =20 + addr +=3D mirror->config_offset; data =3D vfio_pci_read_config(&vdev->pdev, addr, size); trace_vfio_quirk_generic_mirror_read(vdev->vbasedev.name, memory_region_name(mirror->mem), @@ -175,6 +176,7 @@ static void vfio_generic_quirk_mirror_write(void *opaqu= e, hwaddr addr, VFIOConfigMirrorQuirk *mirror =3D opaque; VFIOPCIDevice *vdev =3D mirror->vdev; =20 + addr +=3D mirror->config_offset; vfio_pci_write_config(&vdev->pdev, addr, data, size); trace_vfio_quirk_generic_mirror_write(vdev->vbasedev.name, memory_region_name(mirror->mem), @@ -456,6 +458,7 @@ static void vfio_probe_ati_bar2_quirk(VFIOPCIDevice *vd= ev, int nr) mirror->mem =3D quirk->mem; mirror->vdev =3D vdev; mirror->offset =3D 0x4000; + mirror->config_offset =3D 0; mirror->bar =3D nr; =20 memory_region_init_io(mirror->mem, OBJECT(vdev), @@ -908,6 +911,7 @@ static void vfio_probe_nvidia_bar0_quirk(VFIOPCIDevice = *vdev, int nr) mirror->mem =3D quirk->mem; mirror->vdev =3D vdev; mirror->offset =3D 0x88000; + mirror->config_offset =3D 0; mirror->bar =3D nr; last =3D (LastDataSet *)&mirror->data; last->quirk =3D quirk; @@ -929,6 +933,7 @@ static void vfio_probe_nvidia_bar0_quirk(VFIOPCIDevice = *vdev, int nr) mirror->mem =3D quirk->mem; mirror->vdev =3D vdev; mirror->offset =3D 0x1800; + mirror->config_offset =3D 0; mirror->bar =3D nr; last =3D (LastDataSet *)&mirror->data; last->quirk =3D quirk; diff --git a/hw/vfio/pci-quirks.h b/hw/vfio/pci-quirks.h index c0e96a01cc..d1532e379b 100644 --- a/hw/vfio/pci-quirks.h +++ b/hw/vfio/pci-quirks.h @@ -60,7 +60,8 @@ extern const MemoryRegionOps vfio_generic_window_data_qui= rk; */ typedef struct VFIOConfigMirrorQuirk { struct VFIOPCIDevice *vdev; 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Tue, 31 Dec 2024 07:20:06 -0800 (PST) From: Tomita Moeko To: Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: qemu-devel@nongnu.org, Tomita Moeko Subject: [PATCH 3/3] vfio/igd: use VFIOConfigMirrorQuirk for mirrored registers Date: Tue, 31 Dec 2024 23:19:53 +0800 Message-ID: <20241231151953.59992-4-tomitamoeko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241231151953.59992-1-tomitamoeko@gmail.com> References: <20241231151953.59992-1-tomitamoeko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=tomitamoeko@gmail.com; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1735658470232019100 Content-Type: text/plain; charset="utf-8" With the introduction of config_offset field, VFIOConfigMirrorQuirk can now be used for those mirrored register in igd bar0. This eliminates the need for the macro intoduced in 1a2623b5c9e7 ("vfio/igd: add macro for declaring mirrored registers"). Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 128 ++++++++++++++------------------------------------ 1 file changed, 36 insertions(+), 92 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index f5414b0f8d..28a1d17f01 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -18,6 +18,7 @@ #include "hw/hw.h" #include "hw/nvram/fw_cfg.h" #include "pci.h" +#include "pci-quirks.h" #include "trace.h" =20 /* @@ -422,84 +423,21 @@ static const MemoryRegionOps vfio_igd_index_quirk =3D= { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -static uint64_t vfio_igd_pci_config_read(VFIOPCIDevice *vdev, uint64_t off= set, - unsigned size) -{ - switch (size) { - case 1: - return pci_get_byte(vdev->pdev.config + offset); - case 2: - return pci_get_word(vdev->pdev.config + offset); - case 4: - return pci_get_long(vdev->pdev.config + offset); - case 8: - return pci_get_quad(vdev->pdev.config + offset); - default: - hw_error("igd: unsupported pci config read at %"PRIx64", size %u", - offset, size); - break; - } - - return 0; -} - -static void vfio_igd_pci_config_write(VFIOPCIDevice *vdev, uint64_t offset, - uint64_t data, unsigned size) -{ - switch (size) { - case 1: - pci_set_byte(vdev->pdev.config + offset, data); - break; - case 2: - pci_set_word(vdev->pdev.config + offset, data); - break; - case 4: - pci_set_long(vdev->pdev.config + offset, data); - break; - case 8: - pci_set_quad(vdev->pdev.config + offset, data); - break; - default: - hw_error("igd: unsupported pci config write at %"PRIx64", size %u", - offset, size); - break; - } -} - -#define VFIO_IGD_QUIRK_MIRROR_REG(reg, name) \ -static uint64_t vfio_igd_quirk_read_##name(void *opaque, \ - hwaddr addr, unsigned size) \ -{ \ - VFIOPCIDevice *vdev =3D opaque; \ - \ - return vfio_igd_pci_config_read(vdev, reg + addr, size); \ -} \ - \ -static void vfio_igd_quirk_write_##name(void *opaque, hwaddr addr, \ - uint64_t data, unsigned size) \ -{ \ - VFIOPCIDevice *vdev =3D opaque; \ - \ - vfio_igd_pci_config_write(vdev, reg + addr, data, size); \ -} \ - \ -static const MemoryRegionOps vfio_igd_quirk_mirror_##name =3D { \ - .read =3D vfio_igd_quirk_read_##name, \ - .write =3D vfio_igd_quirk_write_##name, \ - .endianness =3D DEVICE_LITTLE_ENDIAN, \ -}; - -VFIO_IGD_QUIRK_MIRROR_REG(IGD_GMCH, ggc) -VFIO_IGD_QUIRK_MIRROR_REG(IGD_BDSM, bdsm) -VFIO_IGD_QUIRK_MIRROR_REG(IGD_BDSM_GEN11, bdsm64) - #define IGD_GGC_MMIO_OFFSET 0x108040 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 =20 +typedef struct VFIOIGDBAR0Quirk { + VFIOConfigMirrorQuirk ggc_mirror; + VFIOConfigMirrorQuirk bdsm_mirror; +} VFIOIGDBAR0Quirk; + void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) { VFIOQuirk *quirk; + VFIOIGDBAR0Quirk *bar0; + VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror; int gen; + uint32_t bdsm_reg_size; =20 /* * This must be an Intel VGA device at address 00:02.0 for us to even @@ -523,30 +461,36 @@ void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, i= nt nr) } =20 quirk =3D vfio_quirk_alloc(2); - quirk->data =3D vdev; - - memory_region_init_io(&quirk->mem[0], OBJECT(vdev), - &vfio_igd_quirk_mirror_ggc, vdev, + bar0 =3D quirk->data =3D g_malloc0(sizeof(*bar0)); + + ggc_mirror =3D &bar0->ggc_mirror; + ggc_mirror->vdev =3D vdev; + ggc_mirror->mem =3D &quirk->mem[0]; + ggc_mirror->bar =3D nr; + ggc_mirror->offset =3D IGD_GGC_MMIO_OFFSET; + ggc_mirror->config_offset =3D IGD_GMCH; + + bdsm_mirror =3D &bar0->bdsm_mirror; + bdsm_mirror->mem =3D &quirk->mem[1]; + bdsm_mirror->vdev =3D vdev; + bdsm_mirror->offset =3D IGD_BDSM_MMIO_OFFSET; + bdsm_mirror->config_offset =3D (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11; + bdsm_mirror->bar =3D nr; + bdsm_reg_size =3D (gen < 11) ? 4 : 8; + + memory_region_init_io(ggc_mirror->mem, OBJECT(vdev), + &vfio_generic_mirror_quirk, ggc_mirror, "vfio-igd-ggc-quirk", 2); - memory_region_add_subregion_overlap(vdev->bars[0].region.mem, - IGD_GGC_MMIO_OFFSET, &quirk->mem[0= ], + memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, + ggc_mirror->offset, ggc_mirror->me= m, 1); =20 - if (gen < 11) { - memory_region_init_io(&quirk->mem[1], OBJECT(vdev), - &vfio_igd_quirk_mirror_bdsm, vdev, - "vfio-igd-bdsm-quirk", 4); - memory_region_add_subregion_overlap(vdev->bars[0].region.mem, - IGD_BDSM_MMIO_OFFSET, - &quirk->mem[1], 1); - } else { - memory_region_init_io(&quirk->mem[1], OBJECT(vdev), - &vfio_igd_quirk_mirror_bdsm64, vdev, - "vfio-igd-bdsm-quirk", 8); - memory_region_add_subregion_overlap(vdev->bars[0].region.mem, - IGD_BDSM_MMIO_OFFSET, - &quirk->mem[1], 1); - } + memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev), + &vfio_generic_mirror_quirk, bdsm_mirror, + "vfio-igd-bdsm-quirk", bdsm_reg_size); + memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, + bdsm_mirror->offset, bdsm_mirror->= mem, + 1); =20 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); } --=20 2.45.2