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[109.42.49.90]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0e895194sm1329218666b.70.2024.12.28.23.26.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Dec 2024 23:26:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735457209; x=1736062009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8g4JDK2gP7kBGIRp58PLikXD1WmmiHmJeQox3/MKTjs=; b=m5xNMUTUgfBgw91/9PWAvUwUYBPXBMXyxGx6E8GaqacxD/ud7V3tBw/J2LlVFJiG5e KjCvq/8NkngP/NHpcC5+21UuveYXt2HldAN0477qIK6YlRo3+at5/rXMqThH4CV9gyyt kFM6W+kLXUgUDN/MlWXSVNUh/3XPAoLBd+TVQM8sd7WfMQl48jYGZc6ATI/eYHS0Jivy wKBZ2TxphqLc+2Knk07PRPk2ijUe3qbTCmuXVDsrCtNdn0/erIQBFwndMFQsZx93vZcC zMNpAx8z+ATPGe4NogyMuc+awZEh9UA0RGBGeDgqX0AnIU0/R9hUomAcJ02Tfix+1H79 rwcQ== X-Forwarded-Encrypted: i=1; AJvYcCVk1OqycUmdZkGH5UTVxTV5BkgxUrVfe+2k4YU6CldL3g6FS4WWU2lnITdriTtN1cuU8qu2cMMZ+s34@nongnu.org X-Gm-Message-State: AOJu0YymN3SMJ/JOgXTSFXEH7Zd/3Z+osLnqoWpkQgbB5bqSdY8Knf9B KbMQvLUmxDFTaqgGNVQ5YChPBDXiy2d/KnggAG/eYQ+1KCDBsluu X-Gm-Gg: ASbGnctpY1KcDEF3edg/0QEpIA3C/WuFYkrjNNQl3I/J2mAXA3vL1FIp/Lw23OwKFIW mkiIV/+otYsGoauRkqavHACkR9swOF5qFQOeZ3iMxxkiCN3CE8VbC67QuUGbuKW2KPhOkYgZmMJ w4VuWsfsY3cWnM+t8xZMYgqjd8Tiw3vLZxLwX2HAYtXEhey+X1pD1ZfEtDD8EvchYDsWiMuezx/ 9LDAx6/nNyZwyUUDGDTEmWorjHw1UbH1njrUdADsigKC70vJyoHEMgDS/klUUOJ2GX0iJe8nZ1T g1I= X-Google-Smtp-Source: AGHT+IGP457vSLVn1pcZ7UqdRH1rB2XcUREvQNpeqwpJNge7QAz3g4s2hjFyW0skv/h/6ylILhAqaA== X-Received: by 2002:a17:907:3da0:b0:aab:cd45:5d3c with SMTP id a640c23a62f3a-aac33685df3mr2770574866b.50.1735457209031; Sat, 28 Dec 2024 23:26:49 -0800 (PST) From: Thomas Huth To: Stefan Hajnoczi , qemu-devel@nongnu.org Subject: [PULL 10/35] next-cube: move SCSI 4020/4021 logic from next-pc device to next-scsi device Date: Sun, 29 Dec 2024 08:25:01 +0100 Message-ID: <20241229072526.166555-11-huth@tuxfamily.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241229072526.166555-1-huth@tuxfamily.org> References: <20241229072526.166555-1-huth@tuxfamily.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.218.46; envelope-from=th.huth@gmail.com; helo=mail-ej1-f46.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.156, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1735457760848116600 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland The SCSI 4020/4021 logic refers to the offset of the SCSI CSRs within the N= eXTCube address space. Due to the previously overlapping memory regions, there were duplicate MMIO accessors in the next.scr memory region for these registers = but this has now been resolved. Move the remaining SCSI 4020/4021 logic from the next-pc device to the next= -scsi device, with the exception that the SCSI 4021 register now returns its prev= ious value like a normal register instead of a hardcoded 0x40 value. This also m= atches how the registers are implemented in the Previous emulator. Signed-off-by: Mark Cave-Ayland Reviewed-by: Thomas Huth Message-ID: <20241222130012.1013374-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth --- hw/m68k/next-cube.c | 139 ++++++++++++++++++++------------------------ 1 file changed, 62 insertions(+), 77 deletions(-) diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 687d1b3cb0..402e268f6b 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -365,8 +365,6 @@ static const MemoryRegionOps next_mmio_ops =3D { =20 static uint64_t next_scr_readfn(void *opaque, hwaddr addr, unsigned size) { - NeXTPC *s =3D NEXT_PC(opaque); - NeXTSCSI *ns =3D NEXT_SCSI(&s->next_scsi); uint64_t val; =20 switch (addr) { @@ -375,16 +373,6 @@ static uint64_t next_scr_readfn(void *opaque, hwaddr a= ddr, unsigned size) val =3D 0x40 | 0x04 | 0x2 | 0x1; break; =20 - case 0x14020: - DPRINTF("SCSI 4020 STATUS READ %X\n", ns->scsi_csr_1); - val =3D ns->scsi_csr_1; - break; - - case 0x14021: - DPRINTF("SCSI 4021 STATUS READ %X\n", ns->scsi_csr_2); - val =3D 0x40; - break; - /* * These 4 registers are the hardware timer, not sure which register * is the latch instead of data, but no problems so far. @@ -413,9 +401,6 @@ static uint64_t next_scr_readfn(void *opaque, hwaddr ad= dr, unsigned size) static void next_scr_writefn(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - NeXTPC *s =3D NEXT_PC(opaque); - NeXTSCSI *ns =3D NEXT_SCSI(&s->next_scsi); - switch (addr) { case 0x14108: DPRINTF("FDCSR Write: %"PRIx64 "\n", val); @@ -424,68 +409,6 @@ static void next_scr_writefn(void *opaque, hwaddr addr= , uint64_t val, } break; =20 - case 0x14020: /* SCSI Control Register */ - if (val & SCSICSR_FIFOFL) { - DPRINTF("SCSICSR FIFO Flush\n"); - /* will have to add another irq to the esp if this is needed */ - /* esp_puflush_fifo(esp_g); */ - } - - if (val & SCSICSR_ENABLE) { - DPRINTF("SCSICSR Enable\n"); - /* - * qemu_irq_raise(s->scsi_dma); - * s->scsi_csr_1 =3D 0xc0; - * s->scsi_csr_1 |=3D 0x1; - * qemu_irq_pulse(s->scsi_dma); - */ - } - /* - * else - * s->scsi_csr_1 &=3D ~SCSICSR_ENABLE; - */ - - if (val & SCSICSR_RESET) { - DPRINTF("SCSICSR Reset\n"); - /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ - qemu_irq_raise(s->scsi_reset); - ns->scsi_csr_1 &=3D ~(SCSICSR_INTMASK | 0x80 | 0x1); - qemu_irq_lower(s->scsi_reset); - } - if (val & SCSICSR_DMADIR) { - DPRINTF("SCSICSR DMAdir\n"); - } - if (val & SCSICSR_CPUDMA) { - DPRINTF("SCSICSR CPUDMA\n"); - /* qemu_irq_raise(s->scsi_dma); */ - s->int_status |=3D 0x4000000; - } else { - /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ - s->int_status &=3D ~(0x4000000); - /* qemu_irq_lower(s->scsi_dma); */ - } - if (val & SCSICSR_INTMASK) { - DPRINTF("SCSICSR INTMASK\n"); - /* - * int_mask &=3D ~0x1000; - * s->scsi_csr_1 |=3D val; - * s->scsi_csr_1 &=3D ~SCSICSR_INTMASK; - * if (s->scsi_queued) { - * s->scsi_queued =3D 0; - * next_irq(s, NEXT_SCSI_I, level); - * } - */ - } else { - /* int_mask |=3D 0x1000; */ - } - if (val & 0x80) { - /* int_mask |=3D 0x1000; */ - /* s->scsi_csr_1 |=3D 0x80; */ - } - DPRINTF("SCSICSR Write: %"PRIx64 "\n", val); - /* s->scsi_csr_1 =3D val; */ - break; - /* Hardware timer latch - not implemented yet */ case 0x1a000: default: @@ -846,13 +769,73 @@ static void next_scsi_csr_write(void *opaque, hwaddr = addr, uint64_t val, unsigned size) { NeXTSCSI *s =3D NEXT_SCSI(opaque); + NeXTPC *pc =3D NEXT_PC(container_of(s, NeXTPC, next_scsi)); =20 switch (addr) { case 0: + if (val & SCSICSR_FIFOFL) { + DPRINTF("SCSICSR FIFO Flush\n"); + /* will have to add another irq to the esp if this is needed */ + /* esp_puflush_fifo(esp_g); */ + } + + if (val & SCSICSR_ENABLE) { + DPRINTF("SCSICSR Enable\n"); + /* + * qemu_irq_raise(s->scsi_dma); + * s->scsi_csr_1 =3D 0xc0; + * s->scsi_csr_1 |=3D 0x1; + * qemu_irq_pulse(s->scsi_dma); + */ + } + /* + * else + * s->scsi_csr_1 &=3D ~SCSICSR_ENABLE; + */ + + if (val & SCSICSR_RESET) { + DPRINTF("SCSICSR Reset\n"); + /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ + qemu_irq_raise(pc->scsi_reset); + s->scsi_csr_1 &=3D ~(SCSICSR_INTMASK | 0x80 | 0x1); + qemu_irq_lower(pc->scsi_reset); + } + if (val & SCSICSR_DMADIR) { + DPRINTF("SCSICSR DMAdir\n"); + } + if (val & SCSICSR_CPUDMA) { + DPRINTF("SCSICSR CPUDMA\n"); + /* qemu_irq_raise(s->scsi_dma); */ + pc->int_status |=3D 0x4000000; + } else { + /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ + pc->int_status &=3D ~(0x4000000); + /* qemu_irq_lower(s->scsi_dma); */ + } + if (val & SCSICSR_INTMASK) { + DPRINTF("SCSICSR INTMASK\n"); + /* + * int_mask &=3D ~0x1000; + * s->scsi_csr_1 |=3D val; + * s->scsi_csr_1 &=3D ~SCSICSR_INTMASK; + * if (s->scsi_queued) { + * s->scsi_queued =3D 0; + * next_irq(s, NEXT_SCSI_I, level); + * } + */ + } else { + /* int_mask |=3D 0x1000; */ + } + if (val & 0x80) { + /* int_mask |=3D 0x1000; */ + /* s->scsi_csr_1 |=3D 0x80; */ + } + DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); s->scsi_csr_1 =3D val; break; =20 case 1: + DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); s->scsi_csr_2 =3D val; break; =20 @@ -868,10 +851,12 @@ static uint64_t next_scsi_csr_read(void *opaque, hwad= dr addr, unsigned size) =20 switch (addr) { case 0: + DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); val =3D s->scsi_csr_1; break; =20 case 1: + DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); val =3D s->scsi_csr_2; break; =20 --=20 2.47.1