From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201711; cv=none; d=zohomail.com; s=zohoarc; b=hlufzujwLUFyGrDIOBKmzeRIXcAKN5Ho5Cj9i/QPq75Uor5nTR/cc0SWE42aYAhD044nv2twt7t1lgWRAUj0TbVBsDHuw0rBqX7mIXAlQuBwY16hQFko8Yr1sRfbAGKQqd7/2x3+b9YWNtDHTPY16FyHAuPItKede7qM97D6hyU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201711; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=F8RiAlCHl+1NqI9Hasi2td6dnDjrsz5BjuPhZ1v7pKk=; b=Q2QCT1jZAbNqF3nus1fgxG430XbXz51Nj24m6QDnum5ZHN99yizZGrTdhtaHHd4gtuHRInzf0KE8QnGef6UAjsHTYTwHWUFVEVFUzk+YPv6nFlm2siJ9k9+gMZ7PmoUyrr53/vkzDTYYHl32FAfzVmjIfeYVr3xPFNwGoGNb+00= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201711736531.0487931984854; Thu, 26 Dec 2024 00:28:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEG-0002MY-7P; Thu, 26 Dec 2024 03:28:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3mBNtZwgKCrUrpcVjoncbjjbgZ.XjhlZhp-YZqZgijibip.jmb@flex--wuhaotsh.bounces.google.com>) id 1tQjE6-0002Cr-Sl for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:16 -0500 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3mBNtZwgKCrUrpcVjoncbjjbgZ.XjhlZhp-YZqZgijibip.jmb@flex--wuhaotsh.bounces.google.com>) id 1tQjE1-000198-OX for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:11 -0500 Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-21640607349so108029535ad.0 for ; Thu, 26 Dec 2024 00:28:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201688; x=1735806488; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=F8RiAlCHl+1NqI9Hasi2td6dnDjrsz5BjuPhZ1v7pKk=; b=o9378D/BVgozfZrzdFyPXgt3/Oz7+mf7dMZnDBYuCd14AYOdfgGm9ejQ0If5cXxTfJ tCRpOc4sVQZBtaRfZN4MWU/XRWhhZ1HX3dDg3Tk062snOj6XQnTuHMiEdNsU+uevTLM6 JgneXshBAw6evM9i3IHEgaQtyKXPHVvZ4uXL3DK1Xlnr9Iw2vudEvnbzq/UmMUE5sz87 /ARUQf5Y3d2szsJ3tka9SxiOBXcVzDvXDOsw78LlgA/oVYNe2L54EpuHBJuUB8p1YT0z 2hRCawVc+ZuBw943gkb3XbO9AdDJA2UjX14b5t/yZbipvGvGKWNYyD/rYKm9QitsGKmS COTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201688; x=1735806488; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=F8RiAlCHl+1NqI9Hasi2td6dnDjrsz5BjuPhZ1v7pKk=; b=QjzZBUGwPsPSSdpvTbh8gvrvzYxU/I0hyNsoeYIaoGhI++vbJThV3syAGnjhKviMRQ 3bfah5hmVB6n7xgNeAfbtuxCFXeEMBuMDTwna8Vw5HIL4QaaDQutgzBTbCqtgdLLyq7a MlXAgckQeY8QPTxvC5mVL0bkdY1pgARydX5vgifAQ/yce5msfRcYMXxRcNEy949gS5BF Dzouad8OMWt+YUM0QH+j1IXsxyPWb1frnSzuDTziylUJ7spE5vAFJeMkIkbSwpStRAdu /7diY9hKeUtcl3qX1OyjNqBDy2wdrbdASnYk2TI85pgwkLJA8qbBt4zCq6TuOLfBv0cG 2cfA== X-Forwarded-Encrypted: i=1; AJvYcCUGi/RUkj5qP/F6OV4p5+j2StSZhLKzQN5dsrPlJCK1VHMY4+EQjDnbl4y10O/c+uLk5lFemxL8agZ3@nongnu.org X-Gm-Message-State: AOJu0Yw/AjuiinOk3NB98ZS1JzuWa2vTaLjtDxTOFMZPBB8HQWUOS2Qf iBA9WFWymEMFRcx/5Y5Y1ms0CrD2xbiuCq260oYLxB1qT3DFaJw1FjepwgLRGYR169xVI7kjAdU YlauRUxGKRw== X-Google-Smtp-Source: AGHT+IGvilV7ssgYxVWS/Fl41N4PsmieLAc5u0DLPylKWj4vV9D3USDscn7hRVB3zGkPXfESTVEhJ/F+/RSQ/A== X-Received: from pfbbr12.prod.google.com ([2002:a05:6a00:440c:b0:725:eb9c:47e4]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:1014:b0:1e3:e836:8aea with SMTP id adf61e73a8af0-1e5e046f453mr40786073637.14.1735201688208; Thu, 26 Dec 2024 00:28:08 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:44 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-2-wuhaotsh@google.com> Subject: [PATCH v2 01/17] docs/system/arm: Add Description for NPCM8XX SoC From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3mBNtZwgKCrUrpcVjoncbjjbgZ.XjhlZhp-YZqZgijibip.jmb@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201713600116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals. Signed-off-by: Hao Wu --- docs/system/arm/nuvoton.rst | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 05059378e5..0a1916fb99 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -1,12 +1,13 @@ Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta= -gbs-bmc``, ``quanta-gsj``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D =20 -The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are +The `Nuvoton iBMC`_ chips are a family of ARM-based SoCs that are designed to be used as Baseboard Management Controllers (BMCs) in various -servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an -assortment of peripherals targeted for either Enterprise or Data Center / -Hyperscale applications. The former is a superset of the latter, so NPCM75= 0 has -all the peripherals of NPCM730 and more. +servers. Currently there are two families: NPCM7XX series and +NPCM8XX series. NPCM7XX series feature one or two ARM Cortex-A9 CPU cores, +while NPCM8XX feature 4 ARM Cortex-A35 CPU cores. Both series contain a +different assortment of peripherals targeted for either Enterprise or Data +Center / Hyperscale applications. =20 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/ =20 @@ -27,6 +28,8 @@ There are also two more SoCs, NPCM710 and NPCM705, which = are single-core variants of NPCM750 and NPCM730, respectively. These are currently not supported by QEMU. =20 +The NPCM8xx SoC is the successor of the NPCM7xx SoC. + Supported devices ----------------- =20 @@ -62,6 +65,8 @@ Missing devices * System Wake-up Control (SWC) * Shared memory (SHM) * eSPI slave interface + * Block-tranfer interface (8XX only) + * Virtual UART (8XX only) =20 * Ethernet controller (GMAC) * USB device (USBD) @@ -76,6 +81,11 @@ Missing devices * Video capture * Encoding compression engine * Security features + * I3C buses (8XX only) + * Temperator sensor interface (8XX only) + * Virtual UART (8XX only) + * Flash monitor (8XX only) + * JTAG master (8XX only) =20 Boot options ------------ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201771; cv=none; d=zohomail.com; s=zohoarc; b=nY6EnkNtz0ddIS9blCBO/g4CIQjexiHmZPGHDGO/6yz/ugMAEGY5tS+vvkaJfU/QHTCegnDxTjfodDqySKAqkWYTB3lET9qOBUWq00FP6O5vN6ToSYNpQKvIzCMm5y2Dm+bh3/y1OGnPUjjtqIK0IoFxwHZeEIEwGw+vZs3OZzo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201771; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VGy+Nj9c83OW8O8chp58gNtXq2XnteX0cby7ElrxjQo=; b=KHH4CO9/9yRXzpAfr8T4upHVzMDclCfyPe3hGVbOg4Tq0Mc91kgJy0FQ+aRl2JXbXRJ/xEpgyGJPrL/LONbkJWDxyoMy23hfAQjPOUgn46bpVMjgtg+3exYS4EX8EtXbkR0KhBeOZ8m58TOAzDEWbrMgJugND2dJY0/l/6SOXsg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201771737229.90235599896653; Thu, 26 Dec 2024 00:29:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEK-0002ix-2V; Thu, 26 Dec 2024 03:28:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3mxNtZwgKCrgusfYmrqfemmejc.amkocks-bctcjlmlels.mpe@flex--wuhaotsh.bounces.google.com>) id 1tQjE8-0002Da-Jc for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:17 -0500 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3mxNtZwgKCrgusfYmrqfemmejc.amkocks-bctcjlmlels.mpe@flex--wuhaotsh.bounces.google.com>) id 1tQjE7-00019V-2i for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:16 -0500 Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-2ee5668e09bso7870089a91.3 for ; Thu, 26 Dec 2024 00:28:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201691; x=1735806491; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=VGy+Nj9c83OW8O8chp58gNtXq2XnteX0cby7ElrxjQo=; b=YsGwfEYGQI/ItVd3c/VVXJYqfQDEjZpaVSVtX2tgWDYBcYqieo6taqCRzJ2Jasj95t 8p7B1uTK6QUBVp2FjIB3CPI3BgEQBrSVtoPrsMTlwVxi4O9jQHM5Gd2jPuGALstzTzBq KM6kLWFYpyO3CiAPtcy0YwwuJdp2zaS2tZymsVvvATcCHj4maFX3fxR3WpqSDU1GxUJ3 PMYJetUuHb2NcOzrQUvO6nOSb614+LjIFDQ0mUKN3N1kBTjtY6H6RNLddtdanWR2IPEN r5idH+NTZeIFdb0vo2sAW/zRNwP+kx1i9fiKc7P4C0wOAYO8GAhZBc9hfl/0LpqYVJoH u8jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201691; x=1735806491; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VGy+Nj9c83OW8O8chp58gNtXq2XnteX0cby7ElrxjQo=; b=e5Gj6bZZR1NwG+a55ulGIoAQ0zjeeE4H3l2AnF0yA5GIkqUDfJVf9I0emz0Q1BFEGC 9iHRXnab/Yc9ASMBqhFFibCB2SvsyGhO5msa1aWSyRNLkLd5Zzb85YKn4sx0k+jsuU6R rH5j/hssJvO25dnJ82/ZVhvKFnfG4g3+A6QAdwupMuUfDUqncPnLUFisg3UbJU8yT2Ua FBjtvIG13KtnbSyaY8kqzUVJ74R++JrmEJY7qoxi2i7H6tcGw3dJAv/sba9r7TonWbo0 0ctB7SAZVT8bFlE/2G70V/26igsbstL/VMTTICM7P1QHcW4Js9IqZ5E+XorNr8m/Q64T 7gmg== X-Forwarded-Encrypted: i=1; AJvYcCXbD1WRpK9MTXOOinuUKcGsgCH6N+hqwCnj9xylJghQGoVr+AHcivHU7AR/s3TqSj5Ldqg+JdW3GHro@nongnu.org X-Gm-Message-State: AOJu0YxT/kx9V/AUaBKJti+Gl90RzZyFPsbUgG2lb98WpB34y7OyUueY AEFntIELDc7Dq4SYUgtY8W9SrOVoRna/yRBHupT2Haz3z2QHVTG/hZI9eNijMn9NJ0lIcU+/h/N GR3NaZu5V8A== X-Google-Smtp-Source: AGHT+IH0u3SEk4oFQ7ftwSoVSjUFRzp9bdsVlx0CgqOMIVEkmooDOUOSLyNvBr+QI7IZSpYeR+vec7IrCr3B1w== X-Received: from pjur6.prod.google.com ([2002:a17:90a:d406:b0:2ea:d2de:f7ca]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:fc48:b0:2ee:8e75:4aeb with SMTP id 98e67ed59e1d1-2f452e49238mr34728560a91.17.1735201691592; Thu, 26 Dec 2024 00:28:11 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:45 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-3-wuhaotsh@google.com> Subject: [PATCH v2 02/17] roms: Update vbootrom to 1287b6e From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::104a; envelope-from=3mxNtZwgKCrgusfYmrqfemmejc.amkocks-bctcjlmlels.mpe@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x104a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201773912116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one it supports loading the UBoot from the SPI device and not more. We updated the npcm7xx bootrom to be compiled from this version. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes roms/vbootrom | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/pc-bios/npcm7xx_bootrom.bin b/pc-bios/npcm7xx_bootrom.bin index 38f89d1b97b0c2e133af2a9fbed0521be132065b..903f126636f9ef5d1100c056656= ccfb2b32e5e10 100644 GIT binary patch delta 90 zcmZo*Yhc^(l+nU*!D9x6DNkDr=3D09a-2ztoGz`#|*F#jn7L;r()|Np;c0m>C1$z?$0 Ywog`Ma%Vh0Ig_b-VgU<}A_D>d06Rh+WdHyG delta 69 zcmZo*Yhc^(lu^NO!D9x2$xoRb7CdZGnE#ZCA@Cs+0|QqL!~CZV4E+!GPG)41X52Pe SmdTy*+~icIZXQJj1ONb5*AzJb diff --git a/roms/vbootrom b/roms/vbootrom index 0c37a43527..1287b6e42e 160000 --- a/roms/vbootrom +++ b/roms/vbootrom @@ -1 +1 @@ -Subproject commit 0c37a43527f0ee2b9584e7fb2fdc805e902635ac +Subproject commit 1287b6e42e839ba2ab0f06268c5b53ae60df3537 --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201759; cv=none; d=zohomail.com; s=zohoarc; b=WoeVVg3cC9SUjcuXzzcO3deCHmajMinTgHaWgqe+kjPqLYRMS1+EFiZS2KBIvY/jcjFPU6Nh/yrhAysmudjWlufFFAb6caeYcQmWrGfiYie4P/a312JWA2feMyQdHUK51gDFiQQCyy6iQMcbnNzpu1+onD4GnDHUQ4t6aQoVBBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201759; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xfNC9ogz1de0wuLdHYiHiqwKVT4pFZIRykyJquvWBMg=; b=ak2gW0OGBPoH1p+PP3tKdc2pfHo5ifk383SnyoZ1jzTk9LpvXNtVJEgzJPzYHlSTHdjp1bH3ohFCAv+R8Ocn+w0WaApc9zFcikMQJfPC61ttFNaJZbqUyG9c/NoYkteCH12wKy9VViSkvpiUajAwqBYpgaOtNpuy8UU0/6lsiHA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201759705963.1503557782373; Thu, 26 Dec 2024 00:29:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEN-0002zb-5u; Thu, 26 Dec 2024 03:28:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3nxNtZwgKCrwywjcqvujiqqing.eqosgow-fgxgnpqpipw.qti@flex--wuhaotsh.bounces.google.com>) id 1tQjEA-0002G1-Q9 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:21 -0500 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3nxNtZwgKCrwywjcqvujiqqing.eqosgow-fgxgnpqpipw.qti@flex--wuhaotsh.bounces.google.com>) id 1tQjE9-00019t-26 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:18 -0500 Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-21631cbf87dso68327815ad.3 for ; Thu, 26 Dec 2024 00:28:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201695; x=1735806495; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=xfNC9ogz1de0wuLdHYiHiqwKVT4pFZIRykyJquvWBMg=; b=Nzm5BA0nmIij/AJC5kQRZZw8fN3cXXmB/iKhKe3NKsWISux206DJnelpJeiMUelrfR Q01d86u66Ax9ubAy1hVCfGroSpNF2vjVFUpMmvWda8GvGWOkq53HJJo3xWF3A2kK7O36 2kD00TpO2JpGbMkta292rHgNgSGzNbNWJzCQczUudJ4IBtY8pNYSN9kpwBI6dUeQ2Zdd 6UAqE4GYBRdLkNB4/0eMj48sZmE/bkOPQvqllEsc9P6Gwmm7rBJlCD+mD7Z9jmdYJdP0 JIt02NYMado3ymUIOkEv6oHW8oZoRqHJBSswf666gERmylQrnMdm3mbVOXt7g1aOg+XN XTGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201695; x=1735806495; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xfNC9ogz1de0wuLdHYiHiqwKVT4pFZIRykyJquvWBMg=; b=s6Ngjwn8EAY253SKb2MLDoxK2BUh/+TCh/X44zJcztg0L/6wjlaUrTTXUVGb92BVXX v1a1753v+9/hqPebPcdX5UBwtrgyfghOdNODeaK96FI0GpyasiKp/S8Xmui09acC6FSH DjLgY9qbWJ2fE37P3VNDd7xR5eDj8Pc8gvRbl253W5HCkWKI8TgmiYlhm8U42m5MTmgU YZeCUGiq6R7EGNTyeV0b8tDv/A/D1o8nfsgRlHdXvrlVYSzAgJUjRNAQ+Kja5fNUQT/W WphuDN/ME0H2Fow4Req4Dg/jstEjjybuXRBKhEtraJwrWvj4zRC9/j+lFnxw5brW6hAD +PhQ== X-Forwarded-Encrypted: i=1; AJvYcCWbnjl0/al+fH8eIicUS+YBk3R3PyBjcJu8Glgr4wNeY+5fQUOmuQDfjNJxNhUtQTN388nKgBTdBwy6@nongnu.org X-Gm-Message-State: AOJu0YzYTyg6lUstUByogYEilu+ZhxSfz7ytHoNFp+mmbWd/jIEI0pGr 0vzjA5/5YuunPAH/3xXyh9XdPEYQ+pCX/s94mP+UMRrO1QUu6QxbydE04IwqgDekHnR4O8ktxOf kdTEKqG/lxQ== X-Google-Smtp-Source: AGHT+IESZ7Y3INb23OkoSCkS3wnytVIo9w3OKUtwFRMRVEfAsw9KRqLvBGSctyfhIY8VeVGgWdbKdy32aHz4dQ== X-Received: from pgpu12.prod.google.com ([2002:a65:40cc:0:b0:867:6a40:fe56]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:3181:b0:1e1:b062:f409 with SMTP id adf61e73a8af0-1e5e081db95mr33803839637.43.1735201695256; Thu, 26 Dec 2024 00:28:15 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:46 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-4-wuhaotsh@google.com> Subject: [PATCH v2 03/17] pc-bios: Add NPCM8XX vBootrom From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3nxNtZwgKCrwywjcqvujiqqing.eqosgow-fgxgnpqpipw.qti@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201761797116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The bootrom is a minimal bootrom used to load an NPCM8XX image. The source code is located in the same repo as the NPCM7XX one: github.com/google/vbootrom/tree/master/npcm8xx. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- MAINTAINERS | 1 + pc-bios/README | 8 ++++---- pc-bios/meson.build | 1 + pc-bios/npcm8xx_bootrom.bin | Bin 0 -> 608 bytes roms/Makefile | 6 ++++++ 5 files changed, 12 insertions(+), 4 deletions(-) create mode 100644 pc-bios/npcm8xx_bootrom.bin diff --git a/MAINTAINERS b/MAINTAINERS index 38a290e9c2..14bfadabbb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -872,6 +872,7 @@ F: include/hw/*/npcm* F: tests/qtest/npcm* F: tests/qtest/adm1266-test.c F: pc-bios/npcm7xx_bootrom.bin +F: pc-bios/npcm8xx_bootrom.bin F: roms/vbootrom F: docs/system/arm/nuvoton.rst F: tests/functional/test_arm_quanta_gsj.py diff --git a/pc-bios/README b/pc-bios/README index 7ffb2f43a4..700dcaab52 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -70,10 +70,10 @@ source code also contains code reused from other projects described here: https://github.com/riscv/opensbi/blob/master/ThirdPartyNotices.md. =20 -- npcm7xx_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for Nuvo= ton - NPCM7xx BMC devices. It currently implements the bare minimum to load, p= arse, - initialize and run boot images stored in SPI flash, but may grow more - features over time as needed. The source code is available at: +- npcm{7xx,8xx}_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for + Nuvoton NPCM7xx/8xx BMC devices. It currently implements the bare minimu= m to + load, parse, initialize and run boot images stored in SPI flash, but may= grow + more features over time as needed. The source code is available at: https://github.com/google/vbootrom =20 - hppa-firmware.img (32-bit) and hppa-firmware64.img (64-bit) are firmware diff --git a/pc-bios/meson.build b/pc-bios/meson.build index 4823dff189..d282c43658 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -80,6 +80,7 @@ blobs =3D [ 'opensbi-riscv32-generic-fw_dynamic.bin', 'opensbi-riscv64-generic-fw_dynamic.bin', 'npcm7xx_bootrom.bin', + 'npcm8xx_bootrom.bin', 'vof.bin', 'vof-nvram.bin', ] diff --git a/pc-bios/npcm8xx_bootrom.bin b/pc-bios/npcm8xx_bootrom.bin new file mode 100644 index 0000000000000000000000000000000000000000..6370d6475635c4d445d2b927311= edcd591949c82 GIT binary patch literal 608 zcmdUrKTE?<6vfX=3D0{*3B5ET?nwWA^;qEk()n=3DXb9-4dxoSBrz#p|QJQL~zokn{Eyc z?PBXUkU+aB?k?IbNQftG5ej|*FC2c{bKkr7zLy3jhNxj`gc_y5h&V=3DRu)PgZC)Y`f zTqA9Am28qLHlr*^&hT#;re-)dpxT0U42|O+cWOcx=3DB;{6xXH04vx?cjm z+%U{oFx!aPpV3>ZKz0i$XA-yq{f}x4;|pbw;l#@9zGd|z-rs*H@V-o%PEV)D-)8n2%DyH5@w_^Y8 LH5R3RMV#gjxYTW} literal 0 HcmV?d00001 diff --git a/roms/Makefile b/roms/Makefile index 31e4b97c98..beff58d9d5 100644 --- a/roms/Makefile +++ b/roms/Makefile @@ -34,6 +34,7 @@ find-cross-gcc =3D $(firstword $(wildcard $(patsubst %ld,= %gcc,$(call find-cross-ld # finally strip off path + toolname so we get the prefix find-cross-prefix =3D $(subst gcc,,$(notdir $(call find-cross-gcc,$(1)))) =20 +aarch64_cross_prefix :=3D $(call find-cross-prefix,aarch64) arm_cross_prefix :=3D $(call find-cross-prefix,arm) powerpc64_cross_prefix :=3D $(call find-cross-prefix,powerpc64) powerpc_cross_prefix :=3D $(call find-cross-prefix,powerpc) @@ -66,6 +67,7 @@ default help: @echo " u-boot.e500 -- update u-boot.e500" @echo " u-boot.sam460 -- update u-boot.sam460" @echo " npcm7xx_bootrom -- update vbootrom for npcm7xx" + @echo " npcm8xx_bootrom -- update vbootrom for npcm8xx" @echo " efi -- update UEFI (edk2) platform firmware" @echo " opensbi32-generic -- update OpenSBI for 32-bit generic machine" @echo " opensbi64-generic -- update OpenSBI for 64-bit generic machine" @@ -194,6 +196,10 @@ npcm7xx_bootrom: $(MAKE) -C vbootrom CROSS_COMPILE=3D$(arm_cross_prefix) cp vbootrom/npcm7xx_bootrom.bin ../pc-bios/npcm7xx_bootrom.bin =20 +npcm8xx_bootrom: + $(MAKE) -C vbootrom CROSS_COMPILE=3D$(aarch64_cross_prefix) + cp vbootrom/npcm8xx_bootrom.bin ../pc-bios/npcm8xx_bootrom.bin + hppa-firmware: $(MAKE) -C seabios-hppa parisc cp seabios-hppa/out/hppa-firmware.img ../pc-bios/ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201716; cv=none; d=zohomail.com; s=zohoarc; b=SJ1P8F2qfWVbnuev79KSe/u8DqTG5WbBAUltV+KjoMdX6XIogS0A1LDwCgYI+jSotHfTGBnmyHajakovAVJAmkAvfPGpB+LBOkS+fMBygzBA1FxbIdlp8PSG+bKa+I/NBW+LHZF+wtcqNJF0yWa6ELEIxyk/0WYuMkrgVc+swIA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201716; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mII2KQCbUJ3mJ7sYUww2aSfqMfq2RPMoT2IXlGafl+I=; b=Z+9HIHfViNLOU5l35HhbnjCcFVP0sy36gpSoEKjIwxVRm1p56KEv+9QTfHOsd0GCGColz/4hZrjwIBJsJUlLuJ4nSjaGc5ACG93RhiVsrgZSCB3WYTx/b5vder0VW9+hi7gml7zBZual3d2PUgQ0fYALbqZwXaN8yXJ+oTh1smY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173520171690460.37867970695561; Thu, 26 Dec 2024 00:28:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEJ-0002fB-Do; Thu, 26 Dec 2024 03:28:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3oxNtZwgKCsA20nguzynmuumrk.iuswks0-jk1krtutmt0.uxm@flex--wuhaotsh.bounces.google.com>) id 1tQjEF-0002NL-SX for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:24 -0500 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3oxNtZwgKCsA20nguzynmuumrk.iuswks0-jk1krtutmt0.uxm@flex--wuhaotsh.bounces.google.com>) id 1tQjEE-0001Ag-7v for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:23 -0500 Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-216266cc0acso73577895ad.0 for ; Thu, 26 Dec 2024 00:28:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201699; x=1735806499; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=mII2KQCbUJ3mJ7sYUww2aSfqMfq2RPMoT2IXlGafl+I=; b=xQH6QarFSBNHiXUh4qAmxdclYz2zPPNPsg2Im3Y+fEu/6AvsD1IaImRaf4m7I7klLd MltNyzQ2Zfdz8nwc7GvY/iKkTtCvzHOOUO8Dx7nIJ6YvSNV4d3VBUf956dx1u4ZaPB+j k4dh9Q44GhIiNMTQ+ZewzYe1VQl9t7SDnuf/loZ5ZQ0o2/iIVVu1ke5GAYACXoP/bTxS IUlNzx9OGQEu1gUZ7k4dhWxq3U8hP/q+Y7UIuCFV3ZDFV1b2ZwOYxno+V4J0qAFtWflA sf1wI88LECGVJ/osEOL69pPOoHd7arCNabBwiyfkSrTWE48+SRKKFT8DOluhRifc4Ybm vHGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201699; x=1735806499; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=mII2KQCbUJ3mJ7sYUww2aSfqMfq2RPMoT2IXlGafl+I=; b=BguAK/ztlkivlLaj/Pga5fqliMAAx2QOw6okraE5Vs1TA4Bb8OCX0OAbV0jR0Sv4WI 8nDu+26DXM9irShbNXuBkWsa9Ocjbj8M+HSDxiWRXfra1fGffTIQlr50yh2WBsr34EhZ gS2svWGrkyMEI5m9Hy0z3axYSD92NybyIxKWfeTSouGtVGtb5PU1jUEJvBouHeBiC6CM Mal41iCYltvKg+Ycy35nGgC1uPjHOYnsjqCLip75zwhg1dhMbI4kXztjZDDRJQprGqTC UKOkCX3+0AnZsNFUc7bFcURq+4cmiTTgXE0nQIZxuo79X4OS/aesUsN/EMhs4pkgYR8z n9YQ== X-Forwarded-Encrypted: i=1; AJvYcCXQtjTOeid9/kUwwMWcI4nGjtXBci235+7C+bOuiZOmkmN+ttIL8ywKSxrrhkaHtdspyFkViPrYA3sS@nongnu.org X-Gm-Message-State: AOJu0YyzIetJ4ot6VEeM5Lkbvekwy5xvP8mVbloGaOhU6stklR0jZIV6 R5vlm6rbfM114fIuSJ6KzwzB5v436KoW1CzsHFu7yhyHKpQtfliLrht2QcUBJ12+t0OhkPasIoa Jb5WF7bAnaQ== X-Google-Smtp-Source: AGHT+IEOIlKRo0CPIfiRBIASsAj56U8UmGz4URC97JgwDIpObHPRh4rd435D7IRcnRBSXpSycokJmHIbIoViKQ== X-Received: from pgot8.prod.google.com ([2002:a63:b248:0:b0:7fd:56a7:26a8]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:1593:b0:1e1:ffec:b1a9 with SMTP id adf61e73a8af0-1e5c6ec6f11mr40177658637.3.1735201699024; Thu, 26 Dec 2024 00:28:19 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:47 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-5-wuhaotsh@google.com> Subject: [PATCH v2 04/17] hw/ssi: Make flash size a property in NPCM7XX FIU From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3oxNtZwgKCsA20nguzynmuumrk.iuswks0-jk1krtutmt0.uxm@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201717614116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This allows different FIUs to have different flash sizes, useful in NPCM8XX which has multiple different sized FIU modules. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/arm/npcm7xx.c | 6 ++++++ hw/ssi/npcm7xx_fiu.c | 11 +++++++---- include/hw/ssi/npcm7xx_fiu.h | 1 + 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 386b2c35e9..2d6e08b72b 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -292,17 +292,21 @@ static const struct { hwaddr regs_addr; int cs_count; const hwaddr *flash_addr; + size_t flash_size; } npcm7xx_fiu[] =3D { { .name =3D "fiu0", .regs_addr =3D 0xfb000000, .cs_count =3D ARRAY_SIZE(npcm7xx_fiu0_flash_addr), .flash_addr =3D npcm7xx_fiu0_flash_addr, + .flash_size =3D 128 * MiB, + }, { .name =3D "fiu3", .regs_addr =3D 0xc0000000, .cs_count =3D ARRAY_SIZE(npcm7xx_fiu3_flash_addr), .flash_addr =3D npcm7xx_fiu3_flash_addr, + .flash_size =3D 128 * MiB, }, }; =20 @@ -735,6 +739,8 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) =20 object_property_set_int(OBJECT(sbd), "cs-count", npcm7xx_fiu[i].cs_count, &error_abort); + object_property_set_int(OBJECT(sbd), "flash-size", + npcm7xx_fiu[i].flash_size, &error_abort); sysbus_realize(sbd, &error_abort); =20 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr); diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 21fc489038..ccdce67fa9 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -28,9 +28,6 @@ =20 #include "trace.h" =20 -/* Up to 128 MiB of flash may be accessed directly as memory. */ -#define NPCM7XX_FIU_FLASH_WINDOW_SIZE (128 * MiB) - /* Each module has 4 KiB of register space. Only a fraction of it is used.= */ #define NPCM7XX_FIU_CTRL_REGS_SIZE (4 * KiB) =20 @@ -507,6 +504,11 @@ static void npcm7xx_fiu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + if (s->flash_size =3D=3D 0) { + error_setg(errp, "%s: flash size must be set", dev->canonical_path= ); + return; + } + s->spi =3D ssi_create_bus(dev, "spi"); s->cs_lines =3D g_new0(qemu_irq, s->cs_count); qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", s->cs_count); @@ -525,7 +527,7 @@ static void npcm7xx_fiu_realize(DeviceState *dev, Error= **errp) flash->fiu =3D s; memory_region_init_io(&flash->direct_access, OBJECT(s), &npcm7xx_fiu_flash_ops, &s->flash[i], "flash= ", - NPCM7XX_FIU_FLASH_WINDOW_SIZE); + s->flash_size); sysbus_init_mmio(sbd, &flash->direct_access); } } @@ -543,6 +545,7 @@ static const VMStateDescription vmstate_npcm7xx_fiu =3D= { =20 static const Property npcm7xx_fiu_properties[] =3D { DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0), + DEFINE_PROP_SIZE("flash-size", NPCM7xxFIUState, flash_size, 0), }; =20 static void npcm7xx_fiu_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/ssi/npcm7xx_fiu.h b/include/hw/ssi/npcm7xx_fiu.h index a3a1704289..1785ea16f4 100644 --- a/include/hw/ssi/npcm7xx_fiu.h +++ b/include/hw/ssi/npcm7xx_fiu.h @@ -60,6 +60,7 @@ struct NPCM7xxFIUState { int32_t cs_count; int32_t active_cs; qemu_irq *cs_lines; + size_t flash_size; NPCM7xxFIUFlash *flash; =20 SSIBus *spi; --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201738; cv=none; d=zohomail.com; s=zohoarc; b=HLhpcqxBWATB9YOIzCt0t1fatZrcwxk8BDdqQmqxUmxuIMv3Q4QC+JRk2liWsFcmin+nrjo4eKwxdSBYCOtBtKghycKCPIoIuf86e8pkdW2vRdNRKZNWvCXlAVjTQxXMLlTc3jX9pVt1pP7f7RlEEoXkXAcRAmt6duMhuWeWfOM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201738; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=G3x5K8zsn6Y1xJmAh6tP7pJX4NJthEKLJvAizkBq/wM=; b=KsIIDcvOApXn8HuRNBtXeOGOvEqhuYcxAsTQcSuOqSxRDC7T2O0sgnf3XXhWQV5ENaJNMMf2gjzsqTMSktjUPd9afb63Bbqqh/i9VR2xIqvjG9NX5OVUJNdcfHVpgtjjemrPFEHYWfYOmsYjYGL6N6iz6yUA/hPgAp+Qby1AOaM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201738085225.51125844515718; Thu, 26 Dec 2024 00:28:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEQ-0003Iu-Rv; Thu, 26 Dec 2024 03:28:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3phNtZwgKCsM53qjx21qpxxpun.lxvznv3-mn4nuwxwpw3.x0p@flex--wuhaotsh.bounces.google.com>) id 1tQjEI-0002ZL-AL for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:26 -0500 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3phNtZwgKCsM53qjx21qpxxpun.lxvznv3-mn4nuwxwpw3.x0p@flex--wuhaotsh.bounces.google.com>) id 1tQjEG-0001B6-JY for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:26 -0500 Received: by mail-pj1-x1049.google.com with SMTP id 98e67ed59e1d1-2ef9dbeb848so7532160a91.0 for ; Thu, 26 Dec 2024 00:28:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201702; x=1735806502; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=G3x5K8zsn6Y1xJmAh6tP7pJX4NJthEKLJvAizkBq/wM=; b=BAo05Mwn/r1IA06Sutbozd5XYFbdx9ePDRqNZBtcSyBn+EXn4uTybuOrtMIK/FtG8x GTNjGA/otX6/Kx4sIZCXpCzBytRWq1s1rSvxro8vatEShSdXdoJ2l84+Ae18T9T14WLX ixRzhAkDG3OyBRcRRJD7GYwcO6H6mIg5xpJ8g1csz+JPRSvwbUiAYBVFa30emf2zKbRW T5xM5lawzaUGXWrhGkYdcF2SssRJUog0EikoxlwP6vErKoP/HCtm6HUmUp9BuPfntQ1I xMeIvF1eqB3062Ma9DWEXR5YYlyVe3N9A69osHAReCEnJur8+ipH3I0GwSxVVLbLoguP T+kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201702; x=1735806502; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=G3x5K8zsn6Y1xJmAh6tP7pJX4NJthEKLJvAizkBq/wM=; b=kh1BiQXwNqvqGaH4AJgbeAL5nTxvTVsond0zjF7HHglpXqKZB6zwfh6AOLLeqG0FKe yDi89lJZxuwN2cmtDc21NVW99yYS2UTTBDQxAFZv0G0KM05UIlLQMtH6YzB1oVHxrQ1E wb9xRRbyRv5rwv66CHuYrplvD/7pme4+/pYN/2tgx6DTtniEJBsrxyXqdTgbFdDrcJcu +m7LvE73LIr9u+e/GWIYqepKi195/l3YSM7QMk0ezLb2JO57YBUgObIPf8xpAVzqQ7ML xVoO5QK5ATJsN82sU4JSnyDy6oBKR8B2NzdAS/yLTcQPnB1f4jj142M0f6m4pQhNaYHo aUvA== X-Forwarded-Encrypted: i=1; AJvYcCUo9hE6y/wku+yXHnwdbcuUdyKrWiUihVBRCbPF10AdQqSaqMHeHGSL3oMJH6NFHMJ3G+s5dNX6DPjv@nongnu.org X-Gm-Message-State: AOJu0Yw0q7wi+W7J+Rq9LNRP5U8UE1d+GvhNaWUp1MbQWmG2ornDQKqR 33pGu6TQIQS69AuIl9zBi+pl6aTbPuOu6j9JjS1u3Nobvr9koTJPCFhXVfqeqHdD/NlmbTWzxPJ Xz4nQy0JuRg== X-Google-Smtp-Source: AGHT+IG7TfB6tSfev6mdz7Q67N5mGJW1qVoURWTXruqmwpZS15lfsbJW6gLiVDr/pWyifXWY+KOgZpOIKwgphw== X-Received: from pgew11.prod.google.com ([2002:a63:af0b:0:b0:7fe:ffc8:1ac6]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:841d:b0:1e1:b19a:fb58 with SMTP id adf61e73a8af0-1e5e0480dc7mr38846937637.13.1735201702497; Thu, 26 Dec 2024 00:28:22 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:48 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-6-wuhaotsh@google.com> Subject: [PATCH v2 05/17] hw/misc: Rename npcm7xx_gcr to npcm_gcr From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=3phNtZwgKCsM53qjx21qpxxpun.lxvznv3-mn4nuwxwpw3.x0p@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201739675116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module needs to fit both. This commit changes the name of the GCR module. Future commits will add the support for NPCM8XX GCRs. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/meson.build | 2 +- hw/misc/{npcm7xx_gcr.c =3D> npcm_gcr.c} | 2 +- include/hw/arm/npcm7xx.h | 2 +- include/hw/misc/{npcm7xx_gcr.h =3D> npcm_gcr.h} | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) rename hw/misc/{npcm7xx_gcr.c =3D> npcm_gcr.c} (99%) rename include/hw/misc/{npcm7xx_gcr.h =3D> npcm_gcr.h} (96%) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index d02d96e403..9bab048849 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -68,7 +68,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( )) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm7xx_clk.c', - 'npcm7xx_gcr.c', + 'npcm_gcr.c', 'npcm7xx_mft.c', 'npcm7xx_pwm.c', 'npcm7xx_rng.c', diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm_gcr.c similarity index 99% rename from hw/misc/npcm7xx_gcr.c rename to hw/misc/npcm_gcr.c index 07464a4dc9..826fd41123 100644 --- a/hw/misc/npcm7xx_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -16,7 +16,7 @@ =20 #include "qemu/osdep.h" =20 -#include "hw/misc/npcm7xx_gcr.h" +#include "hw/misc/npcm_gcr.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qapi/error.h" diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 4e0d210188..510170471e 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -24,7 +24,7 @@ #include "hw/i2c/npcm7xx_smbus.h" #include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" -#include "hw/misc/npcm7xx_gcr.h" +#include "hw/misc/npcm_gcr.h" #include "hw/misc/npcm7xx_mft.h" #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm_gcr.h similarity index 96% rename from include/hw/misc/npcm7xx_gcr.h rename to include/hw/misc/npcm_gcr.h index c0bbdda77e..9b4998950c 100644 --- a/include/hw/misc/npcm7xx_gcr.h +++ b/include/hw/misc/npcm_gcr.h @@ -13,8 +13,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. */ -#ifndef NPCM7XX_GCR_H -#define NPCM7XX_GCR_H +#ifndef NPCM_GCR_H +#define NPCM_GCR_H =20 #include "exec/memory.h" #include "hw/sysbus.h" @@ -70,4 +70,4 @@ struct NPCM7xxGCRState { #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR) =20 -#endif /* NPCM7XX_GCR_H */ +#endif /* NPCM_GCR_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201742; cv=none; d=zohomail.com; s=zohoarc; b=Q3HV/UexTrqYiKxqjE0jP7XoivfJpMh0mZKn4h/Iw1OWVwy11vPFcMKow+0Az+Cq7zfInJFG0Yy4QzMAoqvXrbd++c/DU0lUZdoP5P+Mm+NpUm/bUWedFwHeAK2M5HcpXt92raoWA4DAwVRNzE/66Mn4IWKFnM6m23X+EjxviOM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201742; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PGiRo5raG/ykEW6v5ck/8cMpgDmuEWhEdPQmIu7j9JY=; b=LBbZ6ybfmDuH6DDzHtQNmFctAtszaYdi3f5RCGO9ZNlloOdd3yaxLAekO16LAWYRpYxSJaZWPHoeyhtQH5CSeDlb8NhW2nJn0sY1bv2xp46UBF7yt1Fn6Obkm3oahB9CU+H7BXjHqp3oE3Bda6hL3vKGvTvNhNoSLQbgK5S8xEE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201742348160.12936687481806; Thu, 26 Dec 2024 00:29:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjET-0003gW-4y; Thu, 26 Dec 2024 03:28:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3qhNtZwgKCsc97un165ut11tyr.p1z3rz7-qr8ry010t07.14t@flex--wuhaotsh.bounces.google.com>) id 1tQjEM-0002yj-HY for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:30 -0500 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3qhNtZwgKCsc97un165ut11tyr.p1z3rz7-qr8ry010t07.14t@flex--wuhaotsh.bounces.google.com>) id 1tQjEK-0001Bj-C4 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:30 -0500 Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-2162f80040aso71073365ad.1 for ; Thu, 26 Dec 2024 00:28:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201706; x=1735806506; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=PGiRo5raG/ykEW6v5ck/8cMpgDmuEWhEdPQmIu7j9JY=; b=OVXpIMIeOqXOzmi/hSYVPz+Irf9Ap+Kh8z4qRzFoOM99gpt2jdghqxxL+EAIegy6RJ ew4pmq9rElPn8IDCzAv7j1opZ6K822KXeM+8th4meRjMpSV82WivQAQptB5PRO2Oyctj sFfD+jA4Bn+7KO/YEzVqT36eBUhrHHycdHk0Nno2nuVxcw8r/PRhMy/fi6cK8tlizcL0 JORouqDiDFpz+IBoYvZgszFHLza1rGJ56CZjbQFHggNzud60FKqwojYiMPLjrVf2durv 0LzmP08JD0Gxw0LbkJ3AYYKYGVbyDat21Gd9OihHgVXxyOXRf/Uv21C//G+R2kzFEdMF Xoeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201706; x=1735806506; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=PGiRo5raG/ykEW6v5ck/8cMpgDmuEWhEdPQmIu7j9JY=; b=ZQ5kccVNG4F0ff72L/ru3vB5Wz4a3xQBFyx9VmIfED2mHS+YumqbeNYas3ZaH+s6x5 9zmJt4YLhIOzRlSQ7vjCkOiwFqcj5vvJG3P2AaB9nqPRh6U8/cB3jyZYaRckq/IIL9IJ fi1i6yvpPpQARS1NqlIKDYSYrk6AIzYS0g7O69Fdg3XFC3RS9d451VrS6Hdy7VdqBWyn ozX7aNwaUvTWV7UCC8p2B/qcmOUVqJ+Aoy6KWWSlRjaiC4n6mWOW+w+lh7nfFNYhOcLo X3vSSZLXzhBivrAX9b5VOIBDXuRtFc1OvG0SXQTjEgOXwdQPTasSwtZuhL8NRL6ZWQzR xK9Q== X-Forwarded-Encrypted: i=1; AJvYcCXVmDSZV4FKfQO+gFs29VJj2f+RuyedVi67iDtn8aUjhAQF2cZDm05+tvgVCV4zQbtpyc9ISPgvfwC7@nongnu.org X-Gm-Message-State: AOJu0YzbwdznNyOvW+v7C0zHAWsMRntLX7cBIW0WPdQKXuC6A51Kaol+ 6cE9+8LSXiwPb/zFj6eneNtDEKmx/SmFbdBs6mI2dZEv+8BRT+IaOfcxwaktJcX0MDSNt4uzor9 jw12ccnllFg== X-Google-Smtp-Source: AGHT+IEmj3GPmQBTzL/iAxTCDy+YAB2U4bP/K4mR8jNmq535VhXUn84BMZN1mfoBkP3QXOS7pGw80SJlDUIuZA== X-Received: from plbkw6.prod.google.com ([2002:a17:902:f906:b0:216:2d2a:d873]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:244b:b0:216:34e5:6e49 with SMTP id d9443c01a7336-219e70dd211mr298005215ad.57.1735201706216; Thu, 26 Dec 2024 00:28:26 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:49 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-7-wuhaotsh@google.com> Subject: [PATCH v2 06/17] hw/misc: Move NPCM7XX GCR to NPCM GCR From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3qhNtZwgKCsc97un165ut11tyr.p1z3rz7-qr8ry010t07.14t@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201743858116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A lot of NPCM7XX and NPCM8XX GCR modules share the same code, this commit moves the NPCM7XX GCR to NPCM GCR for these properties. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm_gcr.c | 92 +++++++++++++++++++++----------------- hw/misc/trace-events | 6 +-- include/hw/arm/npcm7xx.h | 2 +- include/hw/misc/npcm_gcr.h | 7 +-- 4 files changed, 59 insertions(+), 48 deletions(-) diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index 826fd41123..0959f2e5c4 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -84,10 +84,10 @@ static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_= REGS] =3D { [NPCM7XX_GCR_USB2PHYCTL] =3D 0x034730e4, }; =20 -static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned siz= e) +static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); - NPCM7xxGCRState *s =3D opaque; + NPCMGCRState *s =3D opaque; =20 if (reg >=3D NPCM7XX_GCR_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -96,19 +96,19 @@ static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr o= ffset, unsigned size) return 0; } =20 - trace_npcm7xx_gcr_read(offset, s->regs[reg]); + trace_npcm_gcr_read(offset, s->regs[reg]); =20 return s->regs[reg]; } =20 -static void npcm7xx_gcr_write(void *opaque, hwaddr offset, +static void npcm_gcr_write(void *opaque, hwaddr offset, uint64_t v, unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); - NPCM7xxGCRState *s =3D opaque; + NPCMGCRState *s =3D opaque; uint32_t value =3D v; =20 - trace_npcm7xx_gcr_write(offset, value); + trace_npcm_gcr_write(offset, value); =20 if (reg >=3D NPCM7XX_GCR_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -142,9 +142,9 @@ static void npcm7xx_gcr_write(void *opaque, hwaddr offs= et, s->regs[reg] =3D value; } =20 -static const struct MemoryRegionOps npcm7xx_gcr_ops =3D { - .read =3D npcm7xx_gcr_read, - .write =3D npcm7xx_gcr_write, +static const struct MemoryRegionOps npcm_gcr_ops =3D { + .read =3D npcm_gcr_read, + .write =3D npcm_gcr_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, @@ -155,7 +155,7 @@ static const struct MemoryRegionOps npcm7xx_gcr_ops =3D= { =20 static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type) { - NPCM7xxGCRState *s =3D NPCM7XX_GCR(obj); + NPCMGCRState *s =3D NPCM_GCR(obj); =20 QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values)); =20 @@ -165,10 +165,10 @@ static void npcm7xx_gcr_enter_reset(Object *obj, Rese= tType type) s->regs[NPCM7XX_GCR_INTCR3] =3D s->reset_intcr3; } =20 -static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp) +static void npcm_gcr_realize(DeviceState *dev, Error **errp) { ERRP_GUARD(); - NPCM7xxGCRState *s =3D NPCM7XX_GCR(dev); + NPCMGCRState *s =3D NPCM_GCR(dev); uint64_t dram_size; Object *obj; =20 @@ -210,55 +210,65 @@ static void npcm7xx_gcr_realize(DeviceState *dev, Err= or **errp) s->reset_intcr3 |=3D ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8; } =20 -static void npcm7xx_gcr_init(Object *obj) +static void npcm_gcr_init(Object *obj) { - NPCM7xxGCRState *s =3D NPCM7XX_GCR(obj); + NPCMGCRState *s =3D NPCM_GCR(obj); =20 - memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s, - TYPE_NPCM7XX_GCR, 4 * KiB); + memory_region_init_io(&s->iomem, obj, &npcm_gcr_ops, s, + TYPE_NPCM_GCR, 4 * KiB); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } =20 -static const VMStateDescription vmstate_npcm7xx_gcr =3D { - .name =3D "npcm7xx-gcr", - .version_id =3D 0, - .minimum_version_id =3D 0, +static const VMStateDescription vmstate_npcm_gcr =3D { + .name =3D "npcm-gcr", + .version_id =3D 1, + .minimum_version_id =3D 1, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, NPCM7xxGCRState, NPCM7XX_GCR_NR_REGS), + VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM7XX_GCR_NR_REGS), VMSTATE_END_OF_LIST(), }, }; =20 -static const Property npcm7xx_gcr_properties[] =3D { - DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0), - DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0), +static const Property npcm_gcr_properties[] =3D { + DEFINE_PROP_UINT32("disabled-modules", NPCMGCRState, reset_mdlr, 0), + DEFINE_PROP_UINT32("power-on-straps", NPCMGCRState, reset_pwron, 0), }; =20 -static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data) +static void npcm_gcr_class_init(ObjectClass *klass, void *data) { - ResettableClass *rc =3D RESETTABLE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS); + dc->realize =3D npcm_gcr_realize; + dc->vmsd =3D &vmstate_npcm_gcr; + + device_class_set_props(dc, npcm_gcr_properties); +} + +static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 + QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END !=3D NPCM7XX_GCR_NR_REGS); dc->desc =3D "NPCM7xx System Global Control Registers"; - dc->realize =3D npcm7xx_gcr_realize; - dc->vmsd =3D &vmstate_npcm7xx_gcr; rc->phases.enter =3D npcm7xx_gcr_enter_reset; =20 - device_class_set_props(dc, npcm7xx_gcr_properties); } =20 -static const TypeInfo npcm7xx_gcr_info =3D { - .name =3D TYPE_NPCM7XX_GCR, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(NPCM7xxGCRState), - .instance_init =3D npcm7xx_gcr_init, - .class_init =3D npcm7xx_gcr_class_init, +static const TypeInfo npcm_gcr_info[] =3D { + { + .name =3D TYPE_NPCM_GCR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCMGCRState), + .instance_init =3D npcm_gcr_init, + .class_init =3D npcm_gcr_class_init, + .abstract =3D true, + }, + { + .name =3D TYPE_NPCM7XX_GCR, + .parent =3D TYPE_NPCM_GCR, + .class_init =3D npcm7xx_gcr_class_init, + }, }; - -static void npcm7xx_gcr_register_type(void) -{ - type_register_static(&npcm7xx_gcr_info); -} -type_init(npcm7xx_gcr_register_type); +DEFINE_TYPES(npcm_gcr_info) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b9fbcb0924..f2d498e862 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -134,9 +134,9 @@ mos6522_read(uint64_t addr, const char *name, unsigned = val) "reg=3D0x%"PRIx64 " [% npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 =20 -# npcm7xx_gcr.c -npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 -npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 +# npcm_gcr.c +npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx32 +npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx32 =20 # npcm7xx_mft.c npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: o= ffset: 0x%04" PRIx64 " value: 0x%04" PRIx16 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 510170471e..2e708471ec 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -89,7 +89,7 @@ struct NPCM7xxState { MemoryRegion ram3; MemoryRegion *dram; =20 - NPCM7xxGCRState gcr; + NPCMGCRState gcr; NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; NPCM7xxADCState adc; diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h index 9b4998950c..6d3d00d260 100644 --- a/include/hw/misc/npcm_gcr.h +++ b/include/hw/misc/npcm_gcr.h @@ -55,7 +55,7 @@ */ #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) =20 -struct NPCM7xxGCRState { +typedef struct NPCMGCRState { SysBusDevice parent; =20 MemoryRegion iomem; @@ -65,9 +65,10 @@ struct NPCM7xxGCRState { uint32_t reset_pwron; uint32_t reset_mdlr; uint32_t reset_intcr3; -}; +} NPCMGCRState; =20 +#define TYPE_NPCM_GCR "npcm-gcr" #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" -OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR) +OBJECT_DECLARE_SIMPLE_TYPE(NPCMGCRState, NPCM_GCR) =20 #endif /* NPCM_GCR_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201749; cv=none; d=zohomail.com; s=zohoarc; b=K/p/GU4lx5Kw8jXdO4WoLv0YhPY6jJ4HS0/mtGej88VIF+P+4x4fOdfiX6o5DgRt49bM0yxDnCbrqkjgD4RFXOXNhYM3cKYEuAzhTPQalOAFCk1SaJ1yIPVyx14RJdIqCeuEQ10ZJ8ia59XYNeosqgbiU50O2Qg2Z8xDzJoR8A8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201749; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=e0yjpIGSDYAwA98JtHidNici6pMLPUvDd00lZuWT+Lw=; b=I3OMJintD/NttznqKnOrr4/YVSfLVKD2gmwkNcInULz58rFlMLLY8IunLCmsHJKieA3jPKbaFKvmA5z7FJhJKe6tQLTgcI81ZprR8blgBw8m0OvAl1FG2+WJyb9rKuksy0zb6WSVA1QAFBzD9D0+QG4QyU4A76pL0nli2GizjxA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201749797824.0782433317634; Thu, 26 Dec 2024 00:29:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjET-0003gJ-4j; Thu, 26 Dec 2024 03:28:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3rRNtZwgKCsoCAxq498xw44w1u.s426u2A-tuBu1343w3A.47w@flex--wuhaotsh.bounces.google.com>) id 1tQjEP-0003Hj-Jr for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:34 -0500 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3rRNtZwgKCsoCAxq498xw44w1u.s426u2A-tuBu1343w3A.47w@flex--wuhaotsh.bounces.google.com>) id 1tQjEN-0001CI-9F for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:33 -0500 Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-2162259a5dcso136124935ad.3 for ; Thu, 26 Dec 2024 00:28:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201710; x=1735806510; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=e0yjpIGSDYAwA98JtHidNici6pMLPUvDd00lZuWT+Lw=; b=LRMDcOEforP0d6eRO0/lZ6oAKw7Wz1jOwUKnVOAlh6uNABZcgxmUSRBfMgxot/hd59 laa0YVRLRGRTH+4DH/jaSPqJfX7Ofo7FNs4o7x8+bvmfTS8H7JlivXrgysVwc+q4LIPE 4OA+AAFop1YNsja9TWkgqPBtHGX/nzBZ1dl/J84LbwjHrU/LjWbWCZHTgopkQ27AN8RG Ofe8e0VNplN5z4y9OJOIChGd9LqIlwF+BP0QU2PTmQtAey+mM4eTJXGeRFS77Xy2jwtr LtAXVlP9/pR0HiRsTsu8MVI6Atml8B0cpivPE1kxUB1mzj5ocILzOaLfAyiXev+g5AZt djkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201710; x=1735806510; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=e0yjpIGSDYAwA98JtHidNici6pMLPUvDd00lZuWT+Lw=; b=Nfmt2Vt2g7TuAeOfQHTpIpky8oCYfdP0b8yWQ/By8G11lKr/yugevh+ognk2gns+N2 c7eptA96mpLrjHn0i1lt4CvoAZl5UOU/smo1wwbGKp3sELD7GfRF+YxqQNl5skzpAwkS KDfAb5GYY10IzoM6tpCmM5jfHRSGXLuJ+vlj8FG8MOR37VWSEGeWXYmuf9i+Bcm3Ho6l z8uIJgPTeYOp2rp7R0P/UArb9z0zKII2m0cdHX6KRMaYsGqgqjHeYFtypE7h01Z7G2BH xkrtw6XJNfK59k29dsskiwmovc2MWabfC+Eqr6trmrTrPhyFWa/gUsDMuzQjv4vO6AG1 tH8Q== X-Forwarded-Encrypted: i=1; AJvYcCUB8uWzbsoxKmuVqHqJRsSwHIQOvO3T8GNAQZEP4KE36T7NyPgDVIj0u+HLPJv6wuw68v+z/zkp2W8P@nongnu.org X-Gm-Message-State: AOJu0YwKOjJnqkfiC3ZThHlMDm47yCxtmWs4Gp1DAkOXAmT6P7LcGPEt ANPzAvFdxKfk24VLAgzQ11dpR/vPNooJ/2HRYVbK8sqoLec4KngG8zQOEZeeMyhVBWhip5OB0md Yr2MKuwbQnQ== X-Google-Smtp-Source: AGHT+IH9ksU/VzNkMzM/zI4wQS1vQDv6e4vH3mTiJ3Uc53r6qMxna1e/vrPAy+fg16ij1ONC1CUVOy8mde3QTQ== X-Received: from pgbdr3.prod.google.com ([2002:a05:6a02:fc3:b0:7fd:9a34:d2df]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:e92:b0:1e1:a885:3e21 with SMTP id adf61e73a8af0-1e5e044ed2cmr36956461637.7.1735201709805; Thu, 26 Dec 2024 00:28:29 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:50 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-8-wuhaotsh@google.com> Subject: [PATCH v2 07/17] hw/misc: Add nr_regs and cold_reset_values to NPCM GCR From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3rRNtZwgKCsoCAxq498xw44w1u.s426u2A-tuBu1343w3A.47w@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201751787116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These 2 values are different between NPCM7XX and NPCM8XX GCRs. So we add them to the class and assign different values to them. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm_gcr.c | 24 +++++++++++++++--------- include/hw/misc/npcm_gcr.h | 13 +++++++++++-- 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index 0959f2e5c4..295073ba14 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -69,7 +69,7 @@ enum NPCM7xxGCRRegisters { NPCM7XX_GCR_REGS_END, }; =20 -static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] =3D { +static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_GCR_NR_REGS] =3D { [NPCM7XX_GCR_PDID] =3D 0x04a92750, /* Poleg A1 */ [NPCM7XX_GCR_MISCPE] =3D 0x0000ffff, [NPCM7XX_GCR_SPSWC] =3D 0x00000003, @@ -88,8 +88,9 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset= , unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); NPCMGCRState *s =3D opaque; + NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(s); =20 - if (reg >=3D NPCM7XX_GCR_NR_REGS) { + if (reg >=3D c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -106,11 +107,12 @@ static void npcm_gcr_write(void *opaque, hwaddr offse= t, { uint32_t reg =3D offset / sizeof(uint32_t); NPCMGCRState *s =3D opaque; + NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(s); uint32_t value =3D v; =20 - trace_npcm_gcr_write(offset, value); + trace_npcm_gcr_write(offset, v); =20 - if (reg >=3D NPCM7XX_GCR_NR_REGS) { + if (reg >=3D c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -156,10 +158,10 @@ static const struct MemoryRegionOps npcm_gcr_ops =3D { static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type) { NPCMGCRState *s =3D NPCM_GCR(obj); + NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(obj); =20 - QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values)); - - memcpy(s->regs, cold_reset_values, sizeof(s->regs)); + memcpy(s->regs, c->cold_reset_values, c->nr_regs * sizeof(uint32_t)); + /* These 3 registers are at the same location in both 7xx and 8xx. */ s->regs[NPCM7XX_GCR_PWRON] =3D s->reset_pwron; s->regs[NPCM7XX_GCR_MDLR] =3D s->reset_mdlr; s->regs[NPCM7XX_GCR_INTCR3] =3D s->reset_intcr3; @@ -224,7 +226,7 @@ static const VMStateDescription vmstate_npcm_gcr =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM7XX_GCR_NR_REGS), + VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM_GCR_MAX_NR_REGS), VMSTATE_END_OF_LIST(), }, }; @@ -238,7 +240,6 @@ static void npcm_gcr_class_init(ObjectClass *klass, voi= d *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS); dc->realize =3D npcm_gcr_realize; dc->vmsd =3D &vmstate_npcm_gcr; =20 @@ -247,13 +248,17 @@ static void npcm_gcr_class_init(ObjectClass *klass, v= oid *data) =20 static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data) { + NPCMGCRClass *c =3D NPCM_GCR_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 + QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM_GCR_MAX_NR_REGS); QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END !=3D NPCM7XX_GCR_NR_REGS); dc->desc =3D "NPCM7xx System Global Control Registers"; rc->phases.enter =3D npcm7xx_gcr_enter_reset; =20 + c->nr_regs =3D NPCM7XX_GCR_NR_REGS; + c->cold_reset_values =3D npcm7xx_cold_reset_values; } =20 static const TypeInfo npcm_gcr_info[] =3D { @@ -262,6 +267,7 @@ static const TypeInfo npcm_gcr_info[] =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(NPCMGCRState), .instance_init =3D npcm_gcr_init, + .class_size =3D sizeof(NPCMGCRClass), .class_init =3D npcm_gcr_class_init, .abstract =3D true, }, diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h index 6d3d00d260..9af24e5cdc 100644 --- a/include/hw/misc/npcm_gcr.h +++ b/include/hw/misc/npcm_gcr.h @@ -18,6 +18,7 @@ =20 #include "exec/memory.h" #include "hw/sysbus.h" +#include "qom/object.h" =20 /* * NPCM7XX PWRON STRAP bit fields @@ -53,6 +54,7 @@ * Number of registers in our device state structure. Don't change this wi= thout * incrementing the version_id in the vmstate. */ +#define NPCM_GCR_MAX_NR_REGS NPCM7XX_GCR_NR_REGS #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) =20 typedef struct NPCMGCRState { @@ -60,15 +62,22 @@ typedef struct NPCMGCRState { =20 MemoryRegion iomem; =20 - uint32_t regs[NPCM7XX_GCR_NR_REGS]; + uint32_t regs[NPCM_GCR_MAX_NR_REGS]; =20 uint32_t reset_pwron; uint32_t reset_mdlr; uint32_t reset_intcr3; } NPCMGCRState; =20 +typedef struct NPCMGCRClass { + SysBusDeviceClass parent; + + size_t nr_regs; + const uint32_t *cold_reset_values; +} NPCMGCRClass; + #define TYPE_NPCM_GCR "npcm-gcr" #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" -OBJECT_DECLARE_SIMPLE_TYPE(NPCMGCRState, NPCM_GCR) +OBJECT_DECLARE_TYPE(NPCMGCRState, NPCMGCRClass, NPCM_GCR) =20 #endif /* NPCM_GCR_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201792; cv=none; d=zohomail.com; s=zohoarc; b=XSvwDP3RnEyCN5vSD+dnszYtUD4ZsmPRyR9c12m6pFgthu8nCprngWnwIxUCbOJqhMYhESpckTPZvFS4ibwoX/5uR8yZcCWqrmmP494cJ1gMW20FdwrwpDoaCtcWiFyXT0nnOmeNe5cTiH4TvK7iwFeDpJeKl6VAT+LbXpeVNps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201792; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=p/jxfIHJDMTwko8UxNWSo9R6EjZKYMOEyl+7ZxDg9LY=; b=VYljfsbVavydYFI77YVkNLIcraz4U2VTD4XX79XLSSesevlnKVlnAmUCyDydGdpYngY8gklg6Olsn3JXfWcKRW2RABmMJWaByTuQFOdhXtc547bOxGhHS/HMUH3a4kBp9R6M9rB8kmvYkfC1LJ02DMcwSeZAW3ExLAnvyMkukwc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201792098516.6961971202815; Thu, 26 Dec 2024 00:29:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEU-0003rj-PD; Thu, 26 Dec 2024 03:28:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3sRNtZwgKCs4GE1u8DC108805y.w86Ay6E-xyFy578707E.8B0@flex--wuhaotsh.bounces.google.com>) id 1tQjET-0003kN-80 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:37 -0500 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3sRNtZwgKCs4GE1u8DC108805y.w86Ay6E-xyFy578707E.8B0@flex--wuhaotsh.bounces.google.com>) id 1tQjER-0001Cz-2e for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:36 -0500 Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-2ef114d8346so7619305a91.0 for ; Thu, 26 Dec 2024 00:28:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201713; x=1735806513; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=p/jxfIHJDMTwko8UxNWSo9R6EjZKYMOEyl+7ZxDg9LY=; b=yYwLk5dOYKw7ZJWAG8EpaA8x3XeRekr/YUGLjn5lJwTceGfBdS1iHTgOHovPr7GN1e EBaNglukv/A17CQdRQXyHAggsy3UGGgotB/uB0wWb1QH5XW3Pz2fl1HfLN7/uPiIZes8 wWR5xQUShet7bUyjBNwAwXEWOT8AlmBb53HRxlE8lgH7aImjqddr+knECriFgxzWqY1A XLU0IJEK5wpx7wdoBrPBkZ6WgTBzmk1Sp1K9XEeJCOfH4dAPwqAaymmpZRTrvKszOeNj ptTvjXsoJLwnM2bBALIQtl2FvRy5gqQrHSHlZC7MxRooKWHp5o9UjaaSpmpN/5WHVPhj vuyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201713; x=1735806513; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=p/jxfIHJDMTwko8UxNWSo9R6EjZKYMOEyl+7ZxDg9LY=; b=ETXc+IOX+ha2JBD1XEP7Thl4EBulyUNJWuE+OaPgGUhUvTtH/MoFl4VT+qqhOOOo6U Cd9/aZEyqHmu0VFUyP+8i9c0fsc2pwI/Q4XIWr5exFSVlD+EGYYmtJe5jrAjUAbrm4OO RtaXzVqtkFQX5PMrj4mYkjgMwxKOjQ4B5SfvO0zBuiOWwKnKfxxrrL5Q6ZAg64/Q4hGi kGRKGWXCRVaLnIt6ZQpCtIh9rGGXL87jksKnXprwjZcwIuAkhrYhFX7d/QewyfYqrYNa MyE6fdPVi1UcDeIJ0FfY38vbbC+PNu7HW5OTL/TZx/h7jbTd3fWvKaI0VxcKxpmRst5z f1Ag== X-Forwarded-Encrypted: i=1; AJvYcCVYLzheWgXaT7M+OrzB9a9d03PdvJvbNB+ODYzxypDldCj44vm2NBerwNUU6xNDRKeXGCVNWXZXfPYD@nongnu.org X-Gm-Message-State: AOJu0YwuMGwyWxUTXefOAwDA80iLAhZnSWJuEEsh8uWIgUBNY8NGw3QI A+4H6Ur07H+7GcLJ7BTsVcszeaDfTNMZPcMowDEtDBoRJKjwzRybtm300fcirFhJbnDDNLmzWGa ElTNsEFWiSQ== X-Google-Smtp-Source: AGHT+IEgs8S0ajZ5pEql69Fjj8edDb8W/WucjWGEMnTLbm0X8ZqP1MNGcO0P0tKXgEqdA4lIiAEfQP71klelDA== X-Received: from pfar2.prod.google.com ([2002:a05:6a00:a902:b0:726:d6e6:a38]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:124a:b0:725:f4c6:6b68 with SMTP id d2e1a72fcca58-72abde404e9mr31313313b3a.4.1735201713351; Thu, 26 Dec 2024 00:28:33 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:51 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-9-wuhaotsh@google.com> Subject: [PATCH v2 08/17] hw/misc: Add support for NPCM8XX GCR From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::104a; envelope-from=3sRNtZwgKCs4GE1u8DC108805y.w86Ay6E-xyFy578707E.8B0@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x104a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201793768116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm_gcr.c | 131 ++++++++++++++++++++++++++++++++++++- include/hw/misc/npcm_gcr.h | 6 +- 2 files changed, 134 insertions(+), 3 deletions(-) diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index 295073ba14..52d0fa07ea 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx System Global Control Registers. + * Nuvoton NPCM7xx/8xx System Global Control Registers. * * Copyright 2020 Google LLC * @@ -84,6 +84,118 @@ static const uint32_t npcm7xx_cold_reset_values[NPCM7XX= _GCR_NR_REGS] =3D { [NPCM7XX_GCR_USB2PHYCTL] =3D 0x034730e4, }; =20 +enum NPCM8xxGCRRegisters { + NPCM8XX_GCR_PDID, + NPCM8XX_GCR_PWRON, + NPCM8XX_GCR_MISCPE =3D 0x014 / sizeof(uint32_t), + NPCM8XX_GCR_FLOCKR2 =3D 0x020 / sizeof(uint32_t), + NPCM8XX_GCR_FLOCKR3, + NPCM8XX_GCR_A35_MODE =3D 0x034 / sizeof(uint32_t), + NPCM8XX_GCR_SPSWC, + NPCM8XX_GCR_INTCR, + NPCM8XX_GCR_INTSR, + NPCM8XX_GCR_HIFCR =3D 0x050 / sizeof(uint32_t), + NPCM8XX_GCR_INTCR2 =3D 0x060 / sizeof(uint32_t), + NPCM8XX_GCR_SRCNT =3D 0x068 / sizeof(uint32_t), + NPCM8XX_GCR_RESSR, + NPCM8XX_GCR_RLOCKR1, + NPCM8XX_GCR_FLOCKR1, + NPCM8XX_GCR_DSCNT, + NPCM8XX_GCR_MDLR, + NPCM8XX_GCR_SCRPAD_C =3D 0x080 / sizeof(uint32_t), + NPCM8XX_GCR_SCRPAD_B, + NPCM8XX_GCR_DAVCLVLR =3D 0x098 / sizeof(uint32_t), + NPCM8XX_GCR_INTCR3, + NPCM8XX_GCR_PCIRCTL =3D 0x0a0 / sizeof(uint32_t), + NPCM8XX_GCR_VSINTR, + NPCM8XX_GCR_SD2SUR1 =3D 0x0b4 / sizeof(uint32_t), + NPCM8XX_GCR_SD2SUR2, + NPCM8XX_GCR_INTCR4 =3D 0x0c0 / sizeof(uint32_t), + NPCM8XX_GCR_CPCTL =3D 0x0d0 / sizeof(uint32_t), + NPCM8XX_GCR_CP2BST, + NPCM8XX_GCR_B2CPNT, + NPCM8XX_GCR_CPPCTL, + NPCM8XX_GCR_I2CSEGSEL =3D 0x0e0 / sizeof(uint32_t), + NPCM8XX_GCR_I2CSEGCTL, + NPCM8XX_GCR_VSRCR, + NPCM8XX_GCR_MLOCKR, + NPCM8XX_GCR_SCRPAD =3D 0x13c / sizeof(uint32_t), + NPCM8XX_GCR_USB1PHYCTL, + NPCM8XX_GCR_USB2PHYCTL, + NPCM8XX_GCR_USB3PHYCTL, + NPCM8XX_GCR_MFSEL1 =3D 0x260 / sizeof(uint32_t), + NPCM8XX_GCR_MFSEL2, + NPCM8XX_GCR_MFSEL3, + NPCM8XX_GCR_MFSEL4, + NPCM8XX_GCR_MFSEL5, + NPCM8XX_GCR_MFSEL6, + NPCM8XX_GCR_MFSEL7, + NPCM8XX_GCR_MFSEL_LK1 =3D 0x280 / sizeof(uint32_t), + NPCM8XX_GCR_MFSEL_LK2, + NPCM8XX_GCR_MFSEL_LK3, + NPCM8XX_GCR_MFSEL_LK4, + NPCM8XX_GCR_MFSEL_LK5, + NPCM8XX_GCR_MFSEL_LK6, + NPCM8XX_GCR_MFSEL_LK7, + NPCM8XX_GCR_MFSEL_SET1 =3D 0x2a0 / sizeof(uint32_t), + NPCM8XX_GCR_MFSEL_SET2, + NPCM8XX_GCR_MFSEL_SET3, + NPCM8XX_GCR_MFSEL_SET4, + NPCM8XX_GCR_MFSEL_SET5, + NPCM8XX_GCR_MFSEL_SET6, + NPCM8XX_GCR_MFSEL_SET7, + NPCM8XX_GCR_MFSEL_CLR1 =3D 0x2c0 / sizeof(uint32_t), + NPCM8XX_GCR_MFSEL_CLR2, + NPCM8XX_GCR_MFSEL_CLR3, + NPCM8XX_GCR_MFSEL_CLR4, + NPCM8XX_GCR_MFSEL_CLR5, + NPCM8XX_GCR_MFSEL_CLR6, + NPCM8XX_GCR_MFSEL_CLR7, + NPCM8XX_GCR_WD0RCRLK =3D 0x400 / sizeof(uint32_t), + NPCM8XX_GCR_WD1RCRLK, + NPCM8XX_GCR_WD2RCRLK, + NPCM8XX_GCR_SWRSTC1LK, + NPCM8XX_GCR_SWRSTC2LK, + NPCM8XX_GCR_SWRSTC3LK, + NPCM8XX_GCR_TIPRSTCLK, + NPCM8XX_GCR_CORSTCLK, + NPCM8XX_GCR_WD0RCRBLK, + NPCM8XX_GCR_WD1RCRBLK, + NPCM8XX_GCR_WD2RCRBLK, + NPCM8XX_GCR_SWRSTC1BLK, + NPCM8XX_GCR_SWRSTC2BLK, + NPCM8XX_GCR_SWRSTC3BLK, + NPCM8XX_GCR_TIPRSTCBLK, + NPCM8XX_GCR_CORSTCBLK, + /* 64 scratch pad registers start here. 0xe00 ~ 0xefc */ + NPCM8XX_GCR_SCRPAD_00 =3D 0xe00 / sizeof(uint32_t), + /* 32 semaphore registers start here. 0xf00 ~ 0xf7c */ + NPCM8XX_GCR_GP_SEMFR_00 =3D 0xf00 / sizeof(uint32_t), + NPCM8XX_GCR_REGS_END =3D 0xf80 / sizeof(uint32_t), +}; + +static const uint32_t npcm8xx_cold_reset_values[NPCM8XX_GCR_NR_REGS] =3D { + [NPCM8XX_GCR_PDID] =3D 0x04a35850, /* Arbel A1 */ + [NPCM8XX_GCR_MISCPE] =3D 0x0000ffff, + [NPCM8XX_GCR_A35_MODE] =3D 0xfff4ff30, + [NPCM8XX_GCR_SPSWC] =3D 0x00000003, + [NPCM8XX_GCR_INTCR] =3D 0x0010035e, + [NPCM8XX_GCR_HIFCR] =3D 0x0000004e, + [NPCM8XX_GCR_SD2SUR1] =3D 0xfdc80000, + [NPCM8XX_GCR_SD2SUR2] =3D 0x5200b130, + [NPCM8XX_GCR_INTCR2] =3D (1U << 19), /* DDR initialized */ + [NPCM8XX_GCR_RESSR] =3D 0x80000000, + [NPCM8XX_GCR_DAVCLVLR] =3D 0x5a00f3cf, + [NPCM8XX_GCR_INTCR3] =3D 0x5e001002, + [NPCM8XX_GCR_VSRCR] =3D 0x00004800, + [NPCM8XX_GCR_SCRPAD] =3D 0x00000008, + [NPCM8XX_GCR_USB1PHYCTL] =3D 0x034730e4, + [NPCM8XX_GCR_USB2PHYCTL] =3D 0x034730e4, + [NPCM8XX_GCR_USB3PHYCTL] =3D 0x034730e4, + /* All 32 semaphores should be initialized to 1. */ + [NPCM8XX_GCR_GP_SEMFR_00...NPCM8XX_GCR_REGS_END - 1] =3D 0x00000001, +}; + static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); @@ -261,6 +373,18 @@ static void npcm7xx_gcr_class_init(ObjectClass *klass,= void *data) c->cold_reset_values =3D npcm7xx_cold_reset_values; } =20 +static void npcm8xx_gcr_class_init(ObjectClass *klass, void *data) +{ + NPCMGCRClass *c =3D NPCM_GCR_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + QEMU_BUILD_BUG_ON(NPCM8XX_GCR_REGS_END > NPCM_GCR_MAX_NR_REGS); + QEMU_BUILD_BUG_ON(NPCM8XX_GCR_REGS_END !=3D NPCM8XX_GCR_NR_REGS); + dc->desc =3D "NPCM8xx System Global Control Registers"; + c->nr_regs =3D NPCM8XX_GCR_NR_REGS; + c->cold_reset_values =3D npcm8xx_cold_reset_values; +} + static const TypeInfo npcm_gcr_info[] =3D { { .name =3D TYPE_NPCM_GCR, @@ -276,5 +400,10 @@ static const TypeInfo npcm_gcr_info[] =3D { .parent =3D TYPE_NPCM_GCR, .class_init =3D npcm7xx_gcr_class_init, }, + { + .name =3D TYPE_NPCM8XX_GCR, + .parent =3D TYPE_NPCM_GCR, + .class_init =3D npcm8xx_gcr_class_init, + }, }; DEFINE_TYPES(npcm_gcr_info) diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h index 9af24e5cdc..9ac76ca9ab 100644 --- a/include/hw/misc/npcm_gcr.h +++ b/include/hw/misc/npcm_gcr.h @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx System Global Control Registers. + * Nuvoton NPCM7xx/8xx System Global Control Registers. * * Copyright 2020 Google LLC * @@ -54,8 +54,9 @@ * Number of registers in our device state structure. Don't change this wi= thout * incrementing the version_id in the vmstate. */ -#define NPCM_GCR_MAX_NR_REGS NPCM7XX_GCR_NR_REGS +#define NPCM_GCR_MAX_NR_REGS NPCM8XX_GCR_NR_REGS #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) +#define NPCM8XX_GCR_NR_REGS (0xf80 / sizeof(uint32_t)) =20 typedef struct NPCMGCRState { SysBusDevice parent; @@ -78,6 +79,7 @@ typedef struct NPCMGCRClass { =20 #define TYPE_NPCM_GCR "npcm-gcr" #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" +#define TYPE_NPCM8XX_GCR "npcm8xx-gcr" OBJECT_DECLARE_TYPE(NPCMGCRState, NPCMGCRClass, NPCM_GCR) =20 #endif /* NPCM_GCR_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201725; cv=none; d=zohomail.com; s=zohoarc; b=geZXCoJ6+Fsf5WwtiMKOIeFy+TyXuVV/OiTJ051P/zQpgZ6zpoKxlwvz0M5WjOnxOXVrD0ROdcxf2wx70zyUnl6UmeSUcUXeBj+13nvP/l6oMMbf7scSQmDlYEiuNGi7PdL7uIsNiH7k5MD4cPOBisxszZt26U+0+452FemgKXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201725; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VvRWJc9sthcySpDtWp0rsZQlL3SZjKq9uWDFTrlLObQ=; b=IGIR2t6s3yWRgvOoSZSIDP/A/J8XPgH9cloRxM3oD132d6Vd/VEtFtYzyytRTW5PM34kfa6Ri9lkWV9DAv3XA3LTyMUec1b2iFF71COcBsG35FNM8pxBawZlznO0Khw/4RyOeuPVH7cFidPRB8oKW4zdws9l14IpEPSwjTJ+u0E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201725348551.110020909535; Thu, 26 Dec 2024 00:28:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEY-0004Bm-Vl; Thu, 26 Dec 2024 03:28:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3tBNtZwgKCtEJH4xBGF43BB381.zB9D19H-01I18ABA3AH.BE3@flex--wuhaotsh.bounces.google.com>) id 1tQjEW-00043p-Ob for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:40 -0500 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3tBNtZwgKCtEJH4xBGF43BB381.zB9D19H-01I18ABA3AH.BE3@flex--wuhaotsh.bounces.google.com>) id 1tQjEV-0001Da-6N for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:40 -0500 Received: by mail-pj1-x1049.google.com with SMTP id 98e67ed59e1d1-2ee3206466aso8005534a91.1 for ; Thu, 26 Dec 2024 00:28:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201717; x=1735806517; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=VvRWJc9sthcySpDtWp0rsZQlL3SZjKq9uWDFTrlLObQ=; b=TVoki9lG4yfVKsd0JqX3lbq/K18fnqdYBGjHw06xDXPFBIm6JvY7V1Ri2r3XxthkJf Be0OsTpzXly6Vsx9MAmf8ot4z5Wz/Yf4NU8wBcitJGn6l01rhAAiPG8QsPMjFoh73msX evHME2hnEnyAMRGG1Ry5a8iXlQbOHCpdzsawvvCzTPmY92QtgJN2P4mgmOr4VY7pWfYK KO6Nr8DxDX0gh218LsAh5985vWW1XLlIBF7rSG21HXFz+m5Xb/QJLOFA2NSkqOsKhYo1 AoEB2BrT/q5eFgnHscIfDzUt7xT9WRcX2WE7lr7PVDM6NuLk5vejGvrFszRcV99TbWhi T8FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201717; x=1735806517; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VvRWJc9sthcySpDtWp0rsZQlL3SZjKq9uWDFTrlLObQ=; b=IjDhMKDeNz5B38pWAATy06flsBLLakza8ow8h7/8GODOQoKfBzGZOepYbZeZD3yZF+ KTQEplGtv+MzaTwZMkSyy6E5J+OJFVsNhxtAhWBROh0A+YAtUaxC+hjNXkUcF2NdouPV SYhua2wfIjAI9CSk4aOZo6oaDWPO+Wu9gF162QGBfadaNRJVfCLLhaO+79O8oycgeuVF SrcESYXjSu83SW6ZA8mdVB/a47eJBi+3UOHdof5mWDBE3pNbQC9S/lSKzMovGU6JAcIn waw1FUl1llhxKYQqhqyOHvwQcFuHo1K1+hHc3TZW56PsgLGmAj+hXW5ZNi9fFH6/FzH+ h+ZA== X-Forwarded-Encrypted: i=1; AJvYcCWmLVw/eMDSMCDqtteyJLcIp6TTBYeYE1/FtA/OUW81SHfgkVzsq6srrQMCnIg7yH+AU/svlF/0NIzU@nongnu.org X-Gm-Message-State: AOJu0YzUF8h+5e2Nzc9tXN4QBZ9UmUY5xL3PQfOpTNVRg6R30Xw3ZyT+ wSBNtQaQ3bXR4AsGX50hG77WWySUNwqa1XQQnFRhkKeRj5GJkhAZbQw4Jsm3gjRu56A4rZQgIFB hGP6drzO3Cw== X-Google-Smtp-Source: AGHT+IFs6U0OrtZIIEVYAUTbIXox3B0joaxFLxqXILjRGAfP0mEFhOKfqEICLz5xKvCl1coDAjSAndny+KbjDw== X-Received: from pjbnb13.prod.google.com ([2002:a17:90b:35cd:b0:2ef:d283:5089]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:c2c4:b0:2ee:463d:8e8d with SMTP id 98e67ed59e1d1-2f4437bf735mr40289577a91.14.1735201716837; Thu, 26 Dec 2024 00:28:36 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:52 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-10-wuhaotsh@google.com> Subject: [PATCH v2 09/17] hw/misc: Store DRAM size in NPCM8XX GCR Module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=3tBNtZwgKCtEJH4xBGF43BB381.zB9D19H-01I18ABA3AH.BE3@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201725584116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR module. Since we don't simulate a detailed memory controller, we need to store this information directly similar to the NPCM7XX's INCTR3 register. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm_gcr.c | 24 ++++++++++++++++++++++++ include/hw/misc/npcm_gcr.h | 1 + 2 files changed, 25 insertions(+) diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index 52d0fa07ea..a4c9643119 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -279,6 +279,19 @@ static void npcm7xx_gcr_enter_reset(Object *obj, Reset= Type type) s->regs[NPCM7XX_GCR_INTCR3] =3D s->reset_intcr3; } =20 +static void npcm8xx_gcr_enter_reset(Object *obj, ResetType type) +{ + NPCMGCRState *s =3D NPCM_GCR(obj); + NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(obj); + + memcpy(s->regs, c->cold_reset_values, c->nr_regs * sizeof(uint32_t)); + /* These 3 registers are at the same location in both 7xx and 8xx. */ + s->regs[NPCM8XX_GCR_PWRON] =3D s->reset_pwron; + s->regs[NPCM8XX_GCR_MDLR] =3D s->reset_mdlr; + s->regs[NPCM8XX_GCR_INTCR3] =3D s->reset_intcr3; + s->regs[NPCM8XX_GCR_SCRPAD_B] =3D s->reset_scrpad_b; +} + static void npcm_gcr_realize(DeviceState *dev, Error **errp) { ERRP_GUARD(); @@ -322,6 +335,14 @@ static void npcm_gcr_realize(DeviceState *dev, Error *= *errp) * https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408db= aad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244 */ s->reset_intcr3 |=3D ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8; + + /* + * The boot block starting from 0.0.6 for NPCM8xx SoCs stores the DRAM= size + * in the SCRPAD2 registers. We need to set this field correctly since + * the initialization is skipped as we mentioned above. + * https://github.com/Nuvoton-Israel/u-boot/blob/npcm8mnx-v2019.01_tmp= /board/nuvoton/arbel/arbel.c#L737 + */ + s->reset_scrpad_b =3D dram_size; } =20 static void npcm_gcr_init(Object *obj) @@ -371,18 +392,21 @@ static void npcm7xx_gcr_class_init(ObjectClass *klass= , void *data) =20 c->nr_regs =3D NPCM7XX_GCR_NR_REGS; c->cold_reset_values =3D npcm7xx_cold_reset_values; + rc->phases.enter =3D npcm7xx_gcr_enter_reset; } =20 static void npcm8xx_gcr_class_init(ObjectClass *klass, void *data) { NPCMGCRClass *c =3D NPCM_GCR_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 QEMU_BUILD_BUG_ON(NPCM8XX_GCR_REGS_END > NPCM_GCR_MAX_NR_REGS); QEMU_BUILD_BUG_ON(NPCM8XX_GCR_REGS_END !=3D NPCM8XX_GCR_NR_REGS); dc->desc =3D "NPCM8xx System Global Control Registers"; c->nr_regs =3D NPCM8XX_GCR_NR_REGS; c->cold_reset_values =3D npcm8xx_cold_reset_values; + rc->phases.enter =3D npcm8xx_gcr_enter_reset; } =20 static const TypeInfo npcm_gcr_info[] =3D { diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h index 9ac76ca9ab..d81bb9afb2 100644 --- a/include/hw/misc/npcm_gcr.h +++ b/include/hw/misc/npcm_gcr.h @@ -68,6 +68,7 @@ typedef struct NPCMGCRState { uint32_t reset_pwron; uint32_t reset_mdlr; uint32_t reset_intcr3; + uint32_t reset_scrpad_b; } NPCMGCRState; =20 typedef struct NPCMGCRClass { --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201784; cv=none; d=zohomail.com; s=zohoarc; b=PmEc4AlSfu0zrj3/xJmxiajfz1sBoU7WWEJCS0HBvVrM6+mh84NhCIq+4A5UidSD2GHNgNXNM8Ok58jzT81K+V8itDAB9tF/JuLq0IjwUupHyscduo1oQ/Fxqu6W7UOzbas4/MnxOlJvY/l99UyvNy3Sc4Xb+jMkLlM59jMkBFQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201784; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dSh3O5WaaKwNo1iaUvTSpo+z9u0dQr4Ul55JCilzC1E=; b=ForUj9keYh4aY0Y6z6qbssAE6EMzYJyDQUZlfD9ykmlTPy1zcTUA3Zs7ZyWSdq2NDgANoDDzWFcf2y8b7GfLKpmwIvZmHZO884VZEc9B2qza1Xbsdc/PXFz5MzqlQpNVtvkifOsm8bei/hsSwKv7dZs7keu1DGnU+KNEAGNSYsI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201784837428.00468357435363; Thu, 26 Dec 2024 00:29:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEe-0004pL-6C; Thu, 26 Dec 2024 03:28:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3uBNtZwgKCtUNL81FKJ87FF7C5.3FDH5DL-45M5CEFE7EL.FI7@flex--wuhaotsh.bounces.google.com>) id 1tQjEa-0004US-D6 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:44 -0500 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3uBNtZwgKCtUNL81FKJ87FF7C5.3FDH5DL-45M5CEFE7EL.FI7@flex--wuhaotsh.bounces.google.com>) id 1tQjEY-0001EA-Az for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:44 -0500 Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-216728b170cso76654655ad.2 for ; Thu, 26 Dec 2024 00:28:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201720; x=1735806520; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=dSh3O5WaaKwNo1iaUvTSpo+z9u0dQr4Ul55JCilzC1E=; b=RJ8p3k9ljx/jss4BYVaRohTDS1CjIRx6iOn4mKjcaDzVxNeGGp7zhq1Yjxrf3/4VST J30XnN11a/GsaBqZGjnnIkIq1fNbI5TTnD+wIP9Wpazqr8hWgM4AVddigxdDNYhfx81K EoUthbjyJEoiEIpwntbEsSXwok/tOvH+NnOpoGOpmQj2MfAVFMJeesoA8OIERtJZuEMX jZSfeOA18mbDoFqTDnNrwGRj3e7k+YEp2XqVMuH5s2h9eIG8s8+6fVGsk+/kIqOINan3 vvkD8PgXEgu7jkXeqyo6QhmWAF/bhXbmbOR3HoHHn0Vkv6OdYHbwSlXVSn/BQiwgApCd 6wLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201720; x=1735806520; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dSh3O5WaaKwNo1iaUvTSpo+z9u0dQr4Ul55JCilzC1E=; b=mm2ITUgF2bP7tbMZqB4HY6MRcO6ckZLgI6PTH76j5ZGjbKv7Xoo13+MkQXIwEOVZXc i8Q+Q7jV8jIWU/GRNNYXEbCd9+X2GmkhzWOCOIkq+FTxo8zvaZmN7eGVUgo6zSmGub0X NfXIfXFbI9TQybf5XAPV6eaPx9ydNZPCJ+aMn32d97pboP8ZkfWCm+kaCjiIaLl80YI8 asUNFA/HtZ6Xtu6mbzkVC7aqlz4i2lC6c3SGNAX7k3AFjFCnnHxyXa6KmQaQ6W7DhC9B WGy9vnqgLX2XIdFQrvYrg1zIyr2yDFzP3IUU2oSyR440BnErstLp5ASanjsGYf0nlPVL q+Qg== X-Forwarded-Encrypted: i=1; AJvYcCUcCBQWBBGFCT6ddTG1g34vWmvCh+LTYvjWLxN2IfujJz04+5rx6ltO+TSCW2kx/8E+m+I2l50oJMre@nongnu.org X-Gm-Message-State: AOJu0YzMZkFTyqprsOatii3jsOh1jyXFRuHU/DTbmoZTxPoQudyNCzyW RTlowD5iGiPheCUy3eXHkWFcDjoVA2+jJPhc+Az+PFoAYfcIEEPP86gSYpHDGeGPlBZZNDHj775 whyrFJ+QZwA== X-Google-Smtp-Source: AGHT+IGY6mIalT7T0WEgnWg5x1oPmyOhTr/N+z/j3ZrDV5dn/nuVsSxbd4L1QnagybxWz4seL8Q2YN88wnP03g== X-Received: from pgcs71.prod.google.com ([2002:a63:774a:0:b0:7ff:d6:4f07]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:4986:b0:1e1:b1bb:87a0 with SMTP id adf61e73a8af0-1e606dfe60fmr18479549637.34.1735201720267; Thu, 26 Dec 2024 00:28:40 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:53 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-11-wuhaotsh@google.com> Subject: [PATCH v2 10/17] hw/misc: Support 8-bytes memop in NPCM GCR module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3uBNtZwgKCtUNL81FKJ87FF7C5.3FDH5DL-45M5CEFE7EL.FI7@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201785836116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NPCM8xx GCR device can be accessed with 64-bit memory operations. This patch supports that. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm_gcr.c | 94 +++++++++++++++++++++++++++++++++----------- hw/misc/trace-events | 4 +- 2 files changed, 74 insertions(+), 24 deletions(-) diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index a4c9643119..7dfdd3d74b 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -201,6 +201,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offs= et, unsigned size) uint32_t reg =3D offset / sizeof(uint32_t); NPCMGCRState *s =3D opaque; NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(s); + uint64_t value; =20 if (reg >=3D c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, @@ -209,9 +210,21 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr off= set, unsigned size) return 0; } =20 - trace_npcm_gcr_read(offset, s->regs[reg]); + switch (size) { + case 4: + value =3D s->regs[reg]; + break; + + case 8: + value =3D s->regs[reg] + (((uint64_t)s->regs[reg + 1]) << 32); + break; + + default: + g_assert_not_reached(); + } =20 - return s->regs[reg]; + trace_npcm_gcr_read(offset, value); + return value; } =20 static void npcm_gcr_write(void *opaque, hwaddr offset, @@ -231,29 +244,65 @@ static void npcm_gcr_write(void *opaque, hwaddr offse= t, return; } =20 - switch (reg) { - case NPCM7XX_GCR_PDID: - case NPCM7XX_GCR_PWRON: - case NPCM7XX_GCR_INTSR: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", - __func__, offset); - return; - - case NPCM7XX_GCR_RESSR: - case NPCM7XX_GCR_CP2BST: - /* Write 1 to clear */ - value =3D s->regs[reg] & ~value; + switch (size) { + case 4: + switch (reg) { + case NPCM7XX_GCR_PDID: + case NPCM7XX_GCR_PWRON: + case NPCM7XX_GCR_INTSR: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: register @ 0x%04" HWADDR_PRIx " is read-onl= y\n", + __func__, offset); + return; + + case NPCM7XX_GCR_RESSR: + case NPCM7XX_GCR_CP2BST: + /* Write 1 to clear */ + value =3D s->regs[reg] & ~value; + break; + + case NPCM7XX_GCR_RLOCKR1: + case NPCM7XX_GCR_MDLR: + /* Write 1 to set */ + value |=3D s->regs[reg]; + break; + }; + s->regs[reg] =3D value; break; =20 - case NPCM7XX_GCR_RLOCKR1: - case NPCM7XX_GCR_MDLR: - /* Write 1 to set */ - value |=3D s->regs[reg]; + case 8: + s->regs[reg] =3D value; + s->regs[reg + 1] =3D v >> 32; break; - }; =20 - s->regs[reg] =3D value; + default: + g_assert_not_reached(); + } +} + +static bool npcm_gcr_check_mem_op(void *opaque, hwaddr offset, + unsigned size, bool is_write, + MemTxAttrs attrs) +{ + NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(opaque); + + if (offset >=3D c->nr_regs * sizeof(uint32_t)) { + return false; + } + + switch (size) { + case 4: + return true; + case 8: + if (offset >=3D NPCM8XX_GCR_SCRPAD_00 * sizeof(uint32_t) && + offset < (NPCM8XX_GCR_NR_REGS - 1) * sizeof(uint32_t)) { + return true; + } else { + return false; + } + default: + return false; + } } =20 static const struct MemoryRegionOps npcm_gcr_ops =3D { @@ -262,7 +311,8 @@ static const struct MemoryRegionOps npcm_gcr_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, - .max_access_size =3D 4, + .max_access_size =3D 8, + .accepts =3D npcm_gcr_check_mem_op, .unaligned =3D false, }, }; diff --git a/hw/misc/trace-events b/hw/misc/trace-events index f2d498e862..59c2d4ecc0 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -135,8 +135,8 @@ npcm7xx_clk_read(uint64_t offset, uint32_t value) " off= set: 0x%04" PRIx64 " valu npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 =20 # npcm_gcr.c -npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx32 -npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx32 +npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx64 +npcm_gcr_write(uint64_t offset, uint64_t value) "offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx64 =20 # npcm7xx_mft.c npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: o= ffset: 0x%04" PRIx64 " value: 0x%04" PRIx16 --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201771; cv=none; d=zohomail.com; s=zohoarc; b=RO9KrY5hVX5OLmk3279SYS1QAUXBNnVxbwCw70rCbZiVTFGe4Gz4AghVakv0c6dqPl4mKp+OV0Y8B0DDWuivyxJTVCo4/QpQHKNoSt0dYOcvvtOzB+Tu2DyLmJkcoSc/G9UD+h+9wJ81oUMBstZNssQ3RhauRlZlUpRKPqqs9hs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201771; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IC2Oq7akfcisB2i2J+bOE64Sr4Q2OzTG/tLjT/6CTOs=; b=lzix6/UviiW2NT7Drp93PVX0JqSqoJSYAsZSwb5hIwVz97CMTlfqMq99aQpFTdURyXEnZnx5dl9hIFoDgvz8ImrBphjTSswxMda1cKP852jKDvoI/Qglf+N31IjAh69VmifquC5l5zu0bFrt7G84H7wYDIjLzpKTyfo+m0qphMs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201771149904.7041694534439; Thu, 26 Dec 2024 00:29:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEr-00059U-3S; Thu, 26 Dec 2024 03:29:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3uxNtZwgKCtgQOB4INMBAIIAF8.6IGK8GO-78P8FHIHAHO.ILA@flex--wuhaotsh.bounces.google.com>) id 1tQjEd-0004qj-D5 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:47 -0500 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3uxNtZwgKCtgQOB4INMBAIIAF8.6IGK8GO-78P8FHIHAHO.ILA@flex--wuhaotsh.bounces.google.com>) id 1tQjEb-0001Ei-IQ for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:46 -0500 Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-2164861e1feso77080085ad.1 for ; Thu, 26 Dec 2024 00:28:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201723; x=1735806523; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=IC2Oq7akfcisB2i2J+bOE64Sr4Q2OzTG/tLjT/6CTOs=; b=ks6xc+5vV03vbNPP6KAuWZ5faOI5rNF9TEq7DYehaEn97+qKkXNt3suCmBzDElHZrJ xRkzAthAImu6Kod33jLAkyYdL7kWZyFFLvh5DMa+zVAMAtjoCxsccD7xzCl2IioBP15G sj3C8xvprh0f+1RPV3YKjQ16deral+mpDFwNtjsg+MjTLUz/Kg63nr8Moi36gaR8RQ+r H35Boon1VbGmDy+wI+VaF4iU5MlxN26GM8wb16C66sZHHM0mKbo0beigkH1j66hU62Kd 2ap5yR6XmcddwKhKd9EK0cqOvTlcTc0YxvwgZayOdUvYjRSySnhEM9Co8NnsITY0qmFh LWTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201723; x=1735806523; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=IC2Oq7akfcisB2i2J+bOE64Sr4Q2OzTG/tLjT/6CTOs=; b=coD1qSbZR7bl09u7QlTLViXQsHP2RBCEGrZdE2Y0pHvAc4/j/7TughPO2JZxZJhbVy dKGwLePTWrMXMZyUab/X1r09vUuUe5AkuOHlQtgKI2L1L7oATsSdR0CJUKoHDAFJsh/f 44RK3WueHH5FobK0KoEtu4LFkFZiY3/LsiFezoyP74Fzo385I+iwukChMF7rpW6zmcmT e5eF4eKhV6azYKm0lQjUX+A17gDFlRiBBdZU2Gotbm42MtUUs3l526RJaG/it10Xj7cD 7hgEUI5sCgW8oqz5JlvFQ+e/1IqlJnMLa/rysWYRT0XmKPuW3t3Y1wZnBPCi7xxwZWnp NvWA== X-Forwarded-Encrypted: i=1; AJvYcCWAn2Mx5F4GACCNYeWL3pHykhyT/uEG6skwOsMEroDXSSWUolMNusvBLQRQYq1+h6eR8Fqvas4+FV3n@nongnu.org X-Gm-Message-State: AOJu0YzqVgPTcnjQnjLpFudAXwbZEGliAja8apquk5FB7HaYSV+u5nW9 mSOue86do7ccIZmhRMtTqUsS9KsCe+oh7NiKradkH+RgMIuaewvaoHg3DgzEXAE3V712QQ6ExCV SlZw8+J2gaw== X-Google-Smtp-Source: AGHT+IH62brqOMvJsaiv+7MYOOljrKHRZfemUsZHqP0ISyOV59gtOczhh3hWWLJNnxj0Z9yTnG67C2OW81eVag== X-Received: from pgvz25.prod.google.com ([2002:a65:6659:0:b0:7fc:fac3:7df6]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:3189:b0:1e1:af70:a30b with SMTP id adf61e73a8af0-1e5e07f9b7dmr36487714637.34.1735201723533; Thu, 26 Dec 2024 00:28:43 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:54 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-12-wuhaotsh@google.com> Subject: [PATCH v2 11/17] hw/misc: Rename npcm7xx_clk to npcm_clk From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3uxNtZwgKCtgQOB4INMBAIIAF8.6IGK8GO-78P8FHIHAHO.ILA@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201771749116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NPCM7XX and NPCM8XX have a different set of CLK registers. This commit changes the name of the clk files to be used by both NPCM7XX and NPCM8XX CLK modules. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/meson.build | 2 +- hw/misc/{npcm7xx_clk.c =3D> npcm_clk.c} | 2 +- include/hw/arm/npcm7xx.h | 2 +- include/hw/misc/{npcm7xx_clk.h =3D> npcm_clk.h} | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) rename hw/misc/{npcm7xx_clk.c =3D> npcm_clk.c} (99%) rename include/hw/misc/{npcm7xx_clk.h =3D> npcm_clk.h} (98%) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 9bab048849..743066eb96 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -67,7 +67,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx_rngc.c', )) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( - 'npcm7xx_clk.c', + 'npcm_clk.c', 'npcm_gcr.c', 'npcm7xx_mft.c', 'npcm7xx_pwm.c', diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm_clk.c similarity index 99% rename from hw/misc/npcm7xx_clk.c rename to hw/misc/npcm_clk.c index 46f907b61c..2bcb731099 100644 --- a/hw/misc/npcm7xx_clk.c +++ b/hw/misc/npcm_clk.c @@ -16,7 +16,7 @@ =20 #include "qemu/osdep.h" =20 -#include "hw/misc/npcm7xx_clk.h" +#include "hw/misc/npcm_clk.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/qdev-clock.h" #include "migration/vmstate.h" diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 2e708471ec..e80fd91f20 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -23,7 +23,7 @@ #include "hw/gpio/npcm7xx_gpio.h" #include "hw/i2c/npcm7xx_smbus.h" #include "hw/mem/npcm7xx_mc.h" -#include "hw/misc/npcm7xx_clk.h" +#include "hw/misc/npcm_clk.h" #include "hw/misc/npcm_gcr.h" #include "hw/misc/npcm7xx_mft.h" #include "hw/misc/npcm7xx_pwm.h" diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm_clk.h similarity index 98% rename from include/hw/misc/npcm7xx_clk.h rename to include/hw/misc/npcm_clk.h index 5ed4a4672b..0aef81e10c 100644 --- a/include/hw/misc/npcm7xx_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -13,8 +13,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. */ -#ifndef NPCM7XX_CLK_H -#define NPCM7XX_CLK_H +#ifndef NPCM_CLK_H +#define NPCM_CLK_H =20 #include "exec/memory.h" #include "hw/clock.h" @@ -177,4 +177,4 @@ struct NPCM7xxCLKState { #define TYPE_NPCM7XX_CLK "npcm7xx-clk" OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK) =20 -#endif /* NPCM7XX_CLK_H */ +#endif /* NPCM_CLK_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201771; cv=none; d=zohomail.com; s=zohoarc; b=Bvn1VtouX4t7BuCRMuzS104z7oInnsQWfpMTV0mGLF7Cow0h5moP9ynkCxmQHBZEh+cv52o0Qb2XIMbMjZI03Ox7G48naARQ8kTeKgYQ2wqfvwOK9xrwd1LhNPHM61BxCrGbecln+mOid3+jEq020i7Vb02Hp0b8FP0Hn8bC4FM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201771; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PC3/TomEsHn2pxO3IjMB1Y1E4z7z2FDcg8knqGv0i/0=; b=Bq72XXhho0QUSWqc0xKHr5qUMaVBL61P+jWnhbsbaD8CSuCYtXo9LFGPHykpr5zqrkb54Gwgz/nfmPflMOI5/Duead394dwHPq2FCJIJMD8ZF6d/iJ8EglDuXDmn4+/1r0YPnG9Oix+waGLvT+Ep8BFIgbSc5ZJSc5wCczMuEdQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201771415893.7290263610381; Thu, 26 Dec 2024 00:29:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEy-0005oH-4p; Thu, 26 Dec 2024 03:29:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3vxNtZwgKCtwUSF8MRQFEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--wuhaotsh.bounces.google.com>) id 1tQjEh-00056S-37 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:55 -0500 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3vxNtZwgKCtwUSF8MRQFEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--wuhaotsh.bounces.google.com>) id 1tQjEe-0001FI-MA for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:50 -0500 Received: by mail-pj1-x1049.google.com with SMTP id 98e67ed59e1d1-2ee46799961so11949647a91.2 for ; Thu, 26 Dec 2024 00:28:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201727; x=1735806527; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=PC3/TomEsHn2pxO3IjMB1Y1E4z7z2FDcg8knqGv0i/0=; b=VOfgcnOjZze51GhS7hIgEUkXPfPV5ayKIuoLrv19/nRTSwrU8rcgIrvj5rI7HkLu/s RZal8MBcXvtcF+c5az0JUe9SSDoB8AxwA5u62UGe1dsAytmPlec9NmezdAdvYuW0JYFe eFDwFXjUYWRHrNR8ATnYCk0KDl9Uar7Z0Y7BqH7TYHCktnttCZR94PZiUJqgetisTUxj /0Nac9++6wJSygPiC8RHqzjt5sSK2I7Lfw4XgS+QBf+QrdzG40bqQhdN251RHFAscD7c s9RbZt12cDp1Nr5/igsT51683iCQ7IsN8qG76BFUNaMAevJtpUrQSjNvDd1tFPkv5qEf 4eoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201727; x=1735806527; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=PC3/TomEsHn2pxO3IjMB1Y1E4z7z2FDcg8knqGv0i/0=; b=CdHc4NCdwwBqlrPpklPQ34lod3Et9FVdPJnv3wmNxJ/EvZXAuCdk71flGsMJwIq/A0 6g/+Xnx4aS6EGcWDn60QBthEcROmrV6LmZDFQkaSWE68llynG5GoNdYCJEV9xssAlcgD a2BQtYLNWIc9ddMEm9vH9hRi720WA5rqx8LUVPHjcT6/4U35Gf4qUqvgliRFtO3XTzlx N35+m+pvRpijMjQB55Ew/jfYj5d4bztTRHw7vjEZk0EZ2J7LSP449i4Bl3z+wmEemHb5 g9Rhl/0QSEY0Z42nvJYhHxbEM+DpbIe9nsGf1fIAyzN08OyAdTmPftxEb3Uism5XkNe6 1dtA== X-Forwarded-Encrypted: i=1; AJvYcCXVnRhK2+ubD9oCMjltjevHJ7VFTmn9FenNyzSGxJ/FcMecBG4XN3YrY2v7EURNKgQBkvBkUZSf0TyR@nongnu.org X-Gm-Message-State: AOJu0YxGf2YTmtaa6R+3Q/u3s2lXaTyzryIpWM4xWkvi5xZ+nAhk3UNE 7Ih03e+EjfhAjMJ91uPt1otOLRbxsWROJrttcY/hi6JO+1Gpv7FApwNTvlIRw8LtwAjcjRh5yZf y3FWpb3+TvA== X-Google-Smtp-Source: AGHT+IGXQRwpQT2cr8F+ALVdqYOzq3xJzzR3Ni7bhuyOvKSOWAKgpYdu4IpghlUWO7yGudjMt5MKjsAqAwpsrg== X-Received: from pjyd15.prod.google.com ([2002:a17:90a:dfcf:b0:2ea:46ed:5d3b]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1f83:b0:2ee:a744:a4fe with SMTP id 98e67ed59e1d1-2f452ee6dd2mr31125723a91.25.1735201727227; Thu, 26 Dec 2024 00:28:47 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:55 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-13-wuhaotsh@google.com> Subject: [PATCH v2 12/17] hw/misc: Move NPCM7XX CLK to NPCM CLK From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=3vxNtZwgKCtwUSF8MRQFEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201771969116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A lot of NPCM7XX and NPCM8XX CLK modules share the same code, this commit moves the NPCM7XX CLK to NPCM CLK for these properties. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm_clk.c | 106 +++++++++++++++++++++---------------- hw/misc/trace-events | 6 +-- include/hw/arm/npcm7xx.h | 2 +- include/hw/misc/npcm_clk.h | 22 ++++---- 4 files changed, 76 insertions(+), 60 deletions(-) diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index 2bcb731099..0ecf0df3bb 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -198,7 +198,7 @@ static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKR= egisters reg) } } =20 -static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) +static void npcm7xx_clk_update_all_plls(NPCMCLKState *clk) { int i; =20 @@ -207,7 +207,7 @@ static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState= *clk) } } =20 -static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) +static void npcm7xx_clk_update_all_sels(NPCMCLKState *clk) { int i; =20 @@ -216,7 +216,7 @@ static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState= *clk) } } =20 -static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) +static void npcm7xx_clk_update_all_dividers(NPCMCLKState *clk) { int i; =20 @@ -225,7 +225,7 @@ static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKS= tate *clk) } } =20 -static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) +static void npcm7xx_clk_update_all_clocks(NPCMCLKState *clk) { clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); npcm7xx_clk_update_all_plls(clk); @@ -635,7 +635,7 @@ static void npcm7xx_clk_divider_init(Object *obj) } =20 static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, - NPCM7xxCLKState *clk, const PLLInitInfo *init_info) + NPCMCLKState *clk, const PLLInitInfo *init_info) { pll->name =3D init_info->name; pll->clk =3D clk; @@ -647,7 +647,7 @@ static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState= *pll, } =20 static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, - NPCM7xxCLKState *clk, const SELInitInfo *init_info) + NPCMCLKState *clk, const SELInitInfo *init_info) { int input_size =3D init_info->input_size; =20 @@ -664,7 +664,7 @@ static void npcm7xx_init_clock_sel(NPCM7xxClockSELState= *sel, } =20 static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div, - NPCM7xxCLKState *clk, const DividerInitInfo *init_info) + NPCMCLKState *clk, const DividerInitInfo *init_info) { div->name =3D init_info->name; div->clk =3D clk; @@ -683,7 +683,7 @@ static void npcm7xx_init_clock_divider(NPCM7xxClockDivi= derState *div, } } =20 -static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, +static Clock *npcm7xx_get_clock(NPCMCLKState *clk, ClockSrcType type, int index) { switch (type) { @@ -700,7 +700,7 @@ static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, C= lockSrcType type, } } =20 -static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) +static void npcm7xx_connect_clocks(NPCMCLKState *clk) { int i, j; Clock *src; @@ -724,10 +724,10 @@ static void npcm7xx_connect_clocks(NPCM7xxCLKState *c= lk) } } =20 -static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned siz= e) +static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); - NPCM7xxCLKState *s =3D opaque; + NPCMCLKState *s =3D opaque; int64_t now_ns; uint32_t value =3D 0; =20 @@ -766,19 +766,19 @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr= offset, unsigned size) break; }; =20 - trace_npcm7xx_clk_read(offset, value); + trace_npcm_clk_read(offset, value); =20 return value; } =20 -static void npcm7xx_clk_write(void *opaque, hwaddr offset, +static void npcm_clk_write(void *opaque, hwaddr offset, uint64_t v, unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); - NPCM7xxCLKState *s =3D opaque; + NPCMCLKState *s =3D opaque; uint32_t value =3D v; =20 - trace_npcm7xx_clk_write(offset, value); + trace_npcm_clk_write(offset, value); =20 if (reg >=3D NPCM7XX_CLK_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -842,7 +842,7 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offs= et, static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n, int level) { - NPCM7xxCLKState *clk =3D NPCM7XX_CLK(opaque); + NPCMCLKState *clk =3D NPCM_CLK(opaque); uint32_t rcr; =20 g_assert(n >=3D 0 && n <=3D NPCM7XX_NR_WATCHDOGS); @@ -856,9 +856,9 @@ static void npcm7xx_clk_perform_watchdog_reset(void *op= aque, int n, } } =20 -static const struct MemoryRegionOps npcm7xx_clk_ops =3D { - .read =3D npcm7xx_clk_read, - .write =3D npcm7xx_clk_write, +static const struct MemoryRegionOps npcm_clk_ops =3D { + .read =3D npcm_clk_read, + .write =3D npcm_clk_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, @@ -867,9 +867,9 @@ static const struct MemoryRegionOps npcm7xx_clk_ops =3D= { }, }; =20 -static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) +static void npcm_clk_enter_reset(Object *obj, ResetType type) { - NPCM7xxCLKState *s =3D NPCM7XX_CLK(obj); + NPCMCLKState *s =3D NPCM_CLK(obj); =20 QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values)); =20 @@ -882,7 +882,7 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetT= ype type) */ } =20 -static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) +static void npcm7xx_clk_init_clock_hierarchy(NPCMCLKState *s) { int i; =20 @@ -918,19 +918,19 @@ static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxC= LKState *s) clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); } =20 -static void npcm7xx_clk_init(Object *obj) +static void npcm_clk_init(Object *obj) { - NPCM7xxCLKState *s =3D NPCM7XX_CLK(obj); + NPCMCLKState *s =3D NPCM_CLK(obj); =20 - memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, - TYPE_NPCM7XX_CLK, 4 * KiB); + memory_region_init_io(&s->iomem, obj, &npcm_clk_ops, s, + TYPE_NPCM_CLK, 4 * KiB); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); } =20 -static int npcm7xx_clk_post_load(void *opaque, int version_id) +static int npcm_clk_post_load(void *opaque, int version_id) { if (version_id >=3D 1) { - NPCM7xxCLKState *clk =3D opaque; + NPCMCLKState *clk =3D opaque; =20 npcm7xx_clk_update_all_clocks(clk); } @@ -938,10 +938,10 @@ static int npcm7xx_clk_post_load(void *opaque, int ve= rsion_id) return 0; } =20 -static void npcm7xx_clk_realize(DeviceState *dev, Error **errp) +static void npcm_clk_realize(DeviceState *dev, Error **errp) { int i; - NPCM7xxCLKState *s =3D NPCM7XX_CLK(dev); + NPCMCLKState *s =3D NPCM_CLK(dev); =20 qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); @@ -996,15 +996,15 @@ static const VMStateDescription vmstate_npcm7xx_clk_d= ivider =3D { }, }; =20 -static const VMStateDescription vmstate_npcm7xx_clk =3D { - .name =3D "npcm7xx-clk", - .version_id =3D 1, - .minimum_version_id =3D 1, - .post_load =3D npcm7xx_clk_post_load, +static const VMStateDescription vmstate_npcm_clk =3D { + .name =3D "npcm-clk", + .version_id =3D 2, + .minimum_version_id =3D 2, + .post_load =3D npcm_clk_post_load, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), - VMSTATE_INT64(ref_ns, NPCM7xxCLKState), - VMSTATE_CLOCK(clkref, NPCM7xxCLKState), + VMSTATE_UINT32_ARRAY(regs, NPCMCLKState, NPCM_CLK_MAX_NR_REGS), + VMSTATE_INT64(ref_ns, NPCMCLKState), + VMSTATE_CLOCK(clkref, NPCMCLKState), VMSTATE_END_OF_LIST(), }, }; @@ -1033,17 +1033,23 @@ static void npcm7xx_clk_divider_class_init(ObjectCl= ass *klass, void *data) dc->vmsd =3D &vmstate_npcm7xx_clk_divider; } =20 -static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) +static void npcm_clk_class_init(ObjectClass *klass, void *data) { ResettableClass *rc =3D RESETTABLE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS); + dc->vmsd =3D &vmstate_npcm_clk; + dc->realize =3D npcm_clk_realize; + rc->phases.enter =3D npcm_clk_enter_reset; +} + +static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS); + QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END !=3D NPCM7XX_CLK_NR_REGS); dc->desc =3D "NPCM7xx Clock Control Registers"; - dc->vmsd =3D &vmstate_npcm7xx_clk; - dc->realize =3D npcm7xx_clk_realize; - rc->phases.enter =3D npcm7xx_clk_enter_reset; } =20 static const TypeInfo npcm7xx_clk_pll_info =3D { @@ -1070,11 +1076,18 @@ static const TypeInfo npcm7xx_clk_divider_info =3D { .class_init =3D npcm7xx_clk_divider_class_init, }; =20 +static const TypeInfo npcm_clk_info =3D { + .name =3D TYPE_NPCM_CLK, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCMCLKState), + .instance_init =3D npcm_clk_init, + .class_init =3D npcm_clk_class_init, + .abstract =3D true, +}; + static const TypeInfo npcm7xx_clk_info =3D { .name =3D TYPE_NPCM7XX_CLK, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(NPCM7xxCLKState), - .instance_init =3D npcm7xx_clk_init, + .parent =3D TYPE_NPCM_CLK, .class_init =3D npcm7xx_clk_class_init, }; =20 @@ -1083,6 +1096,7 @@ static void npcm7xx_clk_register_type(void) type_register_static(&npcm7xx_clk_pll_info); type_register_static(&npcm7xx_clk_sel_info); type_register_static(&npcm7xx_clk_divider_info); + type_register_static(&npcm_clk_info); type_register_static(&npcm7xx_clk_info); } type_init(npcm7xx_clk_register_type); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 59c2d4ecc0..6b313e4f88 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -130,9 +130,9 @@ mos6522_set_sr_int(void) "set sr_int" mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=3D0x%"PR= Ix64 " [%s] val=3D0x%"PRIx64 mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=3D0x%"PRI= x64 " [%s] val=3D0x%x" =20 -# npcm7xx_clk.c -npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 -npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 = " value: 0x%08" PRIx32 +# npcm_clk.c +npcm_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx32 +npcm_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx32 =20 # npcm_gcr.c npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " v= alue: 0x%08" PRIx64 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index e80fd91f20..56536565b7 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -90,7 +90,7 @@ struct NPCM7xxState { MemoryRegion *dram; =20 NPCMGCRState gcr; - NPCM7xxCLKState clk; + NPCMCLKState clk; NPCM7xxTimerCtrlState tim[3]; NPCM7xxADCState adc; NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES]; diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index 0aef81e10c..db03b46a52 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -20,11 +20,12 @@ #include "hw/clock.h" #include "hw/sysbus.h" =20 +#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) /* - * Number of registers in our device state structure. Don't change this wi= thout - * incrementing the version_id in the vmstate. + * Number of maximum registers in NPCM device state structure. Don't change + * this without incrementing the version_id in the vmstate. */ -#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) +#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS =20 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" =20 @@ -80,7 +81,7 @@ typedef enum NPCM7xxClockDivider { NPCM7XX_CLOCK_NR_DIVIDERS, } NPCM7xxClockConverter; =20 -typedef struct NPCM7xxCLKState NPCM7xxCLKState; +typedef struct NPCMCLKState NPCMCLKState; =20 /** * struct NPCM7xxClockPLLState - A PLL module in CLK module. @@ -94,7 +95,7 @@ typedef struct NPCM7xxClockPLLState { DeviceState parent; =20 const char *name; - NPCM7xxCLKState *clk; + NPCMCLKState *clk; Clock *clock_in; Clock *clock_out; =20 @@ -115,7 +116,7 @@ typedef struct NPCM7xxClockSELState { DeviceState parent; =20 const char *name; - NPCM7xxCLKState *clk; + NPCMCLKState *clk; uint8_t input_size; Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT]; Clock *clock_out; @@ -140,7 +141,7 @@ typedef struct NPCM7xxClockDividerState { DeviceState parent; =20 const char *name; - NPCM7xxCLKState *clk; + NPCMCLKState *clk; Clock *clock_in; Clock *clock_out; =20 @@ -155,7 +156,7 @@ typedef struct NPCM7xxClockDividerState { }; } NPCM7xxClockDividerState; =20 -struct NPCM7xxCLKState { +struct NPCMCLKState { SysBusDevice parent; =20 MemoryRegion iomem; @@ -165,7 +166,7 @@ struct NPCM7xxCLKState { NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; =20 - uint32_t regs[NPCM7XX_CLK_NR_REGS]; + uint32_t regs[NPCM_CLK_MAX_NR_REGS]; =20 /* Time reference for SECCNT and CNTR25M, initialized by power on rese= t */ int64_t ref_ns; @@ -174,7 +175,8 @@ struct NPCM7xxCLKState { Clock *clkref; }; =20 +#define TYPE_NPCM_CLK "npcm-clk" +OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" -OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK) =20 #endif /* NPCM_CLK_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201815; cv=none; d=zohomail.com; s=zohoarc; b=WaMQvEnHGGnTlvivoVeNl5JMVhX72Q2ILhCNqy6vcnr1MVOKqhtsZa1IbYI3MxXN5dUS+cX3WxRTP/jlfxwGosnzehVQVkXYyqXFIWkRLkDdsDvD6SV1yuSyCvK7zMNtrC0CVyEpmZt/IOihcf05hReeWcPZXLhdSa+qO+PtjoQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201815; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mSqBtRF4XTytwLiQf1Tk6i2T92wgV1efOniSzvWdnQk=; b=gapmbLGgiIn1jlEoXP2RSje6JeV+Mun1ya4Y/juupwT5qjR24ZY/WXoN7mfhUtE/CjGcIEt8UUvyU3l3ii/9noTCwFQe9QHVOAvwtuAv4ndBVo60n1CbxLzZwMpOEqKyqSDbCq6x6FVr86OBBqUwyxwggacMZ6I/xIk+IwGaO0o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201815055659.7797130325831; Thu, 26 Dec 2024 00:30:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEw-0005dL-9h; Thu, 26 Dec 2024 03:29:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3whNtZwgKCt8XVIBPUTIHPPHMF.DPNRFNV-EFWFMOPOHOV.PSH@flex--wuhaotsh.bounces.google.com>) id 1tQjEl-00058V-Gz for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:57 -0500 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3whNtZwgKCt8XVIBPUTIHPPHMF.DPNRFNV-EFWFMOPOHOV.PSH@flex--wuhaotsh.bounces.google.com>) id 1tQjEi-0001G3-GN for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:55 -0500 Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-2164861e1feso77081185ad.1 for ; Thu, 26 Dec 2024 00:28:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201730; x=1735806530; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=mSqBtRF4XTytwLiQf1Tk6i2T92wgV1efOniSzvWdnQk=; b=yZf0TG4VnbBeVUXFjLUkN+2beiMGBtS5SwUd5bgGQ9uvoFltvVJWw25XHMaFLqqBUG rsi0jebXNxD0hywPMT00sBHbeyXSTR5aHiUlmS6AIoypnfZhdJLk008C0n9DKSEQYyha PdrIN1hNJ40eIdCte0pU/UbvLvJGBvl2vMZYBJaOBo06la8WMqKgg8jOARHSI5GKxde5 swXUCOqhX7VO8O8EjFxmNXcnhCC4Xk6NGl9nZG/6BRF7pePqAQZM5Ku9dhgW/rPyUmMq v3djS47B8ZnWj97FpQdR5bMhswi8HHbc70UIsSf/Y0FpCi7+rGWIUoJfS5HbIEXdYf9p pxww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201730; x=1735806530; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=mSqBtRF4XTytwLiQf1Tk6i2T92wgV1efOniSzvWdnQk=; b=IkyLciJ5zNS7Kd2KnqoAyJBDDo5sfBsxzCv6VesMSXsIzweJXRnIEc/2x0p/c6WXWj WovOwsaQfgtfy0IL/nEHEJ+fJg4X94M/xS5+X7LoS0f9KgYC97eIoC72UGs+5nCIRJDC vFUfqMZrOS4croopqQNNjtMyu6OV0/F6NIp7J4lYUICGd5Mkck4dkZWq1rzzpI8uBKVq anhoirYRnMTaUQ9YSb8vzSfid7dN6ND0Dtxa45v04SkcOXBRFFcxD3pcllsd5Rto59oc k9673BTlX3drSi0wq2MBYF9MdNRkgq5xguVYBjrXJyLMVeZNIk0amNDmXG5IFeYDNG9N 761w== X-Forwarded-Encrypted: i=1; AJvYcCU59vA1pIazLvR0FUHNSlizFwMrugXj7kw6QWPn202fYQakGDLkFEPWyPKS+ncq5RmSvi8ZbZY1Ehlf@nongnu.org X-Gm-Message-State: AOJu0YytfQi6Y0t/7Ao3/oPQ+oKUJS0MTh/14SqPUoe9jmCFG4qh8wPD NSskPiPbjkELHOkoibtbqexdv0rY3ioyhcHAuOmHvNavvj6k5EdmNR1ZwyuLn8S4WTfKsm5LmJR gOp8emxj4gQ== X-Google-Smtp-Source: AGHT+IGBKuOlvVH53OUIZXB7n3c1T6FqaikM1XlT9ngzjs87MdN8xjYC8TFtzsDOsB8ylBrrqjQz7v71tu6Fvg== X-Received: from pgtq9.prod.google.com ([2002:a65:6849:0:b0:845:b983:9e34]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:946:b0:216:3e9a:89e with SMTP id d9443c01a7336-219e6f2e9dfmr352474315ad.35.1735201730595; Thu, 26 Dec 2024 00:28:50 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:56 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-14-wuhaotsh@google.com> Subject: [PATCH v2 13/17] hw/misc: Add nr_regs and cold_reset_values to NPCM CLK From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3whNtZwgKCt8XVIBPUTIHPPHMF.DPNRFNV-EFWFMOPOHOV.PSH@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201815964116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These 2 values are different between NPCM7XX and NPCM8XX CLKs. So we add them to the class and assign different values to them. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/misc/npcm_clk.c | 17 +++++++++++------ include/hw/misc/npcm_clk.h | 9 ++++++++- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index 0ecf0df3bb..eee754d31f 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -81,7 +81,7 @@ enum NPCM7xxCLKRegisters { * All are loaded on power-up reset. CLKENx and SWRSTR should also be load= ed on * core domain reset, but this reset type is not yet supported by QEMU. */ -static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] =3D { +static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_CLK_NR_REGS] =3D { [NPCM7XX_CLK_CLKEN1] =3D 0xffffffff, [NPCM7XX_CLK_CLKSEL] =3D 0x004aaaaa, [NPCM7XX_CLK_CLKDIV1] =3D 0x5413f855, @@ -728,10 +728,11 @@ static uint64_t npcm_clk_read(void *opaque, hwaddr of= fset, unsigned size) { uint32_t reg =3D offset / sizeof(uint32_t); NPCMCLKState *s =3D opaque; + NPCMCLKClass *c =3D NPCM_CLK_GET_CLASS(s); int64_t now_ns; uint32_t value =3D 0; =20 - if (reg >=3D NPCM7XX_CLK_NR_REGS) { + if (reg >=3D c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -776,11 +777,12 @@ static void npcm_clk_write(void *opaque, hwaddr offse= t, { uint32_t reg =3D offset / sizeof(uint32_t); NPCMCLKState *s =3D opaque; + NPCMCLKClass *c =3D NPCM_CLK_GET_CLASS(s); uint32_t value =3D v; =20 trace_npcm_clk_write(offset, value); =20 - if (reg >=3D NPCM7XX_CLK_NR_REGS) { + if (reg >=3D c->nr_regs) { qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04" HWADDR_PRIx " out of range\n", __func__, offset); @@ -870,10 +872,9 @@ static const struct MemoryRegionOps npcm_clk_ops =3D { static void npcm_clk_enter_reset(Object *obj, ResetType type) { NPCMCLKState *s =3D NPCM_CLK(obj); + NPCMCLKClass *c =3D NPCM_CLK_GET_CLASS(s); =20 - QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values)); - - memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); + memcpy(s->regs, c->cold_reset_values, sizeof(s->regs)); s->ref_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); npcm7xx_clk_update_all_clocks(s); /* @@ -1045,11 +1046,14 @@ static void npcm_clk_class_init(ObjectClass *klass,= void *data) =20 static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) { + NPCMCLKClass *c =3D NPCM_CLK_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS); QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END !=3D NPCM7XX_CLK_NR_REGS); dc->desc =3D "NPCM7xx Clock Control Registers"; + c->nr_regs =3D NPCM7XX_CLK_NR_REGS; + c->cold_reset_values =3D npcm7xx_cold_reset_values; } =20 static const TypeInfo npcm7xx_clk_pll_info =3D { @@ -1081,6 +1085,7 @@ static const TypeInfo npcm_clk_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(NPCMCLKState), .instance_init =3D npcm_clk_init, + .class_size =3D sizeof(NPCMCLKClass), .class_init =3D npcm_clk_class_init, .abstract =3D true, }; diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index db03b46a52..f47614ac8d 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -175,8 +175,15 @@ struct NPCMCLKState { Clock *clkref; }; =20 +typedef struct NPCMCLKClass { + SysBusDeviceClass parent; + + size_t nr_regs; + const uint32_t *cold_reset_values; +} NPCMCLKClass; + #define TYPE_NPCM_CLK "npcm-clk" -OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK) +OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" =20 #endif /* NPCM_CLK_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201771; cv=none; d=zohomail.com; s=zohoarc; b=B3/5a6wuDtVYncojwhLKYK6rd1+JgVJYTwU1zaUt+54F3fIStZSwuQfhDgBeE8sl9Nwp25YcuW8NugFm01xQbt+3O+itRrI0eR/nkD9Vs1IXNpthmfcGT/OlYgzJrIlK0sHz+7lfteipy1SKBKswkCvhhJ9Udk0v275WIO7AWkw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201771; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=y7VgKIyKOGLTsJ2xUWEPCl+kAMd8H5DMHmwH0IVzMCc=; b=dnlK1H47SzJf0qq6+XTUaLL542tc5sTquG5knXloy54NLpW+nbT1O/cQK4St9+MVmOT7MniTjrFfWzzCqb28DoYp5kMLdhxOyi3uvCMs7oel+qbhwHUBclP/a0zcKpKnHVGBpMxkmU/EJo7duByUBcGIPH4YZ13Ixpy48MOMuBQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201771232164.1503833621166; Thu, 26 Dec 2024 00:29:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjEz-00062w-JC; Thu, 26 Dec 2024 03:29:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3xhNtZwgKCuMbZMFTYXMLTTLQJ.HTRVJRZ-IJaJQSTSLSZ.TWL@flex--wuhaotsh.bounces.google.com>) id 1tQjEn-0005Cf-Gr for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:59 -0500 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3xhNtZwgKCuMbZMFTYXMLTTLQJ.HTRVJRZ-IJaJQSTSLSZ.TWL@flex--wuhaotsh.bounces.google.com>) id 1tQjEl-0001GU-Ma for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:28:57 -0500 Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-21661949f23so124323785ad.3 for ; Thu, 26 Dec 2024 00:28:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201734; x=1735806534; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=y7VgKIyKOGLTsJ2xUWEPCl+kAMd8H5DMHmwH0IVzMCc=; b=FvDTnYxv2bvICZTqZkZZ4TvTg2YW6waYcVM5apZ+ArwbMVU3moN6hbB9b6cR/FSSYZ g4owN0gGp/zbt47/AjUSE+4+B2M7M02If6kEXZ1B8nrZnzJk/nryyodcTBdVQGYETDa6 qmKuSEe/ZkwTB6ZcBmqcD+CZJ3ARxBflgi4/zLg286yK4QN5KcDd7zimZFXvBjE8dqMk b9lQ8pLldTmT3MESmMzLf3sDYgytGC0wQ8GOjUPiUD25i5U8yyU7OBcaibNB/enKXQzu REv/SyEaiGCp0hvEFvlgBID9LtzvPCoriJSbuCi2RUt4tkqvLdcnT3A+AcOSL9mT44As vwTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201734; x=1735806534; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=y7VgKIyKOGLTsJ2xUWEPCl+kAMd8H5DMHmwH0IVzMCc=; b=X2zKsTqD907xqLX58UZrNO8cQYRjZzpo5DihPCTcX+e7bG7DMf4pipb3gceqwZIBDD lyDO8jFKS4c+AzKV6jUZ3cAxbB4Amt1TBA3mt3XAuY4ovZ+oBYWGEzzq29Dozh2tgqvs LzGcpvQ/+PuBd5bpVM/xN0enwWTNaIcdbqnYqofF6jF9/RcybMFe7lx4Nk3/giS61QB8 5y11mvHtonsAJeoGOXkd0gUNi4GF3Hv44rMwdY6t5CVhg+vMG3eM9coAAXAfMV8nYjmf xVHBevGblg97keS4CnN+6cca9ajPwiGcosGO+mBA6y1qlRxizKHCY6v/mk9ABBoHjYOC GW7A== X-Forwarded-Encrypted: i=1; AJvYcCViYC2w/tvwcCUNOUhpnPr3ulPg4F1HslXyxKDSVbJqfBrHF4PU25epJbp0sQcNfdAtW+XlNi+BJykw@nongnu.org X-Gm-Message-State: AOJu0Yw+ZyhErbSx251U+t2HyvKTT7z3Vs5HI5kSHELG5x99T7hoSygm RqTcpSi+O2uIvvOUarRYddEyqyN2aeWuHnJz2wYyPJBjP0P4fmWpesM0URRFFSm1tmah4om3Eco 0XWxPHx2z9g== X-Google-Smtp-Source: AGHT+IGaeKSwQy0pnDKEQtQKa8UNpnp8mkkRfhIcEAZEU5Q4wJ35ZCbC7IH+6A4TVqFoItIsb+Tsl48MF4wtNQ== X-Received: from pgmo10.prod.google.com ([2002:a63:5d4a:0:b0:8ae:4cf4:372]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:244a:b0:1db:ff76:99d7 with SMTP id adf61e73a8af0-1e5e07ef1afmr43615669637.35.1735201734092; Thu, 26 Dec 2024 00:28:54 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:57 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-15-wuhaotsh@google.com> Subject: [PATCH v2 14/17] hw/misc: Support NPCM8XX CLK Module Registers From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3xhNtZwgKCuMbZMFTYXMLTTLQJ.HTRVJRZ-IJaJQSTSLSZ.TWL@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201771871116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NPCM8XX adds a few new registers and have a different set of reset values to the CLK modules. This patch supports them. This patch doesn't support the new clock values generated by these registers. Currently no modules use these new clock values so they are not necessary at this point. Implementation of these clocks might be required when implementing these modules. Signed-off-by: Hao Wu Reviewed-by: Titus Rwantare Reviewed-by: Peter Maydell --- hw/misc/npcm_clk.c | 113 ++++++++++++++++++++++++++++++++++++- include/hw/misc/npcm_clk.h | 10 +++- 2 files changed, 120 insertions(+), 3 deletions(-) diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c index eee754d31f..af127991da 100644 --- a/hw/misc/npcm_clk.c +++ b/hw/misc/npcm_clk.c @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx Clock Control Registers. + * Nuvoton NPCM7xx/8xx Clock Control Registers. * * Copyright 2020 Google LLC * @@ -75,6 +75,58 @@ enum NPCM7xxCLKRegisters { NPCM7XX_CLK_REGS_END, }; =20 +enum NPCM8xxCLKRegisters { + NPCM8XX_CLK_CLKEN1, + NPCM8XX_CLK_CLKSEL, + NPCM8XX_CLK_CLKDIV1, + NPCM8XX_CLK_PLLCON0, + NPCM8XX_CLK_PLLCON1, + NPCM8XX_CLK_SWRSTR, + NPCM8XX_CLK_IPSRST1 =3D 0x20 / sizeof(uint32_t), + NPCM8XX_CLK_IPSRST2, + NPCM8XX_CLK_CLKEN2, + NPCM8XX_CLK_CLKDIV2, + NPCM8XX_CLK_CLKEN3, + NPCM8XX_CLK_IPSRST3, + NPCM8XX_CLK_WD0RCR, + NPCM8XX_CLK_WD1RCR, + NPCM8XX_CLK_WD2RCR, + NPCM8XX_CLK_SWRSTC1, + NPCM8XX_CLK_SWRSTC2, + NPCM8XX_CLK_SWRSTC3, + NPCM8XX_CLK_TIPRSTC, + NPCM8XX_CLK_PLLCON2, + NPCM8XX_CLK_CLKDIV3, + NPCM8XX_CLK_CORSTC, + NPCM8XX_CLK_PLLCONG, + NPCM8XX_CLK_AHBCKFI, + NPCM8XX_CLK_SECCNT, + NPCM8XX_CLK_CNTR25M, + /* Registers unique to NPCM8XX SoC */ + NPCM8XX_CLK_CLKEN4, + NPCM8XX_CLK_IPSRST4, + NPCM8XX_CLK_BUSTO, + NPCM8XX_CLK_CLKDIV4, + NPCM8XX_CLK_WD0RCRB, + NPCM8XX_CLK_WD1RCRB, + NPCM8XX_CLK_WD2RCRB, + NPCM8XX_CLK_SWRSTC1B, + NPCM8XX_CLK_SWRSTC2B, + NPCM8XX_CLK_SWRSTC3B, + NPCM8XX_CLK_TIPRSTCB, + NPCM8XX_CLK_CORSTCB, + NPCM8XX_CLK_IPSRSTDIS1, + NPCM8XX_CLK_IPSRSTDIS2, + NPCM8XX_CLK_IPSRSTDIS3, + NPCM8XX_CLK_IPSRSTDIS4, + NPCM8XX_CLK_CLKENDIS1, + NPCM8XX_CLK_CLKENDIS2, + NPCM8XX_CLK_CLKENDIS3, + NPCM8XX_CLK_CLKENDIS4, + NPCM8XX_CLK_THRTL_CNT, + NPCM8XX_CLK_REGS_END, +}; + /* * These reset values were taken from version 0.91 of the NPCM750R data sh= eet. * @@ -103,6 +155,46 @@ static const uint32_t npcm7xx_cold_reset_values[NPCM7X= X_CLK_NR_REGS] =3D { [NPCM7XX_CLK_AHBCKFI] =3D 0x000000c8, }; =20 +/* + * These reset values were taken from version 0.92 of the NPCM8xx data she= et. + */ +static const uint32_t npcm8xx_cold_reset_values[NPCM8XX_CLK_NR_REGS] =3D { + [NPCM8XX_CLK_CLKEN1] =3D 0xffffffff, + [NPCM8XX_CLK_CLKSEL] =3D 0x154aaaaa, + [NPCM8XX_CLK_CLKDIV1] =3D 0x5413f855, + [NPCM8XX_CLK_PLLCON0] =3D 0x00222101 | PLLCON_LOKI, + [NPCM8XX_CLK_PLLCON1] =3D 0x00202101 | PLLCON_LOKI, + [NPCM8XX_CLK_IPSRST1] =3D 0x00001000, + [NPCM8XX_CLK_IPSRST2] =3D 0x80000000, + [NPCM8XX_CLK_CLKEN2] =3D 0xffffffff, + [NPCM8XX_CLK_CLKDIV2] =3D 0xaa4f8f9f, + [NPCM8XX_CLK_CLKEN3] =3D 0xffffffff, + [NPCM8XX_CLK_IPSRST3] =3D 0x03000000, + [NPCM8XX_CLK_WD0RCR] =3D 0xffffffff, + [NPCM8XX_CLK_WD1RCR] =3D 0xffffffff, + [NPCM8XX_CLK_WD2RCR] =3D 0xffffffff, + [NPCM8XX_CLK_SWRSTC1] =3D 0x00000003, + [NPCM8XX_CLK_SWRSTC2] =3D 0x00000001, + [NPCM8XX_CLK_SWRSTC3] =3D 0x00000001, + [NPCM8XX_CLK_TIPRSTC] =3D 0x00000001, + [NPCM8XX_CLK_PLLCON2] =3D 0x00c02105 | PLLCON_LOKI, + [NPCM8XX_CLK_CLKDIV3] =3D 0x00009100, + [NPCM8XX_CLK_CORSTC] =3D 0x04000003, + [NPCM8XX_CLK_PLLCONG] =3D 0x01228606 | PLLCON_LOKI, + [NPCM8XX_CLK_AHBCKFI] =3D 0x000000c8, + [NPCM8XX_CLK_CLKEN4] =3D 0xffffffff, + [NPCM8XX_CLK_CLKDIV4] =3D 0x70009000, + [NPCM8XX_CLK_IPSRST4] =3D 0x02000000, + [NPCM8XX_CLK_WD0RCRB] =3D 0xfffffe71, + [NPCM8XX_CLK_WD1RCRB] =3D 0xfffffe71, + [NPCM8XX_CLK_WD2RCRB] =3D 0xfffffe71, + [NPCM8XX_CLK_SWRSTC1B] =3D 0xfffffe71, + [NPCM8XX_CLK_SWRSTC2B] =3D 0xfffffe71, + [NPCM8XX_CLK_SWRSTC3B] =3D 0xfffffe71, + [NPCM8XX_CLK_TIPRSTCB] =3D 0xfffffe71, + [NPCM8XX_CLK_CORSTCB] =3D 0xfffffe71, +}; + /* The number of watchdogs that can trigger a reset. */ #define NPCM7XX_NR_WATCHDOGS (3) =20 @@ -1056,6 +1148,18 @@ static void npcm7xx_clk_class_init(ObjectClass *klas= s, void *data) c->cold_reset_values =3D npcm7xx_cold_reset_values; } =20 +static void npcm8xx_clk_class_init(ObjectClass *klass, void *data) +{ + NPCMCLKClass *c =3D NPCM_CLK_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + QEMU_BUILD_BUG_ON(NPCM8XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS); + QEMU_BUILD_BUG_ON(NPCM8XX_CLK_REGS_END !=3D NPCM8XX_CLK_NR_REGS); + dc->desc =3D "NPCM8xx Clock Control Registers"; + c->nr_regs =3D NPCM8XX_CLK_NR_REGS; + c->cold_reset_values =3D npcm8xx_cold_reset_values; +} + static const TypeInfo npcm7xx_clk_pll_info =3D { .name =3D TYPE_NPCM7XX_CLOCK_PLL, .parent =3D TYPE_DEVICE, @@ -1096,6 +1200,12 @@ static const TypeInfo npcm7xx_clk_info =3D { .class_init =3D npcm7xx_clk_class_init, }; =20 +static const TypeInfo npcm8xx_clk_info =3D { + .name =3D TYPE_NPCM8XX_CLK, + .parent =3D TYPE_NPCM_CLK, + .class_init =3D npcm8xx_clk_class_init, +}; + static void npcm7xx_clk_register_type(void) { type_register_static(&npcm7xx_clk_pll_info); @@ -1103,5 +1213,6 @@ static void npcm7xx_clk_register_type(void) type_register_static(&npcm7xx_clk_divider_info); type_register_static(&npcm_clk_info); type_register_static(&npcm7xx_clk_info); + type_register_static(&npcm8xx_clk_info); } type_init(npcm7xx_clk_register_type); diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index f47614ac8d..8fa1e14bdd 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx Clock Control Registers. + * Nuvoton NPCM7xx/8xx Clock Control Registers. * * Copyright 2020 Google LLC * @@ -21,11 +21,12 @@ #include "hw/sysbus.h" =20 #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) +#define NPCM8XX_CLK_NR_REGS (0xc4 / sizeof(uint32_t)) /* * Number of maximum registers in NPCM device state structure. Don't change * this without incrementing the version_id in the vmstate. */ -#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS +#define NPCM_CLK_MAX_NR_REGS NPCM8XX_CLK_NR_REGS =20 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" =20 @@ -162,6 +163,10 @@ struct NPCMCLKState { MemoryRegion iomem; =20 /* Clock converters */ + /* + * TODO: Implement unique clock converters for NPCM8xx. + * NPCM8xx adds a few more clock outputs. + */ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; @@ -185,5 +190,6 @@ typedef struct NPCMCLKClass { #define TYPE_NPCM_CLK "npcm-clk" OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" +#define TYPE_NPCM8XX_CLK "npcm8xx-clk" =20 #endif /* NPCM_CLK_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201810; cv=none; d=zohomail.com; s=zohoarc; b=CdyUp3a8JSpFeANWow2XHDFMZI6nPNcgjMFN7dICntkU+NzieFJ5tm0DV4dw4COkmcw9x3z1XLu0ZY9GTsREustIMOyZVOHZOCtGMmw1SAre4myRB+UEV/v9ok1aeUJrKOSIJ25RJGvxDzQugTVU4hqnI6fM3m9+I/PxGr3LoN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201810; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WL52ZJhsXVMfMJTd8y7V9jOMfJ6nGK09GJHBtbLvgJY=; b=aDF2/x5yg6vr4tHjl23dIpRIrEN9yD/gFH4Da5+wLiz7X3qom++COXrYjL8J+Gz7ZYSiAO/+oA98AzgKwi84ko86jm+HeRUmq7vzVuof5CZtWfxbEDP6uVAL+b6pb3EiqqTKoytySzayT8f7WCbXfRkjLfzImcYhrqpoYCn6754= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201810558997.4596040562891; Thu, 26 Dec 2024 00:30:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjF1-0006NU-N5; Thu, 26 Dec 2024 03:29:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3yRNtZwgKCuYecPIWbaPOWWOTM.KWUYMUc-LMdMTVWVOVc.WZO@flex--wuhaotsh.bounces.google.com>) id 1tQjEr-0005If-T9 for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:29:03 -0500 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3yRNtZwgKCuYecPIWbaPOWWOTM.KWUYMUc-LMdMTVWVOVc.WZO@flex--wuhaotsh.bounces.google.com>) id 1tQjEp-0001H1-5j for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:29:01 -0500 Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-2ef9e38b0cfso7501447a91.0 for ; Thu, 26 Dec 2024 00:28:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201738; x=1735806538; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=WL52ZJhsXVMfMJTd8y7V9jOMfJ6nGK09GJHBtbLvgJY=; b=gNO3UXoDLZnUOHZJp4fgw8DOEsJqfLY8vt6BU1mLkgt+vQmsXD8uP+4+1pj07s+vaV YkD5QgCsqgmRj+GsuFJcQAo1+Nt3v71Mc2R8G7IFohR2wEpBKC3g9Ej6H4xYIdp65BZ7 IRmEmyW6u2L7U3IvHLvEWGf+Z8Uuec4nnz/K2z6UCmkiQCZnL6M+4bg6j6r25cfaAp2w 8zyWav8IaLwdduDyfpApFqpb1VJ7mG0st9Gd4Gv5JF/jTWsLrnBBmKiS/hcZZnH1HxxF y1lSwn3yOu4Kz0CBTard4PLf9s4rC3f3NDETW1ehIz7GtSMzq+lTeMD6hTYO4KvYGWjJ 1g8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201738; x=1735806538; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WL52ZJhsXVMfMJTd8y7V9jOMfJ6nGK09GJHBtbLvgJY=; b=APVFev254uZbq6F1tj/ca3T4P03Uk2VrtsUkcUjsYxMzEc4yW4vA6CIz/4t4Dj8W1k 0acqty7JptfoV+zjfO6QGm5RIumZBLNn1UfQo/s5CMo9Kf467ghfGfgG2ql6qR4yp7hC N1Yqmm3WG5N2RAQBH9w4N0MTRBM9ynHDlGxRkqIpr9AwniiRury4acq4dzEQTAlHiAUn 3cQk8/61JHCyz+HeTP9Yj3qaMZh6fdgkFKrKMwk+QosTl1nJxPBow10t8cNeXLAH+ygN T2XQz4hxtVrR//MXQOtESm2d6ZKsgymjhwwI0pWnpJ2xMGqfsgmGK8HKI/BtWdycbYIf L3VA== X-Forwarded-Encrypted: i=1; AJvYcCX+lYNe4bs+PNwxSF5ovFWkBEJSy+2JkFmLK5yUPnNhEYbsqFWjbtXuYAeTJthl7Dbojmyamm6BCVJW@nongnu.org X-Gm-Message-State: AOJu0YwXiqJ1dnqt1r2M+BonKlvyKQMs+10XK665Rb9leYDvF2UuuHx9 uf54kIDvXaAWEywN0Qgz4fpV3fFf4BeJiD1X3NNkRSnCSLkMdxAC7bQspEGJvtCmqXSMR0fx02k 24e8Tj4V0hQ== X-Google-Smtp-Source: AGHT+IEZjtSGNbf/AspWTJvFApdp4Mnh5ZPZgIdTEguudaKXsG3hXnfupZQtxunOhZ6xtlWWqktRFU5pz5JmFg== X-Received: from pgex6.prod.google.com ([2002:a63:b206:0:b0:7fd:4f51:62c6]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:3181:b0:1d9:78c:dcf2 with SMTP id adf61e73a8af0-1e5e082e7abmr32626053637.43.1735201737802; Thu, 26 Dec 2024 00:28:57 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:58 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-16-wuhaotsh@google.com> Subject: [PATCH v2 15/17] hw/net: Add NPCM8XX PCS Module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::104a; envelope-from=3yRNtZwgKCuYecPIWbaPOWWOTM.KWUYMUc-LMdMTVWVOVc.WZO@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x104a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201812244116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII PHY. This implementation contains all the default registers and the soft reset feature that are required to load the Linux kernel driver. Further features have not been implemented yet. Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/net/meson.build | 1 + hw/net/npcm_pcs.c | 410 ++++++++++++++++++++++++++++++++++++++ hw/net/trace-events | 4 +- include/hw/net/npcm_pcs.h | 42 ++++ 4 files changed, 455 insertions(+), 2 deletions(-) create mode 100644 hw/net/npcm_pcs.c create mode 100644 include/hw/net/npcm_pcs.h diff --git a/hw/net/meson.build b/hw/net/meson.build index 3bb5d749a8..e6759e26ca 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -40,6 +40,7 @@ system_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunh= me.c')) system_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c')) system_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c')) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c', 'npc= m_gmac.c')) +system_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm_pcs.c')) =20 system_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_llan.c')) diff --git a/hw/net/npcm_pcs.c b/hw/net/npcm_pcs.c new file mode 100644 index 0000000000..ce5034e234 --- /dev/null +++ b/hw/net/npcm_pcs.c @@ -0,0 +1,410 @@ +/* + * Nuvoton NPCM8xx PCS Module + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +/* + * Disclaimer: + * Currently we only implemented the default values of the registers and + * the soft reset feature. These are required to boot up the GMAC module + * in Linux kernel for NPCM845 boards. Other functionalities are not model= ed. + */ + +#include "qemu/osdep.h" + +#include "exec/hwaddr.h" +#include "hw/registerfields.h" +#include "hw/net/npcm_pcs.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/units.h" +#include "trace.h" + +#define NPCM_PCS_IND_AC_BA 0x1fe +#define NPCM_PCS_IND_SR_CTL 0x1e00 +#define NPCM_PCS_IND_SR_MII 0x1f00 +#define NPCM_PCS_IND_SR_TIM 0x1f07 +#define NPCM_PCS_IND_VR_MII 0x1f80 + +REG16(NPCM_PCS_SR_CTL_ID1, 0x08) +REG16(NPCM_PCS_SR_CTL_ID2, 0x0a) +REG16(NPCM_PCS_SR_CTL_STS, 0x10) + +REG16(NPCM_PCS_SR_MII_CTRL, 0x00) +REG16(NPCM_PCS_SR_MII_STS, 0x02) +REG16(NPCM_PCS_SR_MII_DEV_ID1, 0x04) +REG16(NPCM_PCS_SR_MII_DEV_ID2, 0x06) +REG16(NPCM_PCS_SR_MII_AN_ADV, 0x08) +REG16(NPCM_PCS_SR_MII_LP_BABL, 0x0a) +REG16(NPCM_PCS_SR_MII_AN_EXPN, 0x0c) +REG16(NPCM_PCS_SR_MII_EXT_STS, 0x1e) + +REG16(NPCM_PCS_SR_TIM_SYNC_ABL, 0x10) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x12) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0x14) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x16) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0x18) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x1a) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0x1c) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x1e) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0x20) + +REG16(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x000) +REG16(NPCM_PCS_VR_MII_AN_CTRL, 0x002) +REG16(NPCM_PCS_VR_MII_AN_INTR_STS, 0x004) +REG16(NPCM_PCS_VR_MII_TC, 0x006) +REG16(NPCM_PCS_VR_MII_DBG_CTRL, 0x00a) +REG16(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x00c) +REG16(NPCM_PCS_VR_MII_EEE_TXTIMER, 0x010) +REG16(NPCM_PCS_VR_MII_EEE_RXTIMER, 0x012) +REG16(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0x014) +REG16(NPCM_PCS_VR_MII_EEE_MCTRL1, 0x016) +REG16(NPCM_PCS_VR_MII_DIG_STS, 0x020) +REG16(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0x022) +REG16(NPCM_PCS_VR_MII_MISC_STS, 0x030) +REG16(NPCM_PCS_VR_MII_RX_LSTS, 0x040) +REG16(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x070) +REG16(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x074) +REG16(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x07a) +REG16(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0x07c) +REG16(NPCM_PCS_VR_MII_MP_TX_STS, 0x090) +REG16(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0b0) +REG16(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x0b2) +REG16(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x0ba) +REG16(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0f0) +REG16(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0f2) +REG16(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x110) +REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0x126) +REG16(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x130) +REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0x132) +REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0x134) +REG16(NPCM_PCS_VR_MII_DIG_CTRL2, 0x1c2) +REG16(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0x1c4) + +/* Register Fields */ +#define NPCM_PCS_SR_MII_CTRL_RST BIT(15) + +static const uint16_t npcm_pcs_sr_ctl_cold_reset_values[NPCM_PCS_NR_SR_CTL= S] =3D { + [R_NPCM_PCS_SR_CTL_ID1] =3D 0x699e, + [R_NPCM_PCS_SR_CTL_STS] =3D 0x8000, +}; + +static const uint16_t npcm_pcs_sr_mii_cold_reset_values[NPCM_PCS_NR_SR_MII= S] =3D { + [R_NPCM_PCS_SR_MII_CTRL] =3D 0x1140, + [R_NPCM_PCS_SR_MII_STS] =3D 0x0109, + [R_NPCM_PCS_SR_MII_DEV_ID1] =3D 0x699e, + [R_NPCM_PCS_SR_MII_DEV_ID2] =3D 0xced0, + [R_NPCM_PCS_SR_MII_AN_ADV] =3D 0x0020, + [R_NPCM_PCS_SR_MII_EXT_STS] =3D 0xc000, +}; + +static const uint16_t npcm_pcs_sr_tim_cold_reset_values[NPCM_PCS_NR_SR_TIM= S] =3D { + [R_NPCM_PCS_SR_TIM_SYNC_ABL] =3D 0x0003, + [R_NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR] =3D 0x0038, + [R_NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR] =3D 0x0038, + [R_NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR] =3D 0x0058, + [R_NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR] =3D 0x0048, +}; + +static const uint16_t npcm_pcs_vr_mii_cold_reset_values[NPCM_PCS_NR_VR_MII= S] =3D { + [R_NPCM_PCS_VR_MII_MMD_DIG_CTRL1] =3D 0x2400, + [R_NPCM_PCS_VR_MII_AN_INTR_STS] =3D 0x000a, + [R_NPCM_PCS_VR_MII_EEE_MCTRL0] =3D 0x899c, + [R_NPCM_PCS_VR_MII_DIG_STS] =3D 0x0010, + [R_NPCM_PCS_VR_MII_MP_TX_BSTCTRL0] =3D 0x000a, + [R_NPCM_PCS_VR_MII_MP_TX_LVLCTRL0] =3D 0x007f, + [R_NPCM_PCS_VR_MII_MP_TX_GENCTRL0] =3D 0x0001, + [R_NPCM_PCS_VR_MII_MP_RX_GENCTRL0] =3D 0x0100, + [R_NPCM_PCS_VR_MII_MP_RX_GENCTRL1] =3D 0x1100, + [R_NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0] =3D 0x000e, + [R_NPCM_PCS_VR_MII_MP_MPLL_CTRL0] =3D 0x0100, + [R_NPCM_PCS_VR_MII_MP_MPLL_CTRL1] =3D 0x0032, + [R_NPCM_PCS_VR_MII_MP_MPLL_STS] =3D 0x0001, + [R_NPCM_PCS_VR_MII_MP_LVL_CTRL] =3D 0x0019, +}; + +static void npcm_pcs_soft_reset(NPCMPCSState *s) +{ + memcpy(s->sr_ctl, npcm_pcs_sr_ctl_cold_reset_values, + NPCM_PCS_NR_SR_CTLS * sizeof(uint16_t)); + memcpy(s->sr_mii, npcm_pcs_sr_mii_cold_reset_values, + NPCM_PCS_NR_SR_MIIS * sizeof(uint16_t)); + memcpy(s->sr_tim, npcm_pcs_sr_tim_cold_reset_values, + NPCM_PCS_NR_SR_TIMS * sizeof(uint16_t)); + memcpy(s->vr_mii, npcm_pcs_vr_mii_cold_reset_values, + NPCM_PCS_NR_VR_MIIS * sizeof(uint16_t)); +} + +static uint16_t npcm_pcs_read_sr_ctl(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_CTLS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_CTL read offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->sr_ctl[regno]; +} + +static uint16_t npcm_pcs_read_sr_mii(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_MII read offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->sr_mii[regno]; +} + +static uint16_t npcm_pcs_read_sr_tim(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_TIMS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_TIM read offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->sr_tim[regno]; +} + +static uint16_t npcm_pcs_read_vr_mii(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_VR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: VR_MII read offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->vr_mii[regno]; +} + +static void npcm_pcs_write_sr_ctl(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_CTLS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_CTL write offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return; + } + + s->sr_ctl[regno] =3D v; +} + +static void npcm_pcs_write_sr_mii(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_MII write offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return; + } + + s->sr_mii[regno] =3D v; + + if ((offset =3D=3D A_NPCM_PCS_SR_MII_CTRL) && (v & NPCM_PCS_SR_MII_CTR= L_RST)) { + /* Trigger a soft reset */ + npcm_pcs_soft_reset(s); + } +} + +static void npcm_pcs_write_sr_tim(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_TIMS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_TIM write offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return; + } + + s->sr_tim[regno] =3D v; +} + +static void npcm_pcs_write_vr_mii(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_VR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: VR_MII write offset 0x%04" HWADDR_PRIx + " is out of range.\n", + DEVICE(s)->canonical_path, offset); + return; + } + + s->vr_mii[regno] =3D v; +} + +static uint64_t npcm_pcs_read(void *opaque, hwaddr offset, unsigned size) +{ + NPCMPCSState *s =3D opaque; + uint16_t v =3D 0; + + if (offset =3D=3D NPCM_PCS_IND_AC_BA) { + v =3D s->indirect_access_base; + } else { + switch (s->indirect_access_base) { + case NPCM_PCS_IND_SR_CTL: + v =3D npcm_pcs_read_sr_ctl(s, offset); + break; + + case NPCM_PCS_IND_SR_MII: + v =3D npcm_pcs_read_sr_mii(s, offset); + break; + + case NPCM_PCS_IND_SR_TIM: + v =3D npcm_pcs_read_sr_tim(s, offset); + break; + + case NPCM_PCS_IND_VR_MII: + v =3D npcm_pcs_read_vr_mii(s, offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Read with invalid indirect address base: 0x= %" + PRIx16 "\n", DEVICE(s)->canonical_path, + s->indirect_access_base); + } + } + + trace_npcm_pcs_reg_read(DEVICE(s)->canonical_path, s->indirect_access_= base, + offset, v); + return v; +} + +static void npcm_pcs_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCMPCSState *s =3D opaque; + + trace_npcm_pcs_reg_write(DEVICE(s)->canonical_path, s->indirect_access= _base, + offset, v); + if (offset =3D=3D NPCM_PCS_IND_AC_BA) { + s->indirect_access_base =3D v; + } else { + switch (s->indirect_access_base) { + case NPCM_PCS_IND_SR_CTL: + npcm_pcs_write_sr_ctl(s, offset, v); + break; + + case NPCM_PCS_IND_SR_MII: + npcm_pcs_write_sr_mii(s, offset, v); + break; + + case NPCM_PCS_IND_SR_TIM: + npcm_pcs_write_sr_tim(s, offset, v); + break; + + case NPCM_PCS_IND_VR_MII: + npcm_pcs_write_vr_mii(s, offset, v); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write with invalid indirect address base: 0= x%02" + PRIx16 "\n", DEVICE(s)->canonical_path, + s->indirect_access_base); + } + } +} + +static void npcm_pcs_enter_reset(Object *obj, ResetType type) +{ + NPCMPCSState *s =3D NPCM_PCS(obj); + + npcm_pcs_soft_reset(s); +} + +static const struct MemoryRegionOps npcm_pcs_ops =3D { + .read =3D npcm_pcs_read, + .write =3D npcm_pcs_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 2, + .max_access_size =3D 2, + .unaligned =3D false, + }, +}; + +static void npcm_pcs_realize(DeviceState *dev, Error **errp) +{ + NPCMPCSState *pcs =3D NPCM_PCS(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&pcs->iomem, OBJECT(pcs), &npcm_pcs_ops, pcs, + TYPE_NPCM_PCS, 8 * KiB); + sysbus_init_mmio(sbd, &pcs->iomem); +} + +static const VMStateDescription vmstate_npcm_pcs =3D { + .name =3D TYPE_NPCM_PCS, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT16(indirect_access_base, NPCMPCSState), + VMSTATE_UINT16_ARRAY(sr_ctl, NPCMPCSState, NPCM_PCS_NR_SR_CTLS), + VMSTATE_UINT16_ARRAY(sr_mii, NPCMPCSState, NPCM_PCS_NR_SR_MIIS), + VMSTATE_UINT16_ARRAY(sr_tim, NPCMPCSState, NPCM_PCS_NR_SR_TIMS), + VMSTATE_UINT16_ARRAY(vr_mii, NPCMPCSState, NPCM_PCS_NR_VR_MIIS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm_pcs_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "NPCM PCS Controller"; + dc->realize =3D npcm_pcs_realize; + dc->vmsd =3D &vmstate_npcm_pcs; + rc->phases.enter =3D npcm_pcs_enter_reset; +} + +static const TypeInfo npcm_pcs_types[] =3D { + { + .name =3D TYPE_NPCM_PCS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCMPCSState), + .class_init =3D npcm_pcs_class_init, + }, +}; +DEFINE_TYPES(npcm_pcs_types) diff --git a/hw/net/trace-events b/hw/net/trace-events index 6100ec324a..daaf95beec 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -483,8 +483,8 @@ npcm_gmac_packet_tx_desc_data(const char* name, uint32_= t tdes0, uint32_t tdes1) npcm_gmac_tx_desc_owner(const char* name, uint32_t desc_addr) "%s: TX Desc= riptor @0x%04" PRIX32 " is owned by software" =20 # npcm_pcs.c -npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_= t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 "= value: 0x%04" PRIx16 -npcm_pcs_reg_write(const char *name, uint16_t indirect_access_baes, uint64= _t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 = " value: 0x%04" PRIx16 +npcm_pcs_reg_read(const char *name, uint16_t indirect_access_base, uint64_= t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 "= value: 0x%04" PRIx16 +npcm_pcs_reg_write(const char *name, uint16_t indirect_access_base, uint64= _t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 = " value: 0x%04" PRIx16 =20 # dp8398x.c dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x" diff --git a/include/hw/net/npcm_pcs.h b/include/hw/net/npcm_pcs.h new file mode 100644 index 0000000000..dd947d2a9f --- /dev/null +++ b/include/hw/net/npcm_pcs.h @@ -0,0 +1,42 @@ +/* + * Nuvoton NPCM8xx PCS Module + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef NPCM_PCS_H +#define NPCM_PCS_H + +#include "hw/sysbus.h" + +#define NPCM_PCS_NR_SR_CTLS (0x12 / sizeof(uint16_t)) +#define NPCM_PCS_NR_SR_MIIS (0x20 / sizeof(uint16_t)) +#define NPCM_PCS_NR_SR_TIMS (0x22 / sizeof(uint16_t)) +#define NPCM_PCS_NR_VR_MIIS (0x1c6 / sizeof(uint16_t)) + +struct NPCMPCSState { + SysBusDevice parent; + + MemoryRegion iomem; + + uint16_t indirect_access_base; + uint16_t sr_ctl[NPCM_PCS_NR_SR_CTLS]; + uint16_t sr_mii[NPCM_PCS_NR_SR_MIIS]; + uint16_t sr_tim[NPCM_PCS_NR_SR_TIMS]; + uint16_t vr_mii[NPCM_PCS_NR_VR_MIIS]; +} NPCMPCSState; + +#define TYPE_NPCM_PCS "npcm-pcs" +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCSState, NPCM_PCS) + +#endif /* NPCM_PCS_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201815; cv=none; d=zohomail.com; s=zohoarc; b=BCqifnbvm+xWd3ftKDJx0Dhdev9foaXNsYSYn6KnMVSNXFtfX2DMfTg+x56aKXtId3nCiDboZDFLf9hZmYjY71Wfl1mMKimqCXr5W8UI5ZAGZDFQexdUhr7EG/8SEQzr+A/HYtizHA+/nT9ffrHSJ236zDqlU9QiinMQ224r8Bw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201815; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OxFfehM4821xXaZHaI93YixF79qaBW0kU7rru3aavVg=; b=hOUabtNTMqnXUPVk/meI5+NY2QZbCA3eFhwra57/m4X8tts2v070MPUxyqJvksUhgMJX8jZGi/KPsT7bRnxIeb344eWyppVAh5J3EZIALIhE8Ed7oP7qXzOPkRZzacvuGjlj4ZF7xIna3RNBwaA3OB70OzHwqmp2gTFmSCvmVnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17352018157981014.9078668383522; Thu, 26 Dec 2024 00:30:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjF6-0007DR-03; Thu, 26 Dec 2024 03:29:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3zRNtZwgKCuoigTMafeTSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--wuhaotsh.bounces.google.com>) id 1tQjEx-0005oS-Rw for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:29:07 -0500 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3zRNtZwgKCuoigTMafeTSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--wuhaotsh.bounces.google.com>) id 1tQjEt-0001HN-JL for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:29:07 -0500 Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-2ef909597d9so11393131a91.3 for ; Thu, 26 Dec 2024 00:29:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201741; x=1735806541; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=OxFfehM4821xXaZHaI93YixF79qaBW0kU7rru3aavVg=; b=KnIDfhnKvR3bNrKQRw/lA6LREqIMW1Xg4AaTeZWn7r5EX9N/5VGHnHEMJyAcYtVpmc j8s9mA3Xw4rl3vXBPIDiq6P1rCIkspxMo7G7EntfIilas4HU1Q+HPGDDcN19M54Pn+fe SILJIm7RunGldrzEvVY+WEM6787u2YoiK4zhBcF7yse1idrKWOzA7zi3+r2r6SLxOa+W b3LivxZlUOs+UrGVccqlWTQBJb1nF+1LG8yzAgJmdkNVM4kFLm6bOlQ20CvqbIoN2fBu nq0GFLtZxWnwq/gw3mIImB+UEw9FGnx6mVqAkGI+8k10vd/Mn4jfWj2fcUIFmyd+0zRL YSvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201741; x=1735806541; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=OxFfehM4821xXaZHaI93YixF79qaBW0kU7rru3aavVg=; b=B7K3FX7DjczhO6mDUTcyOYjugySb6RT6DOGWVfpP+f+hoQ403cAaRF951JPy0vwBaj 25LWX0MpXw5UnT/43jYx3rejX8uS27KahKpTIo8fL4+546arITKrDTkKwrK6fL6RwhW9 ttWKOCH5PTt9HET6/JMKNAn++bhQiqf2EJPwoSdnibk7mdOorMpG7sKbEUXUHDn0FdZI LJ7t6Phod3hEJRnQ0QZbxD50Oyfi60gOoNC88B+tLLX6vi1UYCZeoVA54WYl114tPg0c tKnSEtRxueFZkLfRsSYDiYlhEwaF/grrbFCoGeOVA9D3WZ3E8Buz8YEHsE2D2J3hF+hU zg1g== X-Forwarded-Encrypted: i=1; AJvYcCXmkgTr8SjUGMhgM+U+B7EZRt7f+/diA4BAdFVbnT84yBn64B58ix/lQUJn0GRC3a8Tz8Z2ZmB0V7cv@nongnu.org X-Gm-Message-State: AOJu0YyL5oIOI4ktgbL8I7NkJe3RCBffOuUfkAKy/JhDGGbnkyDrgrgM U0eP6tVhE/nOrvFnDzU+OPD24I63h5TCyj/KFy0KtwsK9Ti8/YjbrZ4g1179a9rNReHSWh4H5ie RAV98RRU/jA== X-Google-Smtp-Source: AGHT+IHrhcGbFDFRLuxoy85JK28yqnKE2Ww+BE58P1R7iDOj3yz+BGpOXRqFcamZ6SSxNEA/6YwlQEztaVaEjA== X-Received: from pgjg7.prod.google.com ([2002:a63:dd47:0:b0:801:9858:ef95]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:8cc2:b0:1e1:f281:8d36 with SMTP id adf61e73a8af0-1e5e0458dbdmr33026683637.10.1735201741451; Thu, 26 Dec 2024 00:29:01 -0800 (PST) Date: Thu, 26 Dec 2024 08:27:59 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-17-wuhaotsh@google.com> Subject: [PATCH v2 16/17] hw/arm: Add NPCM8XX SoC From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::104a; envelope-from=3zRNtZwgKCuoigTMafeTSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x104a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201818192116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Hao Wu --- configs/devices/aarch64-softmmu/default.mak | 1 + hw/arm/Kconfig | 11 + hw/arm/meson.build | 1 + hw/arm/npcm8xx.c | 810 ++++++++++++++++++++ include/hw/arm/npcm8xx.h | 107 +++ 5 files changed, 930 insertions(+) create mode 100644 hw/arm/npcm8xx.c create mode 100644 include/hw/arm/npcm8xx.h diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/= aarch64-softmmu/default.mak index f82a04c27d..5ea1cc2dd1 100644 --- a/configs/devices/aarch64-softmmu/default.mak +++ b/configs/devices/aarch64-softmmu/default.mak @@ -8,3 +8,4 @@ include ../arm-softmmu/default.mak # CONFIG_XLNX_ZYNQMP_ARM=3Dn # CONFIG_XLNX_VERSAL=3Dn # CONFIG_SBSA_REF=3Dn +CONFIG_NPCM8XX=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e779b5af95..4fd5a41739 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -481,6 +481,17 @@ config NPCM7XX select PCA954X select USB_OHCI_SYSBUS =20 +config NPCM8XX + bool + select ARM_GIC + select SMBUS + select PL310 # cache controller + select NPCM7XX + select SERIAL + select SSI + select UNIMP + + config FSL_IMX25 bool default y diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 490234b3b8..d7813c089c 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -12,6 +12,7 @@ arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('music= pal.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-= h405.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_bo= ards.c')) +arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c new file mode 100644 index 0000000000..ed4185f37d --- /dev/null +++ b/hw/arm/npcm8xx.c @@ -0,0 +1,810 @@ +/* + * Nuvoton NPCM8xx SoC family. + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/arm/boot.h" +#include "hw/arm/npcm8xx.h" +#include "hw/char/serial-mm.h" +#include "hw/intc/arm_gic.h" +#include "hw/loader.h" +#include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/units.h" +#include "system/system.h" + +#define ARM_PHYS_TIMER_PPI 30 +#define ARM_VIRT_TIMER_PPI 27 +#define ARM_HYP_TIMER_PPI 26 +#define ARM_SEC_TIMER_PPI 29 + +/* + * This covers the whole MMIO space. We'll use this to catch any MMIO acce= sses + * that aren't handled by a device. + */ +#define NPCM8XX_MMIO_BA (0x80000000) +#define NPCM8XX_MMIO_SZ (0x7ffd0000) + +/* OTP fuse array */ +#define NPCM8XX_OTP_BA (0xf0189000) + +/* GIC Distributor */ +#define NPCM8XX_GICD_BA (0xdfff9000) +#define NPCM8XX_GICC_BA (0xdfffa000) + +/* Core system modules. */ +#define NPCM8XX_CPUP_BA (0xf03fe000) +#define NPCM8XX_GCR_BA (0xf0800000) +#define NPCM8XX_CLK_BA (0xf0801000) +#define NPCM8XX_MC_BA (0xf0824000) +#define NPCM8XX_RNG_BA (0xf000b000) + +/* ADC Module */ +#define NPCM8XX_ADC_BA (0xf000c000) + +/* Internal AHB SRAM */ +#define NPCM8XX_RAM3_BA (0xc0008000) +#define NPCM8XX_RAM3_SZ (4 * KiB) + +/* Memory blocks at the end of the address space */ +#define NPCM8XX_RAM2_BA (0xfffb0000) +#define NPCM8XX_RAM2_SZ (256 * KiB) +#define NPCM8XX_ROM_BA (0xffff0100) +#define NPCM8XX_ROM_SZ (64 * KiB) + +/* SDHCI Modules */ +#define NPCM8XX_MMC_BA (0xf0842000) + +/* Run PLL1 at 1600 MHz */ +#define NPCM8XX_PLLCON1_FIXUP_VAL (0x00402101) +/* Run the CPU from PLL1 and UART from PLL2 */ +#define NPCM8XX_CLKSEL_FIXUP_VAL (0x004aaba9) + +/* Clock configuration values to be fixed up when bypassing bootloader */ + +/* + * Interrupt lines going into the GIC. This does not include internal Cort= ex-A9 + * interrupts. + */ +enum NPCM8xxInterrupt { + NPCM8XX_ADC_IRQ =3D 0, + NPCM8XX_PECI_IRQ =3D 6, + NPCM8XX_KCS_HIB_IRQ =3D 9, + NPCM8XX_MMC_IRQ =3D 26, + NPCM8XX_TIMER0_IRQ =3D 32, /* Timer Module 0 */ + NPCM8XX_TIMER1_IRQ, + NPCM8XX_TIMER2_IRQ, + NPCM8XX_TIMER3_IRQ, + NPCM8XX_TIMER4_IRQ, + NPCM8XX_TIMER5_IRQ, /* Timer Module 1 */ + NPCM8XX_TIMER6_IRQ, + NPCM8XX_TIMER7_IRQ, + NPCM8XX_TIMER8_IRQ, + NPCM8XX_TIMER9_IRQ, + NPCM8XX_TIMER10_IRQ, /* Timer Module 2 */ + NPCM8XX_TIMER11_IRQ, + NPCM8XX_TIMER12_IRQ, + NPCM8XX_TIMER13_IRQ, + NPCM8XX_TIMER14_IRQ, + NPCM8XX_WDG0_IRQ =3D 47, /* Timer Module 0 Watchdog */ + NPCM8XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ + NPCM8XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ + NPCM8XX_EHCI1_IRQ =3D 61, + NPCM8XX_OHCI1_IRQ, + NPCM8XX_EHCI2_IRQ, + NPCM8XX_OHCI2_IRQ, + NPCM8XX_PWM0_IRQ =3D 93, /* PWM module 0 */ + NPCM8XX_PWM1_IRQ, /* PWM module 1 */ + NPCM8XX_MFT0_IRQ =3D 96, /* MFT module 0 */ + NPCM8XX_MFT1_IRQ, /* MFT module 1 */ + NPCM8XX_MFT2_IRQ, /* MFT module 2 */ + NPCM8XX_MFT3_IRQ, /* MFT module 3 */ + NPCM8XX_MFT4_IRQ, /* MFT module 4 */ + NPCM8XX_MFT5_IRQ, /* MFT module 5 */ + NPCM8XX_MFT6_IRQ, /* MFT module 6 */ + NPCM8XX_MFT7_IRQ, /* MFT module 7 */ + NPCM8XX_PCI_MBOX1_IRQ =3D 105, + NPCM8XX_PCI_MBOX2_IRQ, + NPCM8XX_GPIO0_IRQ =3D 116, + NPCM8XX_GPIO1_IRQ, + NPCM8XX_GPIO2_IRQ, + NPCM8XX_GPIO3_IRQ, + NPCM8XX_GPIO4_IRQ, + NPCM8XX_GPIO5_IRQ, + NPCM8XX_GPIO6_IRQ, + NPCM8XX_GPIO7_IRQ, + NPCM8XX_SMBUS0_IRQ =3D 128, + NPCM8XX_SMBUS1_IRQ, + NPCM8XX_SMBUS2_IRQ, + NPCM8XX_SMBUS3_IRQ, + NPCM8XX_SMBUS4_IRQ, + NPCM8XX_SMBUS5_IRQ, + NPCM8XX_SMBUS6_IRQ, + NPCM8XX_SMBUS7_IRQ, + NPCM8XX_SMBUS8_IRQ, + NPCM8XX_SMBUS9_IRQ, + NPCM8XX_SMBUS10_IRQ, + NPCM8XX_SMBUS11_IRQ, + NPCM8XX_SMBUS12_IRQ, + NPCM8XX_SMBUS13_IRQ, + NPCM8XX_SMBUS14_IRQ, + NPCM8XX_SMBUS15_IRQ, + NPCM8XX_SMBUS16_IRQ, + NPCM8XX_SMBUS17_IRQ, + NPCM8XX_SMBUS18_IRQ, + NPCM8XX_SMBUS19_IRQ, + NPCM8XX_SMBUS20_IRQ, + NPCM8XX_SMBUS21_IRQ, + NPCM8XX_SMBUS22_IRQ, + NPCM8XX_SMBUS23_IRQ, + NPCM8XX_SMBUS24_IRQ, + NPCM8XX_SMBUS25_IRQ, + NPCM8XX_SMBUS26_IRQ, + NPCM8XX_UART0_IRQ =3D 192, + NPCM8XX_UART1_IRQ, + NPCM8XX_UART2_IRQ, + NPCM8XX_UART3_IRQ, + NPCM8XX_UART4_IRQ, + NPCM8XX_UART5_IRQ, + NPCM8XX_UART6_IRQ, +}; + +/* Total number of GIC interrupts, including internal Cortex-A35 interrupt= s. */ +#define NPCM8XX_NUM_IRQ (288) +#define NPCM8XX_PPI_BASE(cpu) ((NPCM8XX_NUM_IRQ - 32) + (cpu) * 32) + +/* Register base address for each Timer Module */ +static const hwaddr npcm8xx_tim_addr[] =3D { + 0xf0008000, + 0xf0009000, + 0xf000a000, +}; + +/* Register base address for each 16550 UART */ +static const hwaddr npcm8xx_uart_addr[] =3D { + 0xf0000000, + 0xf0001000, + 0xf0002000, + 0xf0003000, + 0xf0004000, + 0xf0005000, + 0xf0006000, +}; + +/* Direct memory-mapped access to SPI0 CS0-1. */ +static const hwaddr npcm8xx_fiu0_flash_addr[] =3D { + 0x80000000, /* CS0 */ + 0x88000000, /* CS1 */ +}; + +/* Direct memory-mapped access to SPI1 CS0-3. */ +static const hwaddr npcm8xx_fiu1_flash_addr[] =3D { + 0x90000000, /* CS0 */ + 0x91000000, /* CS1 */ + 0x92000000, /* CS2 */ + 0x93000000, /* CS3 */ +}; + +/* Direct memory-mapped access to SPI3 CS0-3. */ +static const hwaddr npcm8xx_fiu3_flash_addr[] =3D { + 0xa0000000, /* CS0 */ + 0xa8000000, /* CS1 */ + 0xb0000000, /* CS2 */ + 0xb8000000, /* CS3 */ +}; + +/* Register base address for each PWM Module */ +static const hwaddr npcm8xx_pwm_addr[] =3D { + 0xf0103000, + 0xf0104000, + 0xf0105000, +}; + +/* Register base address for each MFT Module */ +static const hwaddr npcm8xx_mft_addr[] =3D { + 0xf0180000, + 0xf0181000, + 0xf0182000, + 0xf0183000, + 0xf0184000, + 0xf0185000, + 0xf0186000, + 0xf0187000, +}; + +/* Direct memory-mapped access to each SMBus Module. */ +static const hwaddr npcm8xx_smbus_addr[] =3D { + 0xf0080000, + 0xf0081000, + 0xf0082000, + 0xf0083000, + 0xf0084000, + 0xf0085000, + 0xf0086000, + 0xf0087000, + 0xf0088000, + 0xf0089000, + 0xf008a000, + 0xf008b000, + 0xf008c000, + 0xf008d000, + 0xf008e000, + 0xf008f000, + 0xfff00000, + 0xfff01000, + 0xfff02000, + 0xfff03000, + 0xfff04000, + 0xfff05000, + 0xfff06000, + 0xfff07000, + 0xfff08000, + 0xfff09000, + 0xfff0a000, +}; + +/* Register base address for each USB host EHCI registers */ +static const hwaddr npcm8xx_ehci_addr[] =3D { + 0xf0828100, + 0xf082a100, +}; + +/* Register base address for each USB host OHCI registers */ +static const hwaddr npcm8xx_ohci_addr[] =3D { + 0xf0829000, + 0xf082b000, +}; + +static const struct { + hwaddr regs_addr; + uint32_t reset_pu; + uint32_t reset_pd; + uint32_t reset_osrc; + uint32_t reset_odsc; +} npcm8xx_gpio[] =3D { + { + .regs_addr =3D 0xf0010000, + .reset_pu =3D 0x00000300, + .reset_pd =3D 0x000f0000, + }, { + .regs_addr =3D 0xf0011000, + .reset_pu =3D 0xe0fefe01, + .reset_pd =3D 0x07000000, + }, { + .regs_addr =3D 0xf0012000, + .reset_pu =3D 0xc00fffff, + .reset_pd =3D 0x3ff00000, + }, { + .regs_addr =3D 0xf0013000, + .reset_pd =3D 0x00003000, + }, { + .regs_addr =3D 0xf0014000, + .reset_pu =3D 0xffff0000, + }, { + .regs_addr =3D 0xf0015000, + .reset_pu =3D 0xff8387fe, + .reset_pd =3D 0x007c0001, + .reset_osrc =3D 0x08000000, + }, { + .regs_addr =3D 0xf0016000, + .reset_pu =3D 0x00000801, + .reset_pd =3D 0x00000302, + }, { + .regs_addr =3D 0xf0017000, + .reset_pu =3D 0x000002ff, + .reset_pd =3D 0x00000c00, + }, +}; + +static const struct { + const char *name; + hwaddr regs_addr; + int cs_count; + const hwaddr *flash_addr; + size_t flash_size; +} npcm8xx_fiu[] =3D { + { + .name =3D "fiu0", + .regs_addr =3D 0xfb000000, + .cs_count =3D ARRAY_SIZE(npcm8xx_fiu0_flash_addr), + .flash_addr =3D npcm8xx_fiu0_flash_addr, + .flash_size =3D 128 * MiB, + }, + { + .name =3D "fiu1", + .regs_addr =3D 0xfb002000, + .cs_count =3D ARRAY_SIZE(npcm8xx_fiu1_flash_addr), + .flash_addr =3D npcm8xx_fiu1_flash_addr, + .flash_size =3D 16 * MiB, + }, { + .name =3D "fiu3", + .regs_addr =3D 0xc0000000, + .cs_count =3D ARRAY_SIZE(npcm8xx_fiu3_flash_addr), + .flash_addr =3D npcm8xx_fiu3_flash_addr, + .flash_size =3D 128 * MiB, + }, +}; + +static struct arm_boot_info npcm8xx_binfo =3D { + .loader_start =3D NPCM8XX_LOADER_START, + .smp_loader_start =3D NPCM8XX_SMP_LOADER_START, + .smp_bootreg_addr =3D NPCM8XX_SMP_BOOTREG_ADDR, + .gic_cpu_if_addr =3D NPCM8XX_GICC_BA, + .secure_boot =3D false, + .board_id =3D -1, + .board_setup_addr =3D NPCM8XX_BOARD_SETUP_ADDR, +}; + +void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc) +{ + npcm8xx_binfo.ram_size =3D machine->ram_size; + + arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo); +} + +static void npcm8xx_init_fuses(NPCM8xxState *s) +{ + NPCM8xxClass *nc =3D NPCM8XX_GET_CLASS(s); + uint32_t value; + + /* + * The initial mask of disabled modules indicates the chip derivative = (e.g. + * NPCM750 or NPCM730). + */ + value =3D tswap32(nc->disabled_modules); + npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIV= E, + sizeof(value)); +} + +static void npcm8xx_write_adc_calibration(NPCM8xxState *s) +{ + /* Both ADC and the fuse array must have realized. */ + QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) !=3D 4); + npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, + NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); +} + +static qemu_irq npcm8xx_irq(NPCM8xxState *s, int n) +{ + return qdev_get_gpio_in(DEVICE(&s->gic), n); +} + +static void npcm8xx_init(Object *obj) +{ + NPCM8xxState *s =3D NPCM8XX(obj); + int i; + + object_initialize_child(obj, "cpu-cluster", &s->cpu_cluster, + TYPE_CPU_CLUSTER); + for (i =3D 0; i < NPCM8XX_MAX_NUM_CPUS; i++) { + object_initialize_child(OBJECT(&s->cpu_cluster), "cpu[*]", &s->cpu= [i], + ARM_CPU_TYPE_NAME("cortex-a53")); + } + object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); + object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR); + object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), + "power-on-straps"); + object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK); + object_initialize_child(obj, "otp", &s->fuse_array, + TYPE_NPCM7XX_FUSE_ARRAY); + object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); + object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); + object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); + + for (i =3D 0; i < ARRAY_SIZE(s->tim); i++) { + object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TI= MER); + } + + for (i =3D 0; i < ARRAY_SIZE(s->gpio); i++) { + object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_= GPIO); + } + + + for (i =3D 0; i < ARRAY_SIZE(s->smbus); i++) { + object_initialize_child(obj, "smbus[*]", &s->smbus[i], + TYPE_NPCM7XX_SMBUS); + DEVICE(&s->smbus[i])->id =3D g_strdup_printf("smbus[%d]", i); + } + + for (i =3D 0; i < ARRAY_SIZE(s->ehci); i++) { + object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_NPCM7XX_= EHCI); + } + for (i =3D 0; i < ARRAY_SIZE(s->ohci); i++) { + object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_O= HCI); + } + + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) !=3D ARRAY_SIZE(s->fiu)); + for (i =3D 0; i < ARRAY_SIZE(s->fiu); i++) { + object_initialize_child(obj, npcm8xx_fiu[i].name, &s->fiu[i], + TYPE_NPCM7XX_FIU); + } + + for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { + object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PW= M); + } + + for (i =3D 0; i < ARRAY_SIZE(s->mft); i++) { + object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MF= T); + } + + object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); +} + +static void npcm8xx_realize(DeviceState *dev, Error **errp) +{ + NPCM8xxState *s =3D NPCM8XX(dev); + NPCM8xxClass *nc =3D NPCM8XX_GET_CLASS(s); + int i; + + if (memory_region_size(s->dram) > NPCM8XX_DRAM_SZ) { + error_setg(errp, "%s: NPCM8xx cannot address more than %" PRIu64 + " MiB of DRAM", __func__, NPCM8XX_DRAM_SZ / MiB); + return; + } + + /* CPUs */ + for (i =3D 0; i < nc->num_cpus; i++) { + object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", + arm_build_mp_affinity(i, NPCM8XX_MAX_NUM_C= PUS), + &error_abort); + object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, + &error_abort); + object_property_set_int(OBJECT(&s->cpu[i]), "core-count", + nc->num_cpus, &error_abort); + + /* Disable security extensions. */ + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, + &error_abort); + + if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { + return; + } + } + + /* ARM GIC for Cortex A35. Can only fail if we pass bad parameters her= e. */ + object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, err= p); + object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, = errp); + object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp); + object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", t= rue, + errp); + object_property_set_bool(OBJECT(&s->gic), "irq-reset-nonsecure", true, + errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { + return; + } + for (i =3D 0; i < nc->num_cpus; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IR= Q)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FI= Q)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VI= RQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 3, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VF= IQ)); + + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_PHYS, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_PHYS_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_VIRT, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_VIRT_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_HYP, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_HYP_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_SEC, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_SEC_TIMER_PPI)); + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, NPCM8XX_GICD_BA); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, NPCM8XX_GICC_BA); + + /* CPU cluster */ + qdev_prop_set_uint32(DEVICE(&s->cpu_cluster), "cluster-id", 0); + qdev_realize(DEVICE(&s->cpu_cluster), NULL, &error_fatal); + + /* System Global Control Registers (GCR). Can fail due to user input. = */ + object_property_set_int(OBJECT(&s->gcr), "disabled-modules", + nc->disabled_modules, &error_abort); + object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->d= ram)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA); + + /* Clock Control Registers (CLK). Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA); + + /* OTP fuse strap array. Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM8XX_OTP_BA); + npcm8xx_init_fuses(s); + + /* Fake Memory Controller (MC). Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM8XX_MC_BA); + + /* ADC Modules. Cannot fail. */ + qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( + DEVICE(&s->clk), "adc-clock")); + sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM8XX_ADC_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, + npcm8xx_irq(s, NPCM8XX_ADC_IRQ)); + npcm8xx_write_adc_calibration(s); + + /* Timer Modules (TIM). Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_tim_addr) !=3D ARRAY_SIZE(s->tim)= ); + for (i =3D 0; i < ARRAY_SIZE(s->tim); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->tim[i]); + int first_irq; + int j; + + /* Connect the timer clock. */ + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_= out( + DEVICE(&s->clk), "timer-clock")); + + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm8xx_tim_addr[i]); + + first_irq =3D NPCM8XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; + for (j =3D 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { + qemu_irq irq =3D npcm8xx_irq(s, first_irq + j); + sysbus_connect_irq(sbd, j, irq); + } + + /* IRQ for watchdogs */ + sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, + npcm8xx_irq(s, NPCM8XX_WDG0_IRQ + i)); + /* GPIO that connects clk module with watchdog */ + /* TODO: Check this.*/ + qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), + NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, + qdev_get_gpio_in_named(DEVICE(&s->clk), + NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); + } + + /* UART0..6 (16550 compatible) */ + for (i =3D 0; i < ARRAY_SIZE(npcm8xx_uart_addr); i++) { + serial_mm_init(get_system_memory(), npcm8xx_uart_addr[i], 2, + npcm8xx_irq(s, NPCM8XX_UART0_IRQ + i), 115200, + serial_hd(i), DEVICE_LITTLE_ENDIAN); + } + + /* Random Number Generator. Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM8XX_RNG_BA); + + /* GPIO modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) !=3D ARRAY_SIZE(s->gpio)); + for (i =3D 0; i < ARRAY_SIZE(s->gpio); i++) { + Object *obj =3D OBJECT(&s->gpio[i]); + + object_property_set_uint(obj, "reset-pullup", + npcm8xx_gpio[i].reset_pu, &error_abort); + object_property_set_uint(obj, "reset-pulldown", + npcm8xx_gpio[i].reset_pd, &error_abort); + object_property_set_uint(obj, "reset-osrc", + npcm8xx_gpio[i].reset_osrc, &error_abort); + object_property_set_uint(obj, "reset-odsc", + npcm8xx_gpio[i].reset_odsc, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_gpio[i].regs_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm8xx_irq(s, NPCM8XX_GPIO0_IRQ + i)); + } + + /* SMBus modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) !=3D ARRAY_SIZE(s->sm= bus)); + for (i =3D 0; i < ARRAY_SIZE(s->smbus); i++) { + Object *obj =3D OBJECT(&s->smbus[i]); + + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_smbus_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm8xx_irq(s, NPCM8XX_SMBUS0_IRQ + i)); + } + + /* USB Host */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->ohci) !=3D ARRAY_SIZE(s->ehci)); + for (i =3D 0; i < ARRAY_SIZE(s->ehci); i++) { + object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", = true, + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, npcm8xx_ehci_addr[= i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, + npcm8xx_irq(s, NPCM8XX_EHCI1_IRQ + 2 * i)); + } + for (i =3D 0; i < ARRAY_SIZE(s->ohci); i++) { + object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", "usb-bus= .0", + &error_abort); + object_property_set_uint(OBJECT(&s->ohci[i]), "num-ports", 1, + &error_abort); + object_property_set_uint(OBJECT(&s->ohci[i]), "firstport", i, + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, npcm8xx_ohci_addr[= i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, + npcm8xx_irq(s, NPCM8XX_OHCI1_IRQ + 2 * i)); + } + + /* PWM Modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) !=3D ARRAY_SIZE(s->pwm)= ); + for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->pwm[i]); + + qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_= out( + DEVICE(&s->clk), "apb3-clock")); + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm8xx_pwm_addr[i]); + sysbus_connect_irq(sbd, i, npcm8xx_irq(s, NPCM8XX_PWM0_IRQ + i)); + } + + /* MFT Modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_mft_addr) !=3D ARRAY_SIZE(s->mft)= ); + for (i =3D 0; i < ARRAY_SIZE(s->mft); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->mft[i]); + + qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", + qdev_get_clock_out(DEVICE(&s->clk), + "apb4-clock")); + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm8xx_mft_addr[i]); + sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_MFT0_IRQ + i)); + } + + /* + * Flash Interface Unit (FIU). Can fail if incorrect number of chip se= lects + * specified, but this is a programming error. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) !=3D ARRAY_SIZE(s->fiu)); + for (i =3D 0; i < ARRAY_SIZE(s->fiu); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->fiu[i]); + int j; + + object_property_set_int(OBJECT(sbd), "cs-count", + npcm8xx_fiu[i].cs_count, &error_abort); + object_property_set_int(OBJECT(sbd), "flash-size", + npcm8xx_fiu[i].flash_size, &error_abort); + sysbus_realize(sbd, &error_abort); + + sysbus_mmio_map(sbd, 0, npcm8xx_fiu[i].regs_addr); + for (j =3D 0; j < npcm8xx_fiu[i].cs_count; j++) { + sysbus_mmio_map(sbd, j + 1, npcm8xx_fiu[i].flash_addr[j]); + } + } + + /* RAM2 (SRAM) */ + memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", + NPCM8XX_RAM2_SZ, &error_abort); + memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM2_BA, &s->= sram); + + /* RAM3 (SRAM) */ + memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", + NPCM8XX_RAM3_SZ, &error_abort); + memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM3_BA, &s->= ram3); + + /* Internal ROM */ + memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM8XX_ROM_SZ, + &error_abort); + memory_region_add_subregion(get_system_memory(), NPCM8XX_ROM_BA, &s->i= rom); + + /* SDHCI */ + sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM8XX_MMC_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, + npcm8xx_irq(s, NPCM8XX_MMC_IRQ)); + + + create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * = KiB); + create_unimplemented_device("npcm8xx.vdmx", 0xe0800000, 4 * = KiB); + create_unimplemented_device("npcm8xx.pcierc", 0xe1000000, 64 * = KiB); + create_unimplemented_device("npcm8xx.rootc", 0xe8000000, 128 * = MiB); + create_unimplemented_device("npcm8xx.kcs", 0xf0007000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gfxi", 0xf000e000, 4 * = KiB); + create_unimplemented_device("npcm8xx.fsw", 0xf000f000, 4 * = KiB); + create_unimplemented_device("npcm8xx.bt", 0xf0030000, 4 * = KiB); + create_unimplemented_device("npcm8xx.espi", 0xf009f000, 4 * = KiB); + create_unimplemented_device("npcm8xx.peci", 0xf0100000, 4 * = KiB); + create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * = KiB); + create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * = KiB); + create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * = KiB); + create_unimplemented_device("npcm8xx.pspi", 0xf0201000, 4 * = KiB); + create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * = KiB); + create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * = KiB); + create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * = KiB); + create_unimplemented_device("npcm8xx.jtm2", 0xf0209000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm0", 0xf0210000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm1", 0xf0211000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm2", 0xf0212000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm3", 0xf0213000, 4 * = KiB); + create_unimplemented_device("npcm8xx.ahbpci", 0xf0400000, 1 * = MiB); + create_unimplemented_device("npcm8xx.dap", 0xf0500000, 960 * = KiB); + create_unimplemented_device("npcm8xx.mcphy", 0xf05f0000, 64 * = KiB); + create_unimplemented_device("npcm8xx.pcs", 0xf0780000, 256 * = KiB); + create_unimplemented_device("npcm8xx.tsgen", 0xf07fc000, 8 * = KiB); + create_unimplemented_device("npcm8xx.gmac1", 0xf0802000, 8 * = KiB); + create_unimplemented_device("npcm8xx.gmac2", 0xf0804000, 8 * = KiB); + create_unimplemented_device("npcm8xx.gmac3", 0xf0806000, 8 * = KiB); + create_unimplemented_device("npcm8xx.gmac4", 0xf0808000, 8 * = KiB); + create_unimplemented_device("npcm8xx.copctl", 0xf080c000, 4 * = KiB); + create_unimplemented_device("npcm8xx.tipctl", 0xf080d000, 4 * = KiB); + create_unimplemented_device("npcm8xx.rst", 0xf080e000, 4 * = KiB); + create_unimplemented_device("npcm8xx.vcd", 0xf0810000, 64 * = KiB); + create_unimplemented_device("npcm8xx.ece", 0xf0820000, 8 * = KiB); + create_unimplemented_device("npcm8xx.vdma", 0xf0822000, 8 * = KiB); + create_unimplemented_device("npcm8xx.usbd[0]", 0xf0830000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[1]", 0xf0831000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[2]", 0xf0832000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[3]", 0xf0833000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[4]", 0xf0834000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[5]", 0xf0835000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[6]", 0xf0836000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[7]", 0xf0837000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[8]", 0xf0838000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[9]", 0xf0839000, 4 * = KiB); + create_unimplemented_device("npcm8xx.pci_mbox1", 0xf0848000, 64 * = KiB); + create_unimplemented_device("npcm8xx.gdma0", 0xf0850000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gdma1", 0xf0851000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gdma2", 0xf0852000, 4 * = KiB); + create_unimplemented_device("npcm8xx.aes", 0xf0858000, 4 * = KiB); + create_unimplemented_device("npcm8xx.des", 0xf0859000, 4 * = KiB); + create_unimplemented_device("npcm8xx.sha", 0xf085a000, 4 * = KiB); + create_unimplemented_device("npcm8xx.pci_mbox2", 0xf0868000, 64 * = KiB); + create_unimplemented_device("npcm8xx.i3c0", 0xfff10000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c1", 0xfff11000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c2", 0xfff12000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c3", 0xfff13000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c4", 0xfff14000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c5", 0xfff15000, 4 * = KiB); + create_unimplemented_device("npcm8xx.spixcs0", 0xf8000000, 16 * = MiB); + create_unimplemented_device("npcm8xx.spixcs1", 0xf9000000, 16 * = MiB); + create_unimplemented_device("npcm8xx.spix", 0xfb001000, 4 * = KiB); + create_unimplemented_device("npcm8xx.vect", 0xffff0000, 256); +} + +static const Property npcm8xx_properties[] =3D { + DEFINE_PROP_LINK("dram-mr", NPCM8xxState, dram, TYPE_MEMORY_REGION, + MemoryRegion *), +}; + +static void npcm8xx_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + NPCM8xxClass *nc =3D NPCM8XX_CLASS(oc); + + dc->realize =3D npcm8xx_realize; + dc->user_creatable =3D false; + nc->disabled_modules =3D 0x00000000; + nc->num_cpus =3D NPCM8XX_MAX_NUM_CPUS; + device_class_set_props(dc, npcm8xx_properties); +} + +static const TypeInfo npcm8xx_soc_types[] =3D { + { + .name =3D TYPE_NPCM8XX, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(NPCM8xxState), + .instance_init =3D npcm8xx_init, + .class_size =3D sizeof(NPCM8xxClass), + .class_init =3D npcm8xx_class_init, + }, +}; + +DEFINE_TYPES(npcm8xx_soc_types); diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h new file mode 100644 index 0000000000..1f7e3d8116 --- /dev/null +++ b/include/hw/arm/npcm8xx.h @@ -0,0 +1,107 @@ +/* + * Nuvoton NPCM8xx SoC family. + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM8XX_H +#define NPCM8XX_H + +#include "hw/boards.h" +#include "hw/adc/npcm7xx_adc.h" +#include "hw/core/split-irq.h" +#include "hw/cpu/cluster.h" +#include "hw/gpio/npcm7xx_gpio.h" +#include "hw/i2c/npcm7xx_smbus.h" +#include "hw/intc/arm_gic_common.h" +#include "hw/mem/npcm7xx_mc.h" +#include "hw/misc/npcm_clk.h" +#include "hw/misc/npcm_gcr.h" +#include "hw/misc/npcm7xx_mft.h" +#include "hw/misc/npcm7xx_pwm.h" +#include "hw/misc/npcm7xx_rng.h" +#include "hw/net/npcm7xx_emc.h" +#include "hw/nvram/npcm7xx_otp.h" +#include "hw/sd/npcm7xx_sdhci.h" +#include "hw/timer/npcm7xx_timer.h" +#include "hw/ssi/npcm7xx_fiu.h" +#include "hw/usb/hcd-ehci.h" +#include "hw/usb/hcd-ohci.h" +#include "target/arm/cpu.h" + +#define NPCM8XX_MAX_NUM_CPUS (4) + +/* The first half of the address space is reserved for DDR4 DRAM. */ +#define NPCM8XX_DRAM_BA (0x00000000) +#define NPCM8XX_DRAM_SZ (2 * GiB) + +/* Magic addresses for setting up direct kernel booting and SMP boot stubs= . */ +#define NPCM8XX_LOADER_START (0x00000000) /* Start of SDRAM */ +#define NPCM8XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ +#define NPCM8XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ +#define NPCM8XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ + +#define NPCM8XX_NR_PWM_MODULES 3 + +typedef struct NPCM8xxState { + DeviceState parent; + + ARMCPU cpu[NPCM8XX_MAX_NUM_CPUS]; + CPUClusterState cpu_cluster; + GICState gic; + + MemoryRegion sram; + MemoryRegion irom; + MemoryRegion ram3; + MemoryRegion *dram; + + NPCMGCRState gcr; + NPCMCLKState clk; + NPCM7xxTimerCtrlState tim[3]; + NPCM7xxADCState adc; + NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; + NPCM7xxMFTState mft[8]; + NPCM7xxOTPState fuse_array; + NPCM7xxMCState mc; + NPCM7xxRNGState rng; + NPCM7xxGPIOState gpio[8]; + NPCM7xxSMBusState smbus[27]; + EHCISysBusState ehci[2]; + OHCISysBusState ohci[2]; + NPCM7xxFIUState fiu[3]; + NPCM7xxSDHCIState mmc; +} NPCM8xxState; + +typedef struct NPCM8xxClass { + DeviceClass parent; + + /* Bitmask of modules that are permanently disabled on this chip. */ + uint32_t disabled_modules; + /* Number of CPU cores enabled in this SoC class. */ + uint32_t num_cpus; +} NPCM8xxClass; + +#define TYPE_NPCM8XX "npcm8xx" +OBJECT_DECLARE_TYPE(NPCM8xxState, NPCM8xxClass, NPCM8XX) + +/** + * npcm8xx_load_kernel - Loads memory with everything needed to boot + * @machine - The machine containing the SoC to be booted. + * @soc - The SoC containing the CPU to be booted. + * + * This will set up the ARM boot info structure for the specific NPCM8xx + * derivative and call arm_load_kernel() to set up loading of the kernel, = etc. + * into memory, if requested by the user. + */ +void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc); + +#endif /* NPCM8XX_H */ --=20 2.47.1.613.gc27f4b7a9f-goog From nobody Fri Mar 14 18:45:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1735201758; cv=none; d=zohomail.com; s=zohoarc; b=iAA7G2a7iGy4uu3wK/MQ+FkTrRdCMX9bRxmA6wPVgHoszQWHNFtILcesr3BNGJGpO+YVAwUkZSJ2pxSefu8hFOjJXIxrAFn/Nt6AkMtVeDxoyk2V9xzU2v0Z9fR/RH3ki0KLg3YGdzLWt8BKOIjFw6p3okLlVVDrrU/A/Zctvlc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735201758; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3GGcstd8AkyO5x+B+J9MntL4e/gHviPXgQYcMwiO+Co=; b=GTZV4FpII5Nb8WsZNGqoC63IUe+oAQFFNRtqwUl+puBKC4HsA99V646LgQZhXF4j2bQOFJOLo5PjK7gurNtDP2lF9RKMUr8Azg7bw/nzr+kfqFg+ZWXxU0gDgBKX9NCgh5MNEyB8yN5cqi9lrB3X/0LALSOAo+9wuLAeIrRmrvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735201758793731.8602499471544; Thu, 26 Dec 2024 00:29:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQjF2-0006Qx-7a; Thu, 26 Dec 2024 03:29:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <30RNtZwgKCu4mkXQejiXWeeWbU.SecgUck-TUlUbdedWdk.ehW@flex--wuhaotsh.bounces.google.com>) id 1tQjEz-000654-Ma for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:29:10 -0500 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <30RNtZwgKCu4mkXQejiXWeeWbU.SecgUck-TUlUbdedWdk.ehW@flex--wuhaotsh.bounces.google.com>) id 1tQjEw-0001HZ-VW for qemu-devel@nongnu.org; Thu, 26 Dec 2024 03:29:09 -0500 Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-2164861e1feso77084575ad.1 for ; Thu, 26 Dec 2024 00:29:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1735201745; x=1735806545; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=3GGcstd8AkyO5x+B+J9MntL4e/gHviPXgQYcMwiO+Co=; b=bBDD2GT8eBD/VS9ghWXwNfq9YSqKWuc0LebHGhJ01BwCTK4od8p8+M4DhsO6Vn9y5M ltZGJwD4O9N8S6IL5N4QSHj5qQ62zV2eHn3+xc5ii2JIB6ICbrCk5aYNs6kfeyiS3Xcm qmXgZd1JpVeIz0dbCitOrw6N0/+rufHQoXR37cisQqDbUGa4puDe3MK5TCV6wcgV07El UdFfSSq4hKjZpqwiM5l6HD/jvF+ouhA8c1qVH3oGYMRyR6H8P3nvmjphnUIqNue8P3R8 jYbRGRimVJ4ZzERR3oX8h58jcsnv4Pvwh18KP5WvVcRCBS6BSiccni/UVRmKi7lbqvnh bfMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735201745; x=1735806545; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3GGcstd8AkyO5x+B+J9MntL4e/gHviPXgQYcMwiO+Co=; b=wofinC/18+wk6oLJIXZDziC3dg8RC5wjEzAog/82L5c3vqDVfLf9N67VvPjJOMC5+q 7gNbcEGkK1OZuu3tvvsgsbMOzHkBjbvnjg4/yRzkTOZVtziF2uZhBrhDWPnhWxqKCBXt i46ZlKRIdEo2AlanhbgFpulDGtt4W/zTPV3Ku1kQitiFxJf4TbG2tcylt/WwtuwA8ajw PaE1Wsib5V0uks1gQDGkj7NpiY5yDftvMHE7Hylx+dSdczt5sQc+SMNTpwltbYVGlLaS IRJXwHhO/IMHIxEdKkHZBPPlz3ru3SEqVVe8++XhGlZ38HgS7fLGENEE/t5UekxStXBv UmaA== X-Forwarded-Encrypted: i=1; AJvYcCXPEQkkqKy010ReJ/rVtVMj5SK8iegOkfFXg2ohF1fFra6fdgtLJLmzV+YPp3QGkHfPL/XtW63g0nOD@nongnu.org X-Gm-Message-State: AOJu0YxWAgILuItNKl1YFqedKYmXp1u0/9J9pKGHR7iMx6uKQ2Ip7aBC U2yLsOVuNeBbpYQLAyG2p/zti44XYH9V15u0GTdUmMYGyKslde57zX6x/aOg2gx3r1CbKayhlDq Zs2Uw+ARQhg== X-Google-Smtp-Source: AGHT+IGlmQgpRNFvbP5vTiuTUvNj8IJstbU6TWTGl8hjUCpNUCV6lA2+U9Qk357eRx8FzRhcoL6Jyr6w/BViiw== X-Received: from pfbby11.prod.google.com ([2002:a05:6a00:400b:b0:71e:4dee:9d6b]) (user=wuhaotsh job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:2446:b0:1e1:ad39:cc5c with SMTP id adf61e73a8af0-1e5e0460a53mr40561533637.14.1735201745040; Thu, 26 Dec 2024 00:29:05 -0800 (PST) Date: Thu, 26 Dec 2024 08:28:00 +0000 In-Reply-To: <20241226082800.2887689-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20241226082800.2887689-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.47.1.613.gc27f4b7a9f-goog Message-ID: <20241226082800.2887689-18-wuhaotsh@google.com> Subject: [PATCH v2 17/17] hw/arm: Add NPCM845 Evaluation board From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, titusr@google.com, mimik-dev@google.com, hskinnemoen@google.com, venture@google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me, Hao Wu Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=30RNtZwgKCu4mkXQejiXWeeWbU.SecgUck-TUlUbdedWdk.ehW@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1735201759877116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Hao Wu Reviewed-by: Peter Maydell --- hw/arm/meson.build | 2 +- hw/arm/npcm8xx_boards.c | 256 +++++++++++++++++++++++++++++++++++++++ include/hw/arm/npcm8xx.h | 20 +++ 3 files changed, 277 insertions(+), 1 deletion(-) create mode 100644 hw/arm/npcm8xx_boards.c diff --git a/hw/arm/meson.build b/hw/arm/meson.build index d7813c089c..465c757f97 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -12,7 +12,7 @@ arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('music= pal.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-= h405.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_bo= ards.c')) -arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c')) +arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npcm8xx_bo= ards.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c new file mode 100644 index 0000000000..079df695d3 --- /dev/null +++ b/hw/arm/npcm8xx_boards.c @@ -0,0 +1,256 @@ +/* + * Machine definitions for boards featuring an NPCM8xx SoC. + * + * Copyright 2021 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "chardev/char.h" +#include "hw/arm/npcm8xx.h" +#include "hw/core/cpu.h" +#include "hw/loader.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/datadir.h" +#include "qemu/units.h" + +#define NPCM845_EVB_POWER_ON_STRAPS 0x000017ff + +static const char npcm8xx_default_bootrom[] =3D "npcm8xx_bootrom.bin"; + +static void npcm8xx_load_bootrom(MachineState *machine, NPCM8xxState *soc) +{ + const char *bios_name =3D machine->firmware ?: npcm8xx_default_bootrom; + g_autofree char *filename =3D NULL; + int ret; + + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (!filename) { + error_report("Could not find ROM image '%s'", bios_name); + if (!machine->kernel_filename) { + /* We can't boot without a bootrom or a kernel image. */ + exit(1); + } + return; + } + ret =3D load_image_mr(filename, machine->ram); + if (ret < 0) { + error_report("Failed to load ROM image '%s'", filename); + exit(1); + } +} + +static void npcm8xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no, + const char *flash_type, DriveInfo *dinfo) +{ + DeviceState *flash; + qemu_irq flash_cs; + + flash =3D qdev_new(flash_type); + if (dinfo) { + qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo)); + } + qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); + + flash_cs =3D qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0); + qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs); +} + +static void npcm8xx_connect_dram(NPCM8xxState *soc, MemoryRegion *dram) +{ + memory_region_add_subregion(get_system_memory(), NPCM8XX_DRAM_BA, dram= ); + + object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), + &error_abort); +} + +static NPCM8xxState *npcm8xx_create_soc(MachineState *machine, + uint32_t hw_straps) +{ + NPCM8xxMachineClass *nmc =3D NPCM8XX_MACHINE_GET_CLASS(machine); + MachineClass *mc =3D MACHINE_CLASS(nmc); + Object *obj; + + if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { + error_report("This board can only be used with %s", + mc->default_cpu_type); + exit(1); + } + + obj =3D object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", + &error_abort, NULL); + object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abo= rt); + + return NPCM8XX(obj); +} + +static I2CBus *npcm8xx_i2c_get_bus(NPCM8xxState *soc, uint32_t num) +{ + g_assert(num < ARRAY_SIZE(soc->smbus)); + return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")= ); +} + +static void npcm8xx_init_pwm_splitter(NPCM8xxMachine *machine, + NPCM8xxState *soc, const int *fan_co= unts) +{ + SplitIRQ *splitters =3D machine->fan_splitter; + + /* + * PWM 0~3 belong to module 0 output 0~3. + * PWM 4~7 belong to module 1 output 0~3. + */ + for (int i =3D 0; i < NPCM8XX_NR_PWM_MODULES; ++i) { + for (int j =3D 0; j < NPCM7XX_PWM_PER_MODULE; ++j) { + int splitter_no =3D i * NPCM7XX_PWM_PER_MODULE + j; + DeviceState *splitter; + + if (fan_counts[splitter_no] < 1) { + continue; + } + object_initialize_child(OBJECT(machine), "fan-splitter[*]", + &splitters[splitter_no], TYPE_SPLIT_IR= Q); + splitter =3D DEVICE(&splitters[splitter_no]); + qdev_prop_set_uint16(splitter, "num-lines", + fan_counts[splitter_no]); + qdev_realize(splitter, NULL, &error_abort); + qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-o= ut", + j, qdev_get_gpio_in(splitter, 0)); + } + } +} + +static void npcm8xx_connect_pwm_fan(NPCM8xxState *soc, SplitIRQ *splitter, + int fan_no, int output_no) +{ + DeviceState *fan; + int fan_input; + qemu_irq fan_duty_gpio; + + g_assert(fan_no >=3D 0 && fan_no <=3D NPCM7XX_MFT_MAX_FAN_INPUT); + /* + * Fan 0~1 belong to module 0 input 0~1. + * Fan 2~3 belong to module 1 input 0~1. + * ... + * Fan 14~15 belong to module 7 input 0~1. + * Fan 16~17 belong to module 0 input 2~3. + * Fan 18~19 belong to module 1 input 2~3. + */ + if (fan_no < 16) { + fan =3D DEVICE(&soc->mft[fan_no / 2]); + fan_input =3D fan_no % 2; + } else { + fan =3D DEVICE(&soc->mft[(fan_no - 16) / 2]); + fan_input =3D fan_no % 2 + 2; + } + + /* Connect the Fan to PWM module */ + fan_duty_gpio =3D qdev_get_gpio_in_named(fan, "duty", fan_input); + qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio); +} + +static void npcm845_evb_i2c_init(NPCM8xxState *soc) +{ + /* tmp100 temperature sensor on SVB, tmp105 is compatible */ + i2c_slave_create_simple(npcm8xx_i2c_get_bus(soc, 6), "tmp105", 0x48); +} + +static void npcm845_evb_fan_init(NPCM8xxMachine *machine, NPCM8xxState *so= c) +{ + SplitIRQ *splitter =3D machine->fan_splitter; + static const int fan_counts[] =3D {2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0}; + + npcm8xx_init_pwm_splitter(machine, soc, fan_counts); + npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); + npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); + npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); + npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1); + npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1); + npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1); + npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1); + npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0); + npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1); +} + +static void npcm845_evb_init(MachineState *machine) +{ + NPCM8xxState *soc; + + soc =3D npcm8xx_create_soc(machine, NPCM845_EVB_POWER_ON_STRAPS); + npcm8xx_connect_dram(soc, machine->ram); + qdev_realize(DEVICE(soc), NULL, &error_fatal); + + npcm8xx_load_bootrom(machine, soc); + npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0,= 0)); + npcm845_evb_i2c_init(soc); + npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc); + npcm8xx_load_kernel(machine, soc); +} + +static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *typ= e) +{ + NPCM8xxClass *sc =3D NPCM8XX_CLASS(object_class_by_name(type)); + MachineClass *mc =3D MACHINE_CLASS(nmc); + + nmc->soc_type =3D type; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D sc->num_cpus; +} + +static void npcm8xx_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->no_floppy =3D 1; + mc->no_cdrom =3D 1; + mc->no_parallel =3D 1; + mc->default_ram_id =3D "ram"; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"); +} + +static void npcm845_evb_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM8xxMachineClass *nmc =3D NPCM8XX_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + npcm8xx_set_soc_type(nmc, TYPE_NPCM8XX); + + mc->desc =3D "Nuvoton NPCM845 Evaluation Board (Cortex-A35)"; + mc->init =3D npcm845_evb_init; + mc->default_ram_size =3D 1 * GiB; +}; + +static const TypeInfo npcm8xx_machine_types[] =3D { + { + .name =3D TYPE_NPCM8XX_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(NPCM8xxMachine), + .class_size =3D sizeof(NPCM8xxMachineClass), + .class_init =3D npcm8xx_machine_class_init, + .abstract =3D true, + }, { + .name =3D MACHINE_TYPE_NAME("npcm845-evb"), + .parent =3D TYPE_NPCM8XX_MACHINE, + .class_init =3D npcm845_evb_machine_class_init, + }, +}; + +DEFINE_TYPES(npcm8xx_machine_types) diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h index 1f7e3d8116..f465d1eeb5 100644 --- a/include/hw/arm/npcm8xx.h +++ b/include/hw/arm/npcm8xx.h @@ -52,6 +52,26 @@ =20 #define NPCM8XX_NR_PWM_MODULES 3 =20 +typedef struct NPCM8xxMachine { + MachineState parent; + /* + * PWM fan splitter. each splitter connects to one PWM output and + * multiple MFT inputs. + */ + SplitIRQ fan_splitter[NPCM8XX_NR_PWM_MODULES * + NPCM7XX_PWM_PER_MODULE]; +} NPCM8xxMachine; + + +typedef struct NPCM8xxMachineClass { + MachineClass parent; + + const char *soc_type; +} NPCM8xxMachineClass; + +#define TYPE_NPCM8XX_MACHINE MACHINE_TYPE_NAME("npcm8xx") +OBJECT_DECLARE_TYPE(NPCM8xxMachine, NPCM8xxMachineClass, NPCM8XX_MACHINE) + typedef struct NPCM8xxState { DeviceState parent; =20 --=20 2.47.1.613.gc27f4b7a9f-goog