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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Thu, 26 Dec 2024 21:19:37 +0000
Subject: [PATCH v2 06/23] target/loongarch: Store some uint64_t values as
target_ulong
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To: qemu-devel@nongnu.org
Cc: Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>,
Eric Blake <eblake@redhat.com>, Markus Armbruster <armbru@redhat.com>,
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=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,
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Store internal registers including GPRs, CSRs, and LBT scratchs
as target_ulong, as per architecture specification.
The only exception here is tlb_misc, as it's only used by QEMU
internally and need keep to be 64bit to store all required fields.
There is no migration ABI change, as target_ulong is uint64_t on
existing loongarch64 builds anyway.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/loongarch/cpu.c | 34 ++++++------
target/loongarch/cpu.h | 132 ++++++++++++++++++++++-------------------=
----
target/loongarch/machine.c | 120 ++++++++++++++++++++---------------------
3 files changed, 143 insertions(+), 143 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f5bc8720d1fc1b28950ee02de5ae6cce86fc6a96..82412f8867a50a6cd25cff511de=
f0f24d2b10b49 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -748,7 +748,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE=
*f, int flags)
CPULoongArchState *env =3D cpu_env(cs);
int i;
=20
- qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc);
+ qemu_fprintf(f, " PC=3D" TARGET_FMT_lx " ", env->pc);
qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0);
=20
/* gpr */
@@ -756,28 +756,28 @@ static void loongarch_cpu_dump_state(CPUState *cs, FI=
LE *f, int flags)
if ((i & 3) =3D=3D 0) {
qemu_fprintf(f, " GPR%02d:", i);
}
- qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]);
if ((i & 3) =3D=3D 3) {
qemu_fprintf(f, "\n");
}
}
=20
- qemu_fprintf(f, "CRMD=3D%016" PRIx64 "\n", env->CSR_CRMD);
- qemu_fprintf(f, "PRMD=3D%016" PRIx64 "\n", env->CSR_PRMD);
- qemu_fprintf(f, "EUEN=3D%016" PRIx64 "\n", env->CSR_EUEN);
- qemu_fprintf(f, "ESTAT=3D%016" PRIx64 "\n", env->CSR_ESTAT);
- qemu_fprintf(f, "ERA=3D%016" PRIx64 "\n", env->CSR_ERA);
- qemu_fprintf(f, "BADV=3D%016" PRIx64 "\n", env->CSR_BADV);
- qemu_fprintf(f, "BADI=3D%016" PRIx64 "\n", env->CSR_BADI);
- qemu_fprintf(f, "EENTRY=3D%016" PRIx64 "\n", env->CSR_EENTRY);
- qemu_fprintf(f, "PRCFG1=3D%016" PRIx64 ", PRCFG2=3D%016" PRIx64 ","
- " PRCFG3=3D%016" PRIx64 "\n",
+ qemu_fprintf(f, "CRMD=3D" TARGET_FMT_lx "\n", env->CSR_CRMD);
+ qemu_fprintf(f, "PRMD=3D" TARGET_FMT_lx "\n", env->CSR_PRMD);
+ qemu_fprintf(f, "EUEN=3D" TARGET_FMT_lx "\n", env->CSR_EUEN);
+ qemu_fprintf(f, "ESTAT=3D" TARGET_FMT_lx "\n", env->CSR_ESTAT);
+ qemu_fprintf(f, "ERA=3D" TARGET_FMT_lx "\n", env->CSR_ERA);
+ qemu_fprintf(f, "BADV=3D" TARGET_FMT_lx "\n", env->CSR_BADV);
+ qemu_fprintf(f, "BADI=3D" TARGET_FMT_lx "\n", env->CSR_BADI);
+ qemu_fprintf(f, "EENTRY=3D" TARGET_FMT_lx "\n", env->CSR_EENTRY);
+ qemu_fprintf(f, "PRCFG1=3D" TARGET_FMT_lx ", PRCFG2=3D" TARGET_FMT_lx =
","
+ " PRCFG3=3D" TARGET_FMT_lx "\n",
env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
- qemu_fprintf(f, "TLBRENTRY=3D%016" PRIx64 "\n", env->CSR_TLBRENTRY);
- qemu_fprintf(f, "TLBRBADV=3D%016" PRIx64 "\n", env->CSR_TLBRBADV);
- qemu_fprintf(f, "TLBRERA=3D%016" PRIx64 "\n", env->CSR_TLBRERA);
- qemu_fprintf(f, "TCFG=3D%016" PRIx64 "\n", env->CSR_TCFG);
- qemu_fprintf(f, "TVAL=3D%016" PRIx64 "\n", env->CSR_TVAL);
+ qemu_fprintf(f, "TLBRENTRY=3D" TARGET_FMT_lx "\n", env->CSR_TLBRENTRY);
+ qemu_fprintf(f, "TLBRBADV=3D" TARGET_FMT_lx "\n", env->CSR_TLBRBADV);
+ qemu_fprintf(f, "TLBRERA=3D" TARGET_FMT_lx "\n", env->CSR_TLBRERA);
+ qemu_fprintf(f, "TCFG=3D" TARGET_FMT_lx "\n", env->CSR_TCFG);
+ qemu_fprintf(f, "TVAL=3D" TARGET_FMT_lx "\n", env->CSR_TVAL);
=20
/* fpr */
if (flags & CPU_DUMP_FPU) {
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 86c86c6c958db1a215a3e76a27f379bd4a095fb6..4f542a3376831141d012f177dc4=
6a0e928afc85c 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -276,8 +276,8 @@ union fpr_t {
struct LoongArchTLB {
uint64_t tlb_misc;
/* Fields corresponding to CSR_TLBELO0/1 */
- uint64_t tlb_entry0;
- uint64_t tlb_entry1;
+ target_ulong tlb_entry0;
+ target_ulong tlb_entry1;
};
typedef struct LoongArchTLB LoongArchTLB;
#endif
@@ -289,18 +289,18 @@ enum loongarch_features {
=20
typedef struct LoongArchBT {
/* scratch registers */
- uint64_t scr0;
- uint64_t scr1;
- uint64_t scr2;
- uint64_t scr3;
+ target_ulong scr0;
+ target_ulong scr1;
+ target_ulong scr2;
+ target_ulong scr3;
/* loongarch eflags */
uint32_t eflags;
uint32_t ftop;
} lbt_t;
=20
typedef struct CPUArchState {
- uint64_t gpr[32];
- uint64_t pc;
+ target_ulong gpr[32];
+ target_ulong pc;
=20
fpr_t fpr[32];
bool cf[8];
@@ -310,69 +310,69 @@ typedef struct CPUArchState {
uint32_t cpucfg[21];
=20
/* LoongArch CSRs */
- uint64_t CSR_CRMD;
- uint64_t CSR_PRMD;
- uint64_t CSR_EUEN;
- uint64_t CSR_MISC;
- uint64_t CSR_ECFG;
- uint64_t CSR_ESTAT;
- uint64_t CSR_ERA;
- uint64_t CSR_BADV;
- uint64_t CSR_BADI;
- uint64_t CSR_EENTRY;
- uint64_t CSR_TLBIDX;
- uint64_t CSR_TLBEHI;
- uint64_t CSR_TLBELO0;
- uint64_t CSR_TLBELO1;
- uint64_t CSR_ASID;
- uint64_t CSR_PGDL;
- uint64_t CSR_PGDH;
- uint64_t CSR_PGD;
- uint64_t CSR_PWCL;
- uint64_t CSR_PWCH;
- uint64_t CSR_STLBPS;
- uint64_t CSR_RVACFG;
- uint64_t CSR_CPUID;
- uint64_t CSR_PRCFG1;
- uint64_t CSR_PRCFG2;
- uint64_t CSR_PRCFG3;
- uint64_t CSR_SAVE[16];
- uint64_t CSR_TID;
- uint64_t CSR_TCFG;
- uint64_t CSR_TVAL;
- uint64_t CSR_CNTC;
- uint64_t CSR_TICLR;
- uint64_t CSR_LLBCTL;
- uint64_t CSR_IMPCTL1;
- uint64_t CSR_IMPCTL2;
- uint64_t CSR_TLBRENTRY;
- uint64_t CSR_TLBRBADV;
- uint64_t CSR_TLBRERA;
- uint64_t CSR_TLBRSAVE;
- uint64_t CSR_TLBRELO0;
- uint64_t CSR_TLBRELO1;
- uint64_t CSR_TLBREHI;
- uint64_t CSR_TLBRPRMD;
- uint64_t CSR_MERRCTL;
- uint64_t CSR_MERRINFO1;
- uint64_t CSR_MERRINFO2;
- uint64_t CSR_MERRENTRY;
- uint64_t CSR_MERRERA;
- uint64_t CSR_MERRSAVE;
- uint64_t CSR_CTAG;
- uint64_t CSR_DMW[4];
- uint64_t CSR_DBG;
- uint64_t CSR_DERA;
- uint64_t CSR_DSAVE;
+ target_ulong CSR_CRMD;
+ target_ulong CSR_PRMD;
+ target_ulong CSR_EUEN;
+ target_ulong CSR_MISC;
+ target_ulong CSR_ECFG;
+ target_ulong CSR_ESTAT;
+ target_ulong CSR_ERA;
+ target_ulong CSR_BADV;
+ target_ulong CSR_BADI;
+ target_ulong CSR_EENTRY;
+ target_ulong CSR_TLBIDX;
+ target_ulong CSR_TLBEHI;
+ target_ulong CSR_TLBELO0;
+ target_ulong CSR_TLBELO1;
+ target_ulong CSR_ASID;
+ target_ulong CSR_PGDL;
+ target_ulong CSR_PGDH;
+ target_ulong CSR_PGD;
+ target_ulong CSR_PWCL;
+ target_ulong CSR_PWCH;
+ target_ulong CSR_STLBPS;
+ target_ulong CSR_RVACFG;
+ target_ulong CSR_CPUID;
+ target_ulong CSR_PRCFG1;
+ target_ulong CSR_PRCFG2;
+ target_ulong CSR_PRCFG3;
+ target_ulong CSR_SAVE[16];
+ target_ulong CSR_TID;
+ target_ulong CSR_TCFG;
+ target_ulong CSR_TVAL;
+ target_ulong CSR_CNTC;
+ target_ulong CSR_TICLR;
+ target_ulong CSR_LLBCTL;
+ target_ulong CSR_IMPCTL1;
+ target_ulong CSR_IMPCTL2;
+ target_ulong CSR_TLBRENTRY;
+ target_ulong CSR_TLBRBADV;
+ target_ulong CSR_TLBRERA;
+ target_ulong CSR_TLBRSAVE;
+ target_ulong CSR_TLBRELO0;
+ target_ulong CSR_TLBRELO1;
+ target_ulong CSR_TLBREHI;
+ target_ulong CSR_TLBRPRMD;
+ target_ulong CSR_MERRCTL;
+ target_ulong CSR_MERRINFO1;
+ target_ulong CSR_MERRINFO2;
+ target_ulong CSR_MERRENTRY;
+ target_ulong CSR_MERRERA;
+ target_ulong CSR_MERRSAVE;
+ target_ulong CSR_CTAG;
+ target_ulong CSR_DMW[4];
+ target_ulong CSR_DBG;
+ target_ulong CSR_DERA;
+ target_ulong CSR_DSAVE;
struct {
- uint64_t guest_addr;
+ target_ulong guest_addr;
} stealtime;
=20
#ifdef CONFIG_TCG
float_status fp_status;
uint32_t fcsr0_mask;
- uint64_t lladdr; /* LL virtual address compared against SC */
- uint64_t llval;
+ target_ulong lladdr; /* LL virtual address compared against SC */
+ target_ulong llval;
#endif
#ifndef CONFIG_USER_ONLY
#ifdef CONFIG_TCG
@@ -381,7 +381,7 @@ typedef struct CPUArchState {
=20
AddressSpace *address_space_iocsr;
bool load_elf;
- uint64_t elf_address;
+ target_ulong elf_address;
uint32_t mp_state;
/* Store ipistate to access from this struct */
DeviceState *ipistate;
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index 4e70f5c8798bdc826df809c98e8adb4ebf879c39..ba6e4f9df259c9a25962a4cfa18=
0280f56ba6077 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -123,10 +123,10 @@ static const VMStateDescription vmstate_lbt =3D {
.minimum_version_id =3D 0,
.needed =3D lbt_needed,
.fields =3D (const VMStateField[]) {
- VMSTATE_UINT64(env.lbt.scr0, LoongArchCPU),
- VMSTATE_UINT64(env.lbt.scr1, LoongArchCPU),
- VMSTATE_UINT64(env.lbt.scr2, LoongArchCPU),
- VMSTATE_UINT64(env.lbt.scr3, LoongArchCPU),
+ VMSTATE_UINTTL(env.lbt.scr0, LoongArchCPU),
+ VMSTATE_UINTTL(env.lbt.scr1, LoongArchCPU),
+ VMSTATE_UINTTL(env.lbt.scr2, LoongArchCPU),
+ VMSTATE_UINTTL(env.lbt.scr3, LoongArchCPU),
VMSTATE_UINT32(env.lbt.eflags, LoongArchCPU),
VMSTATE_UINT32(env.lbt.ftop, LoongArchCPU),
VMSTATE_END_OF_LIST()
@@ -146,8 +146,8 @@ static const VMStateDescription vmstate_tlb_entry =3D {
.minimum_version_id =3D 0,
.fields =3D (const VMStateField[]) {
VMSTATE_UINT64(tlb_misc, LoongArchTLB),
- VMSTATE_UINT64(tlb_entry0, LoongArchTLB),
- VMSTATE_UINT64(tlb_entry1, LoongArchTLB),
+ VMSTATE_UINTTL(tlb_entry0, LoongArchTLB),
+ VMSTATE_UINTTL(tlb_entry1, LoongArchTLB),
VMSTATE_END_OF_LIST()
}
};
@@ -175,65 +175,65 @@ const VMStateDescription vmstate_loongarch_cpu =3D {
VMSTATE_UINTTL(env.pc, LoongArchCPU),
=20
/* Remaining CSRs */
- VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
- VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
- VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
- VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
+ VMSTATE_UINTTL(env.CSR_CRMD, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PRMD, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_EUEN, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_MISC, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_ECFG, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_ESTAT, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_ERA, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_BADV, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_BADI, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_EENTRY, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBIDX, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBEHI, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBELO0, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBELO1, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_ASID, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PGDL, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PGDH, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PGD, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PWCL, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PWCH, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_STLBPS, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_RVACFG, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PRCFG1, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PRCFG2, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_PRCFG3, LoongArchCPU),
+ VMSTATE_UINTTL_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
+ VMSTATE_UINTTL(env.CSR_TID, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TCFG, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TVAL, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_CNTC, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TICLR, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_LLBCTL, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_IMPCTL1, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_IMPCTL2, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBRENTRY, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBRBADV, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBRERA, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBRSAVE, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBRELO0, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBRELO1, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBREHI, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_TLBRPRMD, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_MERRCTL, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_MERRINFO1, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_MERRINFO2, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_MERRENTRY, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_MERRERA, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_MERRSAVE, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_CTAG, LoongArchCPU),
+ VMSTATE_UINTTL_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
=20
/* Debug CSRs */
- VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
- VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_DBG, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_DERA, LoongArchCPU),
+ VMSTATE_UINTTL(env.CSR_DSAVE, LoongArchCPU),
=20
VMSTATE_UINT64(kvm_state_counter, LoongArchCPU),
/* PV steal time */
- VMSTATE_UINT64(env.stealtime.guest_addr, LoongArchCPU),
+ VMSTATE_UINTTL(env.stealtime.guest_addr, LoongArchCPU),
=20
VMSTATE_END_OF_LIST()
},
--=20
2.43.0