From nobody Sun Apr 6 22:27:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=syntacore.com ARC-Seal: i=1; a=rsa-sha256; t=1735130334; cv=none; d=zohomail.com; s=zohoarc; b=GBZ94VEvlU8gt4YAsBw+Pxngg2mcrUcExAeSURljaUVuKLj3XLv/Zu0rsmh7yDHLb3wkleAJAI1lFw6AD4wuPyhMsXyIMERg9m4VtmO8W4KW+tC04IwOz143G+nPF0UNO0QhdOvyNiDnXnkM7RpB07svnzGv71W4JR6exPU9ygY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1735130334; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pHaxb9Bw6SAt+eDqP7iVb05eLRvGqYUfW5Rr1Sj1opI=; b=DYUucmBkXr6p9jQTygHb0pl0q+weAadiftmPpeqquP2axAer88SBJk2Fzva0KX9YgXky6JXSUiwdYfJqP0nW6opCQwD6t/KAKY6BZkr3jLAUP5gzQqY6HB+Ul9Xyejjmyj5wJmyn8dTID8xc39M7s2bZ0cdcYnoVyxrK5jjOZpk= ARC-Authentication-Results: i=1; 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Wed, 25 Dec 2024 15:37:35 +0300 (MSK) Received: from S-SC-EXCH-01.corp.syntacore.com (mail.syntacore.com [10.76.202.20]) by pmg.syntacore.com (Proxmox) with ESMTPS id ECE64B412D4; Wed, 25 Dec 2024 15:37:34 +0300 (MSK) Received: from VirtualBox.corp.yadro.com (172.22.3.83) by S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 25 Dec 2024 15:36:41 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; h=cc:cc:content-transfer-encoding:content-type:content-type :date:from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=m; bh=pHaxb9Bw6SAt+eDqP7iVb05 eLRvGqYUfW5Rr1Sj1opI=; b=PZy0ottuxrSw6oENWxEREx3ACGtH513UHwjjU1k Rv0xnan5HkkDs0Z6hnoJ9/tdBYzkTwaY1koAMQkkcjOinTFovlr04KpQdSggZgwI mNc74Z0+K8Q9zrLEqzg0JF12Dd5qtPT23hhOUQNm7G8Psj4rjij4H7LWbCMaQCWo de3mXHNcAMSeDnIS4OwRW1r553MP3reBmV1VismqaMYLvssXd/3IfRg5ebEqpEGU yBNK4sA0rakeid3x7nwLZmQsR0V+0XpPAKMSgnpq7JaN3FNJTNSWek16vI/zvv3A n/84p8WcF8nOTF3cJg42000nZseIKI3sBLQVyoSf0gL0v0g== From: Ivan Klokov To: CC: , , , , , , , , , , Ivan Klokov Subject: [PATCH v8 1/2] target/riscv: Add RISC-V CSR qtest support Date: Wed, 25 Dec 2024 15:37:17 +0300 Message-ID: <20241225123718.45991-2-ivan.klokov@syntacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241225123718.45991-1-ivan.klokov@syntacore.com> References: <20241225123718.45991-1-ivan.klokov@syntacore.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.22.3.83] X-ClientProxiedBy: S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) To S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.249.69.228; envelope-from=ivan.klokov@syntacore.com; helo=pmg.syntacore.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1735130335524116600 Content-Type: text/plain; charset="utf-8" The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov Acked-by: Fabiano Rosas Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- hw/riscv/riscv_hart.c | 56 ++++++++++++++++++++++++++++++++++++++++++ tests/qtest/libqtest.c | 27 ++++++++++++++++++++ tests/qtest/libqtest.h | 14 +++++++++++ 3 files changed, 97 insertions(+) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index bc9ffdd2d4..b8151682c0 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -22,6 +22,9 @@ #include "qapi/error.h" #include "qemu/module.h" #include "system/reset.h" +#include "qemu/cutils.h" +#include "sysemu/qtest.h" +#include "sysemu/reset.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" #include "hw/qdev-properties.h" @@ -41,6 +44,55 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } =20 +#ifndef CONFIG_USER_ONLY +static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) +{ + RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(cpu_num)); + CPURISCVState *env =3D &cpu->env; + + int ret =3D RISCV_EXCP_NONE; + if (strcmp(cmd, "get_csr") =3D=3D 0) { + ret =3D riscv_csrr(env, csrno, (target_ulong *)val); + } else if (strcmp(cmd, "set_csr") =3D=3D 0) { + ret =3D riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, + MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + } + + g_assert(ret =3D=3D RISCV_EXCP_NONE); +} + +static bool csr_qtest_callback(CharBackend *chr, gchar **words) +{ + if (strcmp(words[0], "csr") =3D=3D 0) { + + uint64_t cpu; + uint64_t val; + int rc, csr; + + rc =3D qemu_strtou64(words[2], NULL, 0, &cpu); + g_assert(rc =3D=3D 0); + rc =3D qemu_strtoi(words[3], NULL, 0, &csr); + g_assert(rc =3D=3D 0); + rc =3D qemu_strtou64(words[4], NULL, 0, &val); + g_assert(rc =3D=3D 0); + csr_call(words[1], cpu, csr, &val); + + qtest_send_prefix(chr); + qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val); + + return true; + } + + return false; +} + +static void riscv_cpu_register_csr_qtest_callback(void) +{ + static GOnce once; + g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback); +} +#endif + static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, char *cpu_type, Error **errp) { @@ -58,6 +110,10 @@ static void riscv_harts_realize(DeviceState *dev, Error= **errp) =20 s->harts =3D g_new0(RISCVCPU, s->num_harts); =20 +#ifndef CONFIG_USER_ONLY + riscv_cpu_register_csr_qtest_callback(); +#endif + for (n =3D 0; n < s->num_harts; n++) { if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { return; diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 8de5f1fde3..4bc9643aad 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1218,6 +1218,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char *= name, return 0; } =20 +static void qtest_rsp_csr(QTestState *s, uint64_t *val) +{ + gchar **args; + uint64_t ret; + int rc; + + args =3D qtest_rsp_args(s, 3); + + rc =3D qemu_strtou64(args[1], NULL, 16, &ret); + g_assert(rc =3D=3D 0); + rc =3D qemu_strtou64(args[2], NULL, 16, val); + g_assert(rc =3D=3D 0); + + g_strfreev(args); +} + +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + uint64_t *val) +{ + qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n", + name, cpu, csr, *val); + + qtest_rsp_csr(s, val); + return 0; +} + void qtest_add_func(const char *str, void (*fn)(void)) { gchar *path =3D g_strdup_printf("/%s/%s", qtest_get_arch(), str); diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index f23d80e9e5..cd35e11d4c 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -600,6 +600,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *na= me, uint32_t nargs, uint64_t args, uint32_t nret, uint64_t ret); =20 +/** + * qtest_csr_call: + * @s: #QTestState instance to operate on. + * @name: name of the command to call. + * @cpu: hart number. + * @csr: CSR number. + * @val: Value for reading/writing. + * + * Call an RISC-V CSR read/write function + */ +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + unsigned long *val); + /** * qtest_bufread: * @s: #QTestState instance to operate on. --=20 2.34.1 From nobody Sun Apr 6 22:27:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 25 Dec 2024 15:37:36 +0300 (MSK) Received: from S-SC-EXCH-01.corp.syntacore.com (exchange.syntacore.com [10.76.202.20]) by pmg.syntacore.com (Proxmox) with ESMTPS id 5B686B412D4; Wed, 25 Dec 2024 15:37:36 +0300 (MSK) Received: from VirtualBox.corp.yadro.com (172.22.3.83) by S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 25 Dec 2024 15:36:42 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; h=cc:cc:content-transfer-encoding:content-type:content-type :date:from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=m; bh=HhEb5OGThDap061IAiGTEWz 6cH1TOOlieuqHwg3ZsEs=; b=c5DAwmuRpG4h1eIhJc/ftRYG9xZBKw3RT/SWrlF GB6m6jWoapL2l8OPF/BFM3H0NNNQCsGDBWNTk8i6wZlG7cFs7eWOQRbseKuPssin GsEp+7/sVggbufGXg466m63Y8a+DayztQiqWoTk2Cd9OHwuyXjNxFVyEMSF6HCc0 g3IEeMovX09kASGraFOWhpxGaKMAg6tTcjRv1MGTaEttVdncRlStVSObaAAY//vZ NnJK1gZkRCPewm+BsHwbpeI+9Ww8p2ZVPjnR27hItYDrcuN94qWBCDQQH1Va35zu bMhb1xjHkdzH0JCEsuj2oHa3HQue+WUq40eL+zRpNZidL9Q== From: Ivan Klokov To: CC: , , , , , , , , , , Ivan Klokov Subject: [PATCH v8 2/2] tests/qtest: QTest example for RISC-V CSR register Date: Wed, 25 Dec 2024 15:37:18 +0300 Message-ID: <20241225123718.45991-3-ivan.klokov@syntacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241225123718.45991-1-ivan.klokov@syntacore.com> References: <20241225123718.45991-1-ivan.klokov@syntacore.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.22.3.83] X-ClientProxiedBy: S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) To S-SC-EXCH-01.corp.syntacore.com (10.76.202.20) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.249.69.228; envelope-from=ivan.klokov@syntacore.com; helo=pmg.syntacore.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1735130333576116600 Content-Type: text/plain; charset="utf-8" Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov Reviewed-by: Fabiano Rosas Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- tests/qtest/meson.build | 2 +- tests/qtest/riscv-csr-test.c | 56 ++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/riscv-csr-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c5a70021c5..7eb1199d91 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -273,7 +273,7 @@ qtests_s390x =3D \ qtests_riscv32 =3D \ (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) =20 -qtests_riscv64 =3D \ +qtests_riscv64 =3D ['riscv-csr-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) =20 qos_test_ss =3D ss.source_set() diff --git a/tests/qtest/riscv-csr-test.c b/tests/qtest/riscv-csr-test.c new file mode 100644 index 0000000000..ff5c29e6c6 --- /dev/null +++ b/tests/qtest/riscv-csr-test.c @@ -0,0 +1,56 @@ +/* + * QTest testcase for RISC-V CSRs + * + * Copyright (c) 2024 Syntacore. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define CSR_MVENDORID 0xf11 +#define CSR_MISELECT 0x350 + +static void run_test_csr(void) +{ + uint64_t res; + uint64_t val =3D 0; + + QTestState *qts =3D qtest_init("-machine virt -cpu veyron-v1"); + + res =3D qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val); + + g_assert_cmpint(res, =3D=3D, 0); + g_assert_cmpint(val, =3D=3D, 0x61f); + + val =3D 0xff; + res =3D qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, =3D=3D, 0); + + val =3D 0; + res =3D qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, =3D=3D, 0); + g_assert_cmpint(val, =3D=3D, 0xff); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/cpu/csr", run_test_csr); + + return g_test_run(); +} --=20 2.34.1