From nobody Sun Apr 6 22:38:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735094485077865.3224060624082; Tue, 24 Dec 2024 18:41:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHK3-0007TG-Og; Tue, 24 Dec 2024 21:40:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tQHK1-0007RA-7V for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:29 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHJx-0000Xw-JS for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:28 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxIK+NcGtnKUBaAA--.22150S3; Wed, 25 Dec 2024 10:40:13 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx3sWJcGtnJV0IAA--.35957S3; Wed, 25 Dec 2024 10:40:12 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , ghy <2247883756@qq.com>, Guo Hongyu , Xianglai Li Subject: [PULL 1/6] target/loongarch: Fix vldi inst Date: Wed, 25 Dec 2024 10:40:03 +0800 Message-Id: <20241225024008.486236-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241225024008.486236-1-maobibo@loongson.cn> References: <20241225024008.486236-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx3sWJcGtnJV0IAA--.35957S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_SBL_A=0.1 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1735094487826116600 Content-Type: text/plain; charset="utf-8" From: ghy <2247883756@qq.com> Refer to the link below for a description of the vldi instructions: https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88 Fixed errors in vldi instruction implementation. Signed-off-by: Guo Hongyu Tested-by: Xianglai Li Signed-off-by: Xianglai Li Reviewed-by: Bibo Mao Signed-off-by: Bibo Mao --- target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loong= arch/tcg/insn_trans/trans_vec.c.inc index 92b1d22e28..d317dfcc1c 100644 --- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc @@ -3480,7 +3480,7 @@ static uint64_t vldi_get_value(DisasContext *ctx, uin= t32_t imm) break; case 1: /* data: {2{16'0, imm[7:0], 8'0}} */ - data =3D (t << 24) | (t << 8); + data =3D (t << 40) | (t << 8); break; case 2: /* data: {2{8'0, imm[7:0], 16'0}} */ --=20 2.43.5 From nobody Sun Apr 6 22:38:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735094484977729.4238491055961; Tue, 24 Dec 2024 18:41:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHK4-0007TZ-JN; Tue, 24 Dec 2024 21:40:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tQHK1-0007RJ-AK; Tue, 24 Dec 2024 21:40:29 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHJy-0000YW-5n; Tue, 24 Dec 2024 21:40:29 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxL62OcGtnLUBaAA--.7334S3; Wed, 25 Dec 2024 10:40:14 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx3sWJcGtnJV0IAA--.35957S4; Wed, 25 Dec 2024 10:40:13 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao , qemu-stable@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 2/6] target/loongarch: Use actual operand size with vbsrl check Date: Wed, 25 Dec 2024 10:40:04 +0800 Message-Id: <20241225024008.486236-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241225024008.486236-1-maobibo@loongson.cn> References: <20241225024008.486236-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx3sWJcGtnJV0IAA--.35957S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1735094487994116600 Hardcoded 32 bytes is used for vbsrl emulation check, there is problem when options lsx=3Don,lasx=3Doff is used for vbsrl.v instruction in TCG mode. It injects LASX exception rather LSX exception. Here actual operand size is used. Cc: qemu-stable@nongnu.org Fixes: df97f338076 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve= ") Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loong= arch/tcg/insn_trans/trans_vec.c.inc index d317dfcc1c..dff92772ad 100644 --- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc @@ -5126,7 +5126,7 @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a= , uint32_t oprsz) { int i, ofs; =20 - if (!check_vec(ctx, 32)) { + if (!check_vec(ctx, oprsz)) { return true; } =20 --=20 2.43.5 From nobody Sun Apr 6 22:38:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735094527344625.119474055441; Tue, 24 Dec 2024 18:42:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHK4-0007TX-De; Tue, 24 Dec 2024 21:40:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tQHK1-0007RW-Jy for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:29 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHJx-0000Xt-Jb for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:29 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxCeGOcGtnL0BaAA--.46400S3; Wed, 25 Dec 2024 10:40:14 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx3sWJcGtnJV0IAA--.35957S5; Wed, 25 Dec 2024 10:40:14 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao Subject: [PULL 3/6] hw/loongarch/virt: Create fdt table on machine creation done notification Date: Wed, 25 Dec 2024 10:40:05 +0800 Message-Id: <20241225024008.486236-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241225024008.486236-1-maobibo@loongson.cn> References: <20241225024008.486236-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx3sWJcGtnJV0IAA--.35957S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1735094528031116600 Content-Type: text/plain; charset="utf-8" The same with ACPI table, fdt table is created on machine done notification. Some objects like CPU objects can be created with cold-plug method with command such as -smp x, -device la464-loongarch-cpu, so all objects finish to create when machine is done. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/loongarch/virt.c | 103 ++++++++++++++++++++++++-------------------- 1 file changed, 57 insertions(+), 46 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 3a905cf71d..266f291509 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -615,12 +615,67 @@ static void virt_build_smbios(LoongArchVirtMachineSta= te *lvms) } } =20 +static void virt_fdt_setup(LoongArchVirtMachineState *lvms) +{ + MachineState *machine =3D MACHINE(lvms); + uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_ph= andle; + int i; + + create_fdt(lvms); + fdt_add_cpu_nodes(lvms); + fdt_add_memory_nodes(machine); + fdt_add_fw_cfg_node(lvms); + fdt_add_flash_node(lvms); + + /* Add cpu interrupt-controller */ + fdt_add_cpuic_node(lvms, &cpuintc_phandle); + /* Add Extend I/O Interrupt Controller node */ + fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle); + /* Add PCH PIC node */ + fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle); + /* Add PCH MSI node */ + fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle); + /* Add pcie node */ + fdt_add_pcie_node(lvms, &pch_pic_phandle, &pch_msi_phandle); + + /* + * Create uart fdt node in reverse order so that they appear + * in the finished device tree lowest address first + */ + for (i =3D VIRT_UART_COUNT; i-- > 0;) { + hwaddr base =3D VIRT_UART_BASE + i * VIRT_UART_SIZE; + int irq =3D VIRT_UART_IRQ + i - VIRT_GSI_BASE; + fdt_add_uart_node(lvms, &pch_pic_phandle, base, irq, i =3D=3D 0); + } + + fdt_add_rtc_node(lvms, &pch_pic_phandle); + fdt_add_ged_reset(lvms); + platform_bus_add_all_fdt_nodes(machine->fdt, "/platic", + VIRT_PLATFORM_BUS_BASEADDRESS, + VIRT_PLATFORM_BUS_SIZE, + VIRT_PLATFORM_BUS_IRQ); + + /* + * Since lowmem region starts from 0 and Linux kernel legacy start add= ress + * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer + * access. FDT size limit with 1 MiB. + * Put the FDT into the memory map as a ROM image: this will ensure + * the FDT is copied again upon reset, even if addr points into RAM. + */ + qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size); + rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE, + &address_space_memory); + qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, + rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size= )); +} + static void virt_done(Notifier *notifier, void *data) { LoongArchVirtMachineState *lvms =3D container_of(notifier, LoongArchVirtMachineState, machine_d= one); virt_build_smbios(lvms); loongarch_acpi_setup(lvms); + virt_fdt_setup(lvms); } =20 static void virt_powerdown_req(Notifier *notifier, void *opaque) @@ -699,9 +754,7 @@ static DeviceState *create_platform_bus(DeviceState *pc= h_pic) } =20 static void virt_devices_init(DeviceState *pch_pic, - LoongArchVirtMachineState *lvms, - uint32_t *pch_pic_phandle, - uint32_t *pch_msi_phandle) + LoongArchVirtMachineState *lvms) { MachineClass *mc =3D MACHINE_GET_CLASS(lvms); DeviceState *gpex_dev; @@ -747,9 +800,6 @@ static void virt_devices_init(DeviceState *pch_pic, gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); } =20 - /* Add pcie node */ - fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle); - /* * Create uart fdt node in reverse order so that they appear * in the finished device tree lowest address first @@ -760,7 +810,6 @@ static void virt_devices_init(DeviceState *pch_pic, serial_mm_init(get_system_memory(), base, 0, qdev_get_gpio_in(pch_pic, irq), 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN); - fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i =3D=3D 0); } =20 /* Network init */ @@ -774,8 +823,6 @@ static void virt_devices_init(DeviceState *pch_pic, sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, qdev_get_gpio_in(pch_pic, VIRT_RTC_IRQ - VIRT_GSI_BASE)); - fdt_add_rtc_node(lvms, pch_pic_phandle); - fdt_add_ged_reset(lvms); =20 /* acpi ged */ lvms->acpi_ged =3D create_acpi_ged(pch_pic, lvms); @@ -793,7 +840,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) CPULoongArchState *env; CPUState *cpu_state; int cpu, pin, i, start, num; - uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_ph= andle; =20 /* * Extended IRQ model. @@ -850,9 +896,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); =20 - /* Add cpu interrupt-controller */ - fdt_add_cpuic_node(lvms, &cpuintc_phandle); - for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { cpu_state =3D qemu_get_cpu(cpu); cpudev =3D DEVICE(cpu_state); @@ -891,9 +934,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) } } =20 - /* Add Extend I/O Interrupt Controller node */ - fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle); - pch_pic =3D qdev_new(TYPE_LOONGARCH_PIC); num =3D VIRT_PCH_PIC_IRQ_NUM; qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); @@ -913,9 +953,6 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); } =20 - /* Add PCH PIC node */ - fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle); - pch_msi =3D qdev_new(TYPE_LOONGARCH_PCH_MSI); start =3D num; num =3D EXTIOI_IRQS - start; @@ -930,10 +967,7 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) qdev_get_gpio_in(extioi, i + start)); } =20 - /* Add PCH MSI node */ - fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle); - - virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle); + virt_devices_init(pch_pic, lvms); } =20 static void virt_firmware_init(LoongArchVirtMachineState *lvms) @@ -1151,8 +1185,6 @@ static void virt_init(MachineState *machine) cpu_model =3D LOONGARCH_CPU_TYPE_NAME("la464"); } =20 - create_fdt(lvms); - /* Create IOCSR space */ memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, machine, "iocsr", UINT64_MAX); @@ -1171,8 +1203,6 @@ static void virt_init(MachineState *machine) lacpu =3D LOONGARCH_CPU(cpu); lacpu->phy_id =3D machine->possible_cpus->cpus[i].arch_id; } - fdt_add_cpu_nodes(lvms); - fdt_add_memory_nodes(machine); fw_cfg_add_memory(machine); =20 /* Node0 memory */ @@ -1224,34 +1254,15 @@ static void virt_init(MachineState *machine) memmap_table, sizeof(struct memmap_entry) * (memmap_entries)); } - fdt_add_fw_cfg_node(lvms); - fdt_add_flash_node(lvms); =20 /* Initialize the IO interrupt subsystem */ virt_irq_init(lvms); - platform_bus_add_all_fdt_nodes(machine->fdt, "/platic", - VIRT_PLATFORM_BUS_BASEADDRESS, - VIRT_PLATFORM_BUS_SIZE, - VIRT_PLATFORM_BUS_IRQ); lvms->machine_done.notify =3D virt_done; qemu_add_machine_init_done_notifier(&lvms->machine_done); /* connect powerdown request */ lvms->powerdown_notifier.notify =3D virt_powerdown_req; qemu_register_powerdown_notifier(&lvms->powerdown_notifier); =20 - /* - * Since lowmem region starts from 0 and Linux kernel legacy start add= ress - * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer - * access. FDT size limit with 1 MiB. - * Put the FDT into the memory map as a ROM image: this will ensure - * the FDT is copied again upon reset, even if addr points into RAM. - */ - qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size); - rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE, - &address_space_memory); - qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, - rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size= )); - lvms->bootinfo.ram_size =3D ram_size; loongarch_load_kernel(machine, &lvms->bootinfo); } --=20 2.43.5 From nobody Sun Apr 6 22:38:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17350945307151015.1844279127204; Tue, 24 Dec 2024 18:42:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHK2-0007SY-PD; Tue, 24 Dec 2024 21:40:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tQHK0-0007Qx-WC for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:29 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHJx-0000Y4-K0 for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:28 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxDeOPcGtnMkBaAA--.45566S3; Wed, 25 Dec 2024 10:40:15 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx3sWJcGtnJV0IAA--.35957S6; Wed, 25 Dec 2024 10:40:14 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao Subject: [PULL 4/6] hw/loongarch/virt: Improve fdt table creation for CPU object Date: Wed, 25 Dec 2024 10:40:06 +0800 Message-Id: <20241225024008.486236-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241225024008.486236-1-maobibo@loongson.cn> References: <20241225024008.486236-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx3sWJcGtnJV0IAA--.35957S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1735094532067116600 Content-Type: text/plain; charset="utf-8" For CPU object, possible_cpu_arch_ids() function is used rather than smp.cpus. With command -smp x, -device la464-loongarch-cpu, smp.cpus is not accurate for all possible CPU objects, possible_cpu_arch_ids() is used here. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- hw/loongarch/virt.c | 39 +++++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 266f291509..99594a13a0 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -365,26 +365,35 @@ static void create_fdt(LoongArchVirtMachineState *lvm= s) static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms) { int num; - const MachineState *ms =3D MACHINE(lvms); - int smp_cpus =3D ms->smp.cpus; + MachineState *ms =3D MACHINE(lvms); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *possible_cpus; + LoongArchCPU *cpu; + CPUState *cs; + char *nodename, *map_path; =20 qemu_fdt_add_subnode(ms->fdt, "/cpus"); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); =20 /* cpu nodes */ - for (num =3D smp_cpus - 1; num >=3D 0; num--) { - char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); - LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num)); - CPUState *cs =3D CPU(cpu); + possible_cpus =3D mc->possible_cpu_arch_ids(ms); + for (num =3D 0; num < possible_cpus->len; num++) { + cs =3D possible_cpus->cpus[num].cpu; + if (cs =3D=3D NULL) { + continue; + } + + nodename =3D g_strdup_printf("/cpus/cpu@%d", num); + cpu =3D LOONGARCH_CPU(cs); =20 qemu_fdt_add_subnode(ms->fdt, nodename); qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", cpu->dtb_compatible); - if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + if (possible_cpus->cpus[num].props.has_node_id) { qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", - ms->possible_cpus->cpus[cs->cpu_index].props.node_id); + possible_cpus->cpus[num].props.node_id); } qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", @@ -394,11 +403,13 @@ static void fdt_add_cpu_nodes(const LoongArchVirtMach= ineState *lvms) =20 /*cpu map */ qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); + for (num =3D 0; num < possible_cpus->len; num++) { + cs =3D possible_cpus->cpus[num].cpu; + if (cs =3D=3D NULL) { + continue; + } =20 - for (num =3D smp_cpus - 1; num >=3D 0; num--) { - char *cpu_path =3D g_strdup_printf("/cpus/cpu@%d", num); - char *map_path; - + nodename =3D g_strdup_printf("/cpus/cpu@%d", num); if (ms->smp.threads > 1) { map_path =3D g_strdup_printf( "/cpus/cpu-map/socket%d/core%d/thread%d", @@ -412,10 +423,10 @@ static void fdt_add_cpu_nodes(const LoongArchVirtMach= ineState *lvms) num % ms->smp.cores); } qemu_fdt_add_path(ms->fdt, map_path); - qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); + qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", nodename); =20 g_free(map_path); - g_free(cpu_path); + g_free(nodename); } } =20 --=20 2.43.5 From nobody Sun Apr 6 22:38:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735094513142254.745372062015; Tue, 24 Dec 2024 18:41:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHK3-0007T1-JP; Tue, 24 Dec 2024 21:40:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tQHK1-0007RK-AN for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:29 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHJx-0000YC-KD for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:29 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxTOKQcGtnNEBaAA--.45437S3; Wed, 25 Dec 2024 10:40:16 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx3sWJcGtnJV0IAA--.35957S7; Wed, 25 Dec 2024 10:40:15 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao Subject: [PULL 5/6] target/loongarch: Use auto method with LSX feature Date: Wed, 25 Dec 2024 10:40:07 +0800 Message-Id: <20241225024008.486236-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241225024008.486236-1-maobibo@loongson.cn> References: <20241225024008.486236-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx3sWJcGtnJV0IAA--.35957S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1735094514941116600 Content-Type: text/plain; charset="utf-8" Like LBT feature, add type OnOffAuto for LSX feature setting. Also add LSX feature detection with new VM ioctl command, fallback to old method if it is not supported. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- target/loongarch/cpu.c | 38 +++++++++++++++------------ target/loongarch/cpu.h | 2 ++ target/loongarch/kvm/kvm.c | 54 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 17 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5bc8720d1..4f425df9f3 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -379,6 +379,7 @@ static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; + uint32_t data =3D 0; int i; =20 for (i =3D 0; i < 21; i++) { @@ -388,7 +389,6 @@ static void loongarch_la464_initfn(Object *obj) cpu->dtb_compatible =3D "loongarch,Loongson-3A5000"; env->cpucfg[0] =3D 0x14c010; /* PRID */ =20 - uint32_t data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 2); data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); @@ -477,7 +477,7 @@ static void loongarch_la132_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; - + uint32_t data =3D 0; int i; =20 for (i =3D 0; i < 21; i++) { @@ -487,7 +487,6 @@ static void loongarch_la132_initfn(Object *obj) cpu->dtb_compatible =3D "loongarch,Loongson-1C103"; env->cpucfg[0] =3D 0x148042; /* PRID */ =20 - uint32_t data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); @@ -615,27 +614,30 @@ static void loongarch_cpu_realizefn(DeviceState *dev,= Error **errp) =20 static bool loongarch_get_lsx(Object *obj, Error **errp) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - bool ret; - - if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { - ret =3D true; - } else { - ret =3D false; - } - return ret; + return LOONGARCH_CPU(obj)->lsx !=3D ON_OFF_AUTO_OFF; } =20 static void loongarch_set_lsx(Object *obj, bool value, Error **errp) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; =20 - if (value) { - cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX= , 1); - } else { - cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX= , 0); - cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LAS= X, 0); + cpu->lsx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + if (kvm_enabled()) { + /* kvm feature detection in function kvm_arch_init_vcpu */ + return; } + + /* LSX feature detection in TCG mode */ + val =3D cpu->env.cpucfg[2]; + if (cpu->lsx =3D=3D ON_OFF_AUTO_ON) { + if (FIELD_EX32(val, CPUCFG2, LSX) =3D=3D 0) { + error_setg(errp, "Failed to enable LSX in TCG mode"); + return; + } + } + + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LSX, value); } =20 static bool loongarch_get_lasx(Object *obj, Error **errp) @@ -693,6 +695,7 @@ void loongarch_cpu_post_init(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); =20 + cpu->lsx =3D ON_OFF_AUTO_AUTO; object_property_add_bool(obj, "lsx", loongarch_get_lsx, loongarch_set_lsx); object_property_add_bool(obj, "lasx", loongarch_get_lasx, @@ -713,6 +716,7 @@ void loongarch_cpu_post_init(Object *obj) =20 } else { cpu->lbt =3D ON_OFF_AUTO_OFF; + cpu->pmu =3D ON_OFF_AUTO_OFF; } } =20 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 86c86c6c95..5bddf72c22 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -283,6 +283,7 @@ typedef struct LoongArchTLB LoongArchTLB; #endif =20 enum loongarch_features { + LOONGARCH_FEATURE_LSX, LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ LOONGARCH_FEATURE_PMU, }; @@ -404,6 +405,7 @@ struct ArchCPU { uint32_t phy_id; OnOffAuto lbt; OnOffAuto pmu; + OnOffAuto lsx; =20 /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 3c86f5ffb9..eeedf3175e 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -798,8 +798,35 @@ static bool kvm_feature_supported(CPUState *cs, enum l= oongarch_features feature) { int ret; struct kvm_device_attr attr; + uint64_t val; =20 switch (feature) { + case LOONGARCH_FEATURE_LSX: + attr.group =3D KVM_LOONGARCH_VM_FEAT_CTRL; + attr.attr =3D KVM_LOONGARCH_VM_FEAT_LSX; + ret =3D kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); + if (ret =3D=3D 0) { + return true; + } + + /* Fallback to old kernel detect interface */ + val =3D 0; + attr.group =3D KVM_LOONGARCH_VCPU_CPUCFG; + /* Cpucfg2 */ + attr.attr =3D 2; + attr.addr =3D (uint64_t)&val; + ret =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr); + if (!ret) { + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr); + if (ret) { + return false; + } + + ret =3D FIELD_EX32((uint32_t)val, CPUCFG2, LSX); + return (ret !=3D 0); + } + return false; + case LOONGARCH_FEATURE_LBT: /* * Return all if all the LBT features are supported such as: @@ -829,6 +856,28 @@ static bool kvm_feature_supported(CPUState *cs, enum l= oongarch_features feature) return false; } =20 +static int kvm_cpu_check_lsx(CPUState *cs, Error **errp) +{ + CPULoongArchState *env =3D cpu_env(cs); + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + bool kvm_supported; + + kvm_supported =3D kvm_feature_supported(cs, LOONGARCH_FEATURE_LSX); + env->cpucfg[2] =3D FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 0); + if (cpu->lsx =3D=3D ON_OFF_AUTO_ON) { + if (kvm_supported) { + env->cpucfg[2] =3D FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1); + } else { + error_setg(errp, "'lsx' feature not supported by KVM on this h= ost"); + return -ENOTSUP; + } + } else if ((cpu->lsx =3D=3D ON_OFF_AUTO_AUTO) && kvm_supported) { + env->cpucfg[2] =3D FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1); + } + + return 0; +} + static int kvm_cpu_check_lbt(CPUState *cs, Error **errp) { CPULoongArchState *env =3D cpu_env(cs); @@ -889,6 +938,11 @@ int kvm_arch_init_vcpu(CPUState *cs) brk_insn =3D val; } =20 + ret =3D kvm_cpu_check_lsx(cs, &local_err); + if (ret < 0) { + error_report_err(local_err); + } + ret =3D kvm_cpu_check_lbt(cs, &local_err); if (ret < 0) { error_report_err(local_err); --=20 2.43.5 From nobody Sun Apr 6 22:38:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1735094531090706.1517309454516; Tue, 24 Dec 2024 18:42:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHK6-0007Td-7c; Tue, 24 Dec 2024 21:40:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tQHJz-0007Qh-QO for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:27 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tQHJw-0000YN-Kp for qemu-devel@nongnu.org; Tue, 24 Dec 2024 21:40:27 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxCeGRcGtnNkBaAA--.46402S3; Wed, 25 Dec 2024 10:40:17 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx3sWJcGtnJV0IAA--.35957S8; Wed, 25 Dec 2024 10:40:16 +0800 (CST) From: Bibo Mao To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Song Gao Subject: [PULL 6/6] target/loongarch: Use auto method with LASX feature Date: Wed, 25 Dec 2024 10:40:08 +0800 Message-Id: <20241225024008.486236-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241225024008.486236-1-maobibo@loongson.cn> References: <20241225024008.486236-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx3sWJcGtnJV0IAA--.35957S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1735094532171116600 Content-Type: text/plain; charset="utf-8" Like LSX feature, add type OnOffAuto for LASX feature setting. Signed-off-by: Bibo Mao Reviewed-by: Bibo Mao --- target/loongarch/cpu.c | 50 +++++++++++++++++++++++------------ target/loongarch/cpu.h | 2 ++ target/loongarch/kvm/kvm.c | 53 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 16 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 4f425df9f3..84b2fda3be 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -623,6 +623,14 @@ static void loongarch_set_lsx(Object *obj, bool value,= Error **errp) uint32_t val; =20 cpu->lsx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + if (cpu->lsx =3D=3D ON_OFF_AUTO_OFF) { + cpu->lasx =3D ON_OFF_AUTO_OFF; + if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { + error_setg(errp, "Failed to disable LSX since LASX is enabled"= ); + return; + } + } + if (kvm_enabled()) { /* kvm feature detection in function kvm_arch_init_vcpu */ return; @@ -635,6 +643,9 @@ static void loongarch_set_lsx(Object *obj, bool value, = Error **errp) error_setg(errp, "Failed to enable LSX in TCG mode"); return; } + } else { + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, 0); + val =3D cpu->env.cpucfg[2]; } =20 cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LSX, value); @@ -642,29 +653,35 @@ static void loongarch_set_lsx(Object *obj, bool value= , Error **errp) =20 static bool loongarch_get_lasx(Object *obj, Error **errp) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - bool ret; - - if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) { - ret =3D true; - } else { - ret =3D false; - } - return ret; + return LOONGARCH_CPU(obj)->lasx !=3D ON_OFF_AUTO_OFF; } =20 static void loongarch_set_lasx(Object *obj, bool value, Error **errp) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; =20 - if (value) { - if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) { - cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2,= LSX, 1); - } - cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LAS= X, 1); - } else { - cpu->env.cpucfg[2] =3D FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LAS= X, 0); + cpu->lasx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + if ((cpu->lsx =3D=3D ON_OFF_AUTO_OFF) && (cpu->lasx =3D=3D ON_OFF_AUTO= _ON)) { + error_setg(errp, "Failed to enable LASX since lSX is disabled"); + return; + } + + if (kvm_enabled()) { + /* kvm feature detection in function kvm_arch_init_vcpu */ + return; } + + /* LASX feature detection in TCG mode */ + val =3D cpu->env.cpucfg[2]; + if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { + if (FIELD_EX32(val, CPUCFG2, LASX) =3D=3D 0) { + error_setg(errp, "Failed to enable LASX in TCG mode"); + return; + } + } + + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); } =20 static bool loongarch_get_lbt(Object *obj, Error **errp) @@ -696,6 +713,7 @@ void loongarch_cpu_post_init(Object *obj) LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); =20 cpu->lsx =3D ON_OFF_AUTO_AUTO; + cpu->lasx =3D ON_OFF_AUTO_AUTO; object_property_add_bool(obj, "lsx", loongarch_get_lsx, loongarch_set_lsx); object_property_add_bool(obj, "lasx", loongarch_get_lasx, diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 5bddf72c22..8eee49a984 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -284,6 +284,7 @@ typedef struct LoongArchTLB LoongArchTLB; =20 enum loongarch_features { LOONGARCH_FEATURE_LSX, + LOONGARCH_FEATURE_LASX, LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ LOONGARCH_FEATURE_PMU, }; @@ -406,6 +407,7 @@ struct ArchCPU { OnOffAuto lbt; OnOffAuto pmu; OnOffAuto lsx; + OnOffAuto lasx; =20 /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index eeedf3175e..a3f55155b0 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -827,6 +827,32 @@ static bool kvm_feature_supported(CPUState *cs, enum l= oongarch_features feature) } return false; =20 + case LOONGARCH_FEATURE_LASX: + attr.group =3D KVM_LOONGARCH_VM_FEAT_CTRL; + attr.attr =3D KVM_LOONGARCH_VM_FEAT_LASX; + ret =3D kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr); + if (ret =3D=3D 0) { + return true; + } + + /* Fallback to old kernel detect interface */ + val =3D 0; + attr.group =3D KVM_LOONGARCH_VCPU_CPUCFG; + /* Cpucfg2 */ + attr.attr =3D 2; + attr.addr =3D (uint64_t)&val; + ret =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr); + if (!ret) { + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr); + if (ret) { + return false; + } + + ret =3D FIELD_EX32((uint32_t)val, CPUCFG2, LASX); + return (ret !=3D 0); + } + return false; + case LOONGARCH_FEATURE_LBT: /* * Return all if all the LBT features are supported such as: @@ -878,6 +904,28 @@ static int kvm_cpu_check_lsx(CPUState *cs, Error **err= p) return 0; } =20 +static int kvm_cpu_check_lasx(CPUState *cs, Error **errp) +{ + CPULoongArchState *env =3D cpu_env(cs); + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + bool kvm_supported; + + kvm_supported =3D kvm_feature_supported(cs, LOONGARCH_FEATURE_LASX); + env->cpucfg[2] =3D FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 0); + if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { + if (kvm_supported) { + env->cpucfg[2] =3D FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1= ); + } else { + error_setg(errp, "'lasx' feature not supported by KVM on host"= ); + return -ENOTSUP; + } + } else if ((cpu->lasx =3D=3D ON_OFF_AUTO_AUTO) && kvm_supported) { + env->cpucfg[2] =3D FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1); + } + + return 0; +} + static int kvm_cpu_check_lbt(CPUState *cs, Error **errp) { CPULoongArchState *env =3D cpu_env(cs); @@ -943,6 +991,11 @@ int kvm_arch_init_vcpu(CPUState *cs) error_report_err(local_err); } =20 + ret =3D kvm_cpu_check_lasx(cs, &local_err); + if (ret < 0) { + error_report_err(local_err); + } + ret =3D kvm_cpu_check_lbt(cs, &local_err); if (ret < 0) { error_report_err(local_err); --=20 2.43.5