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([71.212.144.252]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f2ee26fc22sm4165260a91.51.2024.12.19.20.11.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 20:11:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734667867; x=1735272667; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Y9RnxHpN0x96A+UA+qFx0eOiDNd9nU3BGhNBeQSd/Rg=; b=D3SizqZj5QjBT23cabkwuoVRwwYUlfoii6kzMCoxp5kJTUg5wGinVdRNk6VK14AwJt qYxy/FVYy/90BZs/eIPa6esIri1Fn8JuzLaeriyo1OqKOQpmt+w2wbwttfBKGBKFYZlU 3NlNGjLmRIKnIaPP0TlPkrS5LbD+OLhpkEUxJJSrzLGbdgx3OmGgIZ7nHT4xm7vE9ewc PZ6yMH3SD5OWkwGCWHC7KmD+7eJDWSmJ9eazmhqqgDJHxQbr7cobfSXyotOw0Hi0SzLe ChnHEKhHWH2UY2l6NDSz6NdW2S6Q3KiyTagMYj38k850w1yUxECjiI1DZl6Pmlro396K SFYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734667867; x=1735272667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y9RnxHpN0x96A+UA+qFx0eOiDNd9nU3BGhNBeQSd/Rg=; b=ktSwLajhOiexh6uaIruhGsis/+Eyx5NGjPWXPF56q/vUmU64in8BLSzTHMzX5YPOdC Pzh1A/bY34Ep66pfM+D7HeeEZev3AsrBWFfDgxSQkEHKTMCdByX97b3jRMadpTpwxgNE h2g/BA87sgp9JkYGQ8vxW+p3ISBkUk5ef5DaBxF7tjs38Mb9GV0S6J3M+L72+fVZXKJ0 IqyNs8gC7hhcdjovpWoVVnkhGGQw7h9kC9O/k+sb0lefS0m7KeC3k+IwlmfbwflmUXI7 uwi4siDcLWKW9UfBqTOBFZAG6E4vbJGNZ+RfGEsPfGLUG6osjN4B7TzSUMm+RoNY7Cjn vvbg== X-Gm-Message-State: AOJu0Yyv4RJwX8ZVNxTWY5smaACE3j74ZtvdyNZulEqXL2WOJ28K06o4 PPIv9yg18BVFEHudGK/1Q2oM4Tw1T5Y5B4mKFF7VloMX1lF1aaH3dxEYL2NpNWgn2axfZxtc4K8 o X-Gm-Gg: ASbGncuz5iLgT1Wfli7IUhUw5FugoBCeZ/kkilov0PpKzKXedpljRr0njZOCbZ15+ce 3rrwtO+cnmoQU1VPuNZlhzCsF5wZEKKyMUNR4Odry7/BNk2SjpTjSM9N7gLkk9d7Nl4Pme74UGO R8jtHfY5l8MQj+BjVa0WYWew75YCgPlwwmskjttdtIhKsvbdZHzLq57nUoIJHY0udyGtKk0vUlj OBi+r5ovzpJjPtSQsqPDawcapMpS8QohzWiesYITHl9mjjy/cMWK18zxD4mWWI= X-Google-Smtp-Source: AGHT+IGb9957OjpSfK5DpeQmJQVhPEoDu917eXQbfXzS6jGXJVLsMNWDZS42XZhPdbHigtlqjQH1Ng== X-Received: by 2002:a17:90b:3a43:b0:2ee:94a0:255c with SMTP id 98e67ed59e1d1-2f4536d25fcmr2140111a91.13.1734667866749; Thu, 19 Dec 2024 20:11:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/51] tcg/optimize: Split out fold_affected_mask Date: Thu, 19 Dec 2024 20:10:14 -0800 Message-ID: <20241220041104.53105-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241220041104.53105-1-richard.henderson@linaro.org> References: <20241220041104.53105-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1734668227834116600 Content-Type: text/plain; charset="utf-8" There are only a few logical operations which can compute an "affected" mask. Split out handling of this optimization to a separate function, only to be called when applicable. Remove the a_mask field from OptContext, as the mask is no longer stored anywhere. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- tcg/optimize.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 453e8c43bd..6757fe0036 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -64,7 +64,6 @@ typedef struct OptContext { QSIMPLEQ_HEAD(, MemCopyInfo) mem_free; =20 /* In flight values from optimization. */ - uint64_t a_mask; /* mask bit is 0 iff value identical to first input = */ uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */ uint64_t s_mask; /* mask of clrsb(value) bits */ TCGType type; @@ -1047,7 +1046,6 @@ static bool fold_const2_commutative(OptContext *ctx, = TCGOp *op) =20 static bool fold_masks(OptContext *ctx, TCGOp *op) { - uint64_t a_mask =3D ctx->a_mask; uint64_t z_mask =3D ctx->z_mask; uint64_t s_mask =3D ctx->s_mask; =20 @@ -1059,7 +1057,6 @@ static bool fold_masks(OptContext *ctx, TCGOp *op) * type changing opcodes. */ if (ctx->type =3D=3D TCG_TYPE_I32) { - a_mask =3D (int32_t)a_mask; z_mask =3D (int32_t)z_mask; s_mask |=3D MAKE_64BIT_MASK(32, 32); ctx->z_mask =3D z_mask; @@ -1069,6 +1066,19 @@ static bool fold_masks(OptContext *ctx, TCGOp *op) if (z_mask =3D=3D 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], 0); } + return false; +} + +/* + * An "affected" mask bit is 0 if and only if the result is identical + * to the first input. Thus if the entire mask is 0, the operation + * is equivalent to a copy. + */ +static bool fold_affected_mask(OptContext *ctx, TCGOp *op, uint64_t a_mask) +{ + if (ctx->type =3D=3D TCG_TYPE_I32) { + a_mask =3D (uint32_t)a_mask; + } if (a_mask =3D=3D 0) { return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); } @@ -1305,8 +1315,9 @@ static bool fold_and(OptContext *ctx, TCGOp *op) * Known-zeros does not imply known-ones. Therefore unless * arg2 is constant, we can't infer affected bits from it. */ - if (arg_is_const(op->args[2])) { - ctx->a_mask =3D z1 & ~z2; + if (arg_is_const(op->args[2]) && + fold_affected_mask(ctx, op, z1 & ~z2)) { + return true; } =20 return fold_masks(ctx, op); @@ -1331,7 +1342,9 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) */ if (arg_is_const(op->args[2])) { uint64_t z2 =3D ~arg_info(op->args[2])->z_mask; - ctx->a_mask =3D z1 & ~z2; + if (fold_affected_mask(ctx, op, z1 & ~z2)) { + return true; + } z1 &=3D z2; } ctx->z_mask =3D z1; @@ -1709,8 +1722,8 @@ static bool fold_extract(OptContext *ctx, TCGOp *op) =20 z_mask_old =3D arg_info(op->args[1])->z_mask; z_mask =3D extract64(z_mask_old, pos, len); - if (pos =3D=3D 0) { - ctx->a_mask =3D z_mask_old ^ z_mask; + if (pos =3D=3D 0 && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) { + return true; } ctx->z_mask =3D z_mask; ctx->s_mask =3D smask_from_zmask(z_mask); @@ -1777,8 +1790,8 @@ static bool fold_exts(OptContext *ctx, TCGOp *op) =20 ctx->z_mask =3D z_mask; ctx->s_mask =3D s_mask; - if (!type_change) { - ctx->a_mask =3D s_mask & ~s_mask_old; + if (!type_change && fold_affected_mask(ctx, op, s_mask & ~s_mask_old))= { + return true; } =20 return fold_masks(ctx, op); @@ -1819,8 +1832,8 @@ static bool fold_extu(OptContext *ctx, TCGOp *op) =20 ctx->z_mask =3D z_mask; ctx->s_mask =3D smask_from_zmask(z_mask); - if (!type_change) { - ctx->a_mask =3D z_mask_old ^ z_mask; + if (!type_change && fold_affected_mask(ctx, op, z_mask_old ^ z_mask)) { + return true; } return fold_masks(ctx, op); } @@ -2482,8 +2495,8 @@ static bool fold_sextract(OptContext *ctx, TCGOp *op) s_mask |=3D MAKE_64BIT_MASK(len, 64 - len); ctx->s_mask =3D s_mask; =20 - if (pos =3D=3D 0) { - ctx->a_mask =3D s_mask & ~s_mask_old; + if (pos =3D=3D 0 && fold_affected_mask(ctx, op, s_mask & ~s_mask_old))= { + return true; } =20 return fold_masks(ctx, op); @@ -2843,7 +2856,6 @@ void tcg_optimize(TCGContext *s) } =20 /* Assume all bits affected, no bits known zero, no sign reps. */ - ctx.a_mask =3D -1; ctx.z_mask =3D -1; ctx.s_mask =3D 0; =20 --=20 2.43.0