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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8164d3sm2002539b3a.15.2024.12.19.17.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 17:56:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1734659777; x=1735264577; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RCANHJZzdmh7o/b4Y2SxAZxP9CzPNdbu0e2gMuhfVd8=; b=H3SVLNAc0LrYDsggdn85IJL/YhCzOJ+kENbG2nR80WLId/KPK2RvbqlO9ndWmXv37D 52Mg+VlHy5SIoSHvsfNFxaqCSUS6AIZcAOLuPPv5A7eT27rQZea3VEw21Fxa5Ojts/3B 3nINdVfPOm2VkPUpQM3o9UDAP6QPjOe5//y8uYTvjC+huxxATio8LG4fj2kK1PQW4/lQ cWKeVotKbLugSe6ak1xD3nRTlkbpZ1xojffkN7Rxqs+rgjHdfVmxqNf2IOZqlUV9N3V6 bbBgI8+4WAMG+DFVNtnBcL1fspk0sfVrj4h95SR3Kv/bt5Uv/t64oljq8wGPlFMDYqDT FOKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734659777; x=1735264577; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RCANHJZzdmh7o/b4Y2SxAZxP9CzPNdbu0e2gMuhfVd8=; b=X6YyGWUA0rVes3Ak+SiqEioXGw1YKMohqzRobo+FrCSz7FbK660req5LfCoAf50oly BTCx8M5m2MSMSNVbom2pmUZRTbmUS1fjp8LFgngw/TpCL6+LWOuVP3Z8o1dSKV57P0WU X/96BpRfYdDA5fmXyws1MPSJe37aaIxhlOUpfrLrvMAsPsh4jHkaUiDl4E67zkXSJHCq 9SIRiyA9m8vmk7eYFfqLBOXa0Xohhm+BIcn+kbA7I5od5Qg32SK1wj4GL2gInOu8dlbi 36sX4Gg23xX4u7ZY2hcJPacUu6P0t1jhiIGBdzl2HeAu6RqXVPYP5uGOF0XFEnhIYM8V w2AQ== X-Gm-Message-State: AOJu0Yz9pDweu+8dBiaUknKFQRbwaNcRq4mydSV/Svthsg3GRXDGYO1j xtyIbwyI+HYoQhFuctnrEQglmerA38Yk0re1yadsXAn0+fuyoivJUGPPvJiQ X-Gm-Gg: ASbGncuSGk1vSJWBj6pDYyu+R5DVhBcC00WHDS2VSUhCOSHft4pOdXFlFCflZWgzuP7 5ayh23fm9vif8UpwndMViYfcFCtw6VQDBB6sIgwhYTAicPvLYjJs1y7fUC1oOZTAxpNClfzUKqZ uybcSOlFTxz++mibDCLiQRl0PZLTf9aas2R/2RtvKd/XGzXnffpSHTG7Hj6ROSZhRhvzu05RM6C AL3OjmBSdvIJHhcmUERgtyqxREmoTQBwrnY/Er7bdd2whkpWNinzrcW4F5HiQxuEPT91EQvzYmt V/aGjahmUo/2KII8tOeuh0Y/dnpsB/joGZjs6ZTZmQA0yFDB6J6UYoVz7W81yl8= X-Google-Smtp-Source: AGHT+IF4mtho33m/iCTl6owM03TFbsBxV+yWTfKcSxTrsZn3sKYLdxMEo3IoTg8VK/XBuUaQ4vXEwg== X-Received: by 2002:a05:6a21:99a8:b0:1e0:d796:b079 with SMTP id adf61e73a8af0-1e5e0459b32mr1899391637.17.1734659777469; Thu, 19 Dec 2024 17:56:17 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jim Shu , Alistair Francis , Daniel Henrique Barboza Subject: [PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd Date: Fri, 20 Dec 2024 11:54:28 +1000 Message-ID: <20241220015441.317236-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241220015441.317236-1-alistair.francis@wdc.com> References: <20241220015441.317236-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1734660065377116600 Content-Type: text/plain; charset="utf-8" From: Jim Shu DTB is placed to the end of memory, so we will check if the start address of DTB overlaps to the address of kernel/initrd. Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20241120153935.24706-4-jim.shu@sifive.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 3 +++ hw/riscv/boot.c | 25 ++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 06b51ed086..7d59b2e6c6 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -32,6 +32,9 @@ typedef struct RISCVBootInfo { hwaddr image_low_addr; hwaddr image_high_addr; =20 + hwaddr initrd_start; + ssize_t initrd_size; + bool is_32bit; } RISCVBootInfo; =20 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 81d27f935e..bc8074fec8 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -70,6 +70,7 @@ char *riscv_plic_hart_config_string(int hart_count) void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) { info->kernel_size =3D 0; + info->initrd_size =3D 0; info->is_32bit =3D riscv_is_32bit(harts); } =20 @@ -213,6 +214,9 @@ static void riscv_load_initrd(MachineState *machine, RI= SCVBootInfo *info) } } =20 + info->initrd_start =3D start; + info->initrd_size =3D size; + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ if (fdt) { end =3D start + size; @@ -309,6 +313,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwadd= r dram_size, int ret =3D fdt_pack(ms->fdt); hwaddr dram_end, temp; int fdtsize; + uint64_t dtb_start, dtb_start_limit; =20 /* Should only fail if we've built a corrupted tree */ g_assert(ret =3D=3D 0); @@ -319,6 +324,17 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwad= dr dram_size, exit(1); } =20 + if (info->initrd_size) { + /* If initrd is successfully loaded, place DTB after it. */ + dtb_start_limit =3D info->initrd_start + info->initrd_size; + } else if (info->kernel_size) { + /* If only kernel is successfully loaded, place DTB after it. */ + dtb_start_limit =3D info->image_high_addr; + } else { + /* Otherwise, do not check DTB overlapping */ + dtb_start_limit =3D 0; + } + /* * A dram_size =3D=3D 0, usually from a MemMapEntry[].size element, * means that the DRAM block goes all the way to ms->ram_size. @@ -338,7 +354,14 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwad= dr dram_size, temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr= am_end; } =20 - return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + dtb_start =3D QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + + if (dtb_start_limit && (dtb_start < dtb_start_limit)) { + error_report("No enough memory to place DTB after kernel/initrd"); + exit(1); + } + + return dtb_start; } =20 /* --=20 2.47.1