From nobody Tue Dec 24 13:26:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1734660064; cv=none; d=zohomail.com; s=zohoarc; b=NfO30rNiI8srkt3mPRcVPmZOLRuXhKPXbEGxCZMr5O94aSFOMSi+aYePBWrkdqA6EQIjhrw3FicRUBEMh3WCNaJiq7UCmXefQOGYBjFarVDvkHsvMpBFNlUTbwZjS92jrOAmi5gN80BYfYrPk4qESjbnH2jIpRfTNYLkzpT8T1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1734660064; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W+a5eLWtazjKjyGdseEIBKLBcCSyugHNCLmPRqaOCVY=; b=atdLm97XTd7gs8TDZFigAnTMgVakEwqT0dSlsfgbeLaMo0hYLCAMnl6onT3GhcWgvo2o4aZemS87m/JZTffQamQ3FzKCf416JuE92nyOEGPsPbAUvEy4EBH5OgQYZe9vzNrTJqQx7yXZlTQdb1EPypusToor+1IsneHN9pVfIhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1734660064261230.8221156577622; Thu, 19 Dec 2024 18:01:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOSEx-0006G6-36; Thu, 19 Dec 2024 20:55:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOSEi-0006Db-Lj for qemu-devel@nongnu.org; Thu, 19 Dec 2024 20:55:28 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tOSEg-0004Qo-Ln for qemu-devel@nongnu.org; Thu, 19 Dec 2024 20:55:28 -0500 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-725ea1e19f0so1278592b3a.3 for ; Thu, 19 Dec 2024 17:55:25 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8164d3sm2002539b3a.15.2024.12.19.17.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2024 17:55:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1734659724; x=1735264524; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W+a5eLWtazjKjyGdseEIBKLBcCSyugHNCLmPRqaOCVY=; b=L75dT5An23yZYu+HZKgnQ7qyfPDxJVzUX/wJEew6aJot7enDkeAYT0cmBfHocG4XbS B1fyGUTrbatto5qPPuVGo0noG1crDtXRGGe2Z7WyEzfemBzO0UkSs+jGV8HQXBvKpLF9 XFJINlyj84LDwSn0nxgbVD+XnGIWDxkO1Dryu22Rh6KiNhfl8vvJF6iIa324zgxxC4CS hH9sWF1aP+y9d4tTXUJEPok9vnsPdJuE4Z94vntIu/Rf/7UV8E/zGBWdd2hyg3uFy54j 9Vo9QskA/s7S5gw7NeEl0hni2nu2a8e2B1ynvmPlopw2cNjY2HnEfH/Vjfnb8EshEEtj 0N/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734659724; x=1735264524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W+a5eLWtazjKjyGdseEIBKLBcCSyugHNCLmPRqaOCVY=; b=aZBJcKrMROE7TSfErDG0Y945aopK05aN88Ef9AIKRAofx+qsJ9VCjHotUqYluhOWXw S6v2TfFWKoMzMigc4ifsyrwU8jz0TRME/f3mgaLpO4me4twu1m/8HiCa6tslxUNZQF5I RSppIGbl8Dgs3svj1oOdbmfM0Q3b8z57yBTY56gci53AcpNT6d8RCLTlGyoRX8tw+ndI HuLGvnV4Ij1XWwJOM6lCRZvVaRjZnC3RlYDRcjJ/VkEW+9erAG5+7pkAODGNF93borEU 96pEft/W7B0p16yeabT07/29tKwA4PqLGqEZQV1z73IsvrYmsFYSAgX8I8SRPsIsHvEr JLFw== X-Gm-Message-State: AOJu0YwKAtb6QHlxeupl0z/F428h8jMqUd5T8tqy7E+6+MnDmaYs0vgZ 1JiXfUu/TllXjrH8jOY+r1aOgC+qWlvj74tjlM/8lTljNMc90zmHnyhWwg/u X-Gm-Gg: ASbGnctesj+qwSGxuGYJ4Eb+V5NyCiSsVYoMWcImex9fyB1gfKGowzBUtZuQS7kzPBn l4wgwTIPbMGzn/OJ4EAwcWYjrKwYJQ6Th/UdT8FFXbGlXkUUTdV1aGzovPTN66k4hBOz8v+cm/L dfAD25md7esXlxN2PSPsLYdeQ3RV61r/5bBmtzi2A0ImLfF9S+IiNz2aCsEWPlAif4bu4jHt8Mc 5iw8lcIzYEmaOgqhUL5MH6zkgnq1o2RElNoe0R90lgdws2L8psaxNvJRQKavYN092yQIVogiJqP Gv+8BW1ezaPhZA8PZXlQ/fhDMOlEUj8W23gMuqELDbXzkY/V4OYkUUlnbtiswlo= X-Google-Smtp-Source: AGHT+IF7pu5sOzVMQagBNFw2HSUyf58p0ionaciagDP4g8Z39+gaCWnk9djx1OYyIJt66Ie0rKzQFg== X-Received: by 2002:a05:6a00:4096:b0:729:c7b:9385 with SMTP id d2e1a72fcca58-72abdd7bdecmr1443652b3a.6.1734659723952; Thu, 19 Dec 2024 17:55:23 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anton Blanchard , Alistair Francis , Daniel Henrique Barboza Subject: [PULL v2 10/39] target/riscv: Add Tenstorrent Ascalon CPU Date: Fri, 20 Dec 2024 11:54:10 +1000 Message-ID: <20241220015441.317236-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241220015441.317236-1-alistair.francis@wdc.com> References: <20241220015441.317236-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1734660065258116600 Content-Type: text/plain; charset="utf-8" From: Anton Blanchard Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to 8 wide RV64 cores. More details can be found at https://tenstorrent.com/ip/tt-ascalon Signed-off-by: Anton Blanchard Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20241113110459.1607299-1-antonb@tenstorrent.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 67 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 62115375cd..6547642287 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -49,6 +49,7 @@ #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") +#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4329015076..66e00ed260 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -579,6 +579,72 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } =20 +/* Tenstorrent Ascalon */ +static void rv64_tt_ascalon_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); + env->priv_ver =3D PRIV_VERSION_1_13_0; + + /* Enable ISA extensions */ + cpu->cfg.mmu =3D true; + cpu->cfg.vlenb =3D 256 >> 3; + cpu->cfg.elen =3D 64; + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; + cpu->cfg.rvv_ma_all_1s =3D true; + cpu->cfg.rvv_ta_all_1s =3D true; + cpu->cfg.misa_w =3D true; + cpu->cfg.pmp =3D true; + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.ext_zic64b =3D true; + cpu->cfg.ext_zicbom =3D true; + cpu->cfg.ext_zicbop =3D true; + cpu->cfg.ext_zicboz =3D true; + cpu->cfg.ext_zicntr =3D true; + cpu->cfg.ext_zicond =3D true; + cpu->cfg.ext_zicsr =3D true; + cpu->cfg.ext_zifencei =3D true; + cpu->cfg.ext_zihintntl =3D true; + cpu->cfg.ext_zihintpause =3D true; + cpu->cfg.ext_zihpm =3D true; + cpu->cfg.ext_zimop =3D true; + cpu->cfg.ext_zawrs =3D true; + cpu->cfg.ext_zfa =3D true; + cpu->cfg.ext_zfbfmin =3D true; + cpu->cfg.ext_zfh =3D true; + cpu->cfg.ext_zfhmin =3D true; + cpu->cfg.ext_zcb =3D true; + cpu->cfg.ext_zcmop =3D true; + cpu->cfg.ext_zba =3D true; + cpu->cfg.ext_zbb =3D true; + cpu->cfg.ext_zbs =3D true; + cpu->cfg.ext_zkt =3D true; + cpu->cfg.ext_zvbb =3D true; + cpu->cfg.ext_zvbc =3D true; + cpu->cfg.ext_zvfbfmin =3D true; + cpu->cfg.ext_zvfbfwma =3D true; + cpu->cfg.ext_zvfh =3D true; + cpu->cfg.ext_zvfhmin =3D true; + cpu->cfg.ext_zvkng =3D true; + cpu->cfg.ext_smaia =3D true; + cpu->cfg.ext_smstateen =3D true; + cpu->cfg.ext_ssaia =3D true; + cpu->cfg.ext_sscofpmf =3D true; + cpu->cfg.ext_sstc =3D true; + cpu->cfg.ext_svade =3D true; + cpu->cfg.ext_svinval =3D true; + cpu->cfg.ext_svnapot =3D true; + cpu->cfg.ext_svpbmt =3D true; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif +} + #ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { @@ -2984,6 +3050,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), #ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), --=20 2.47.1