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Tsirkin" , Richard Henderson , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v6 1/4] i386/cpu: Support thread and module level cache topology Date: Thu, 19 Dec 2024 16:32:34 +0800 Message-Id: <20241219083237.265419-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219083237.265419-1-zhao1.liu@intel.com> References: <20241219083237.265419-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1734596102544116600 Content-Type: text/plain; charset="utf-8" Allow cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 525339945920..87ffb9840cc1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -243,9 +243,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, uint32_t num_ids =3D 0; =20 switch (share_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + num_ids =3D 1; + break; case CPU_TOPOLOGY_LEVEL_CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids =3D 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; @@ -253,10 +259,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, num_ids =3D 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } =20 --=20 2.34.1