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Tsirkin" , Richard Henderson , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v6 1/4] i386/cpu: Support thread and module level cache topology Date: Thu, 19 Dec 2024 16:32:34 +0800 Message-Id: <20241219083237.265419-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219083237.265419-1-zhao1.liu@intel.com> References: <20241219083237.265419-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1734596102544116600 Content-Type: text/plain; charset="utf-8" Allow cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Reviewed-by from previous review). --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 525339945920..87ffb9840cc1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -243,9 +243,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, uint32_t num_ids =3D 0; =20 switch (share_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + num_ids =3D 1; + break; case CPU_TOPOLOGY_LEVEL_CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; + case CPU_TOPOLOGY_LEVEL_MODULE: + num_ids =3D 1 << apicid_module_offset(topo_info); + break; case CPU_TOPOLOGY_LEVEL_DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; @@ -253,10 +259,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInf= o *topo_info, num_ids =3D 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } =20 --=20 2.34.1 From nobody Mon Dec 23 22:59:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1734596082; cv=none; d=zohomail.com; s=zohoarc; b=NJ7hXGcq7jS2IFDeABqvEuqG5xE8VyXDmZoW6Ms7TBqYH/vHJC2ZlqRsofkFBrJJzS7rxwnDz7lvXZ/RsOlYp4negOG8M1h1Ma246GrM0LwvKrqaImKYV/fmWKAEFgF1JqosiUr93reMuqO8t+WPvIQ7w1ZstblOaqxYUPztwKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1734596082; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=x9vF51Ut+Ki9ogotkSCAeiliea+EVliZdYbw0UzKpzE=; b=HOVsdO0untUNoM1uM6udOYfUURz/mLnFiZWMSRYEyfXQS7yAqVCk8O5fyPIyzRykpFQLgWP2t249GG7euA8GdwDn4Yojx0PBwqU+1Z4SqWKtiMPZdAjXFl9gyhfBqzVfDdsJ+YanXzYGJ00G80Rj7KfrL+gpslgynIrCj5oZQ2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1734596081577880.6796357800596; Thu, 19 Dec 2024 00:14:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOBfv-00057W-7S; Thu, 19 Dec 2024 03:14:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOBft-00056Z-72 for qemu-devel@nongnu.org; Thu, 19 Dec 2024 03:14:25 -0500 Received: from mgamail.intel.com ([192.198.163.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOBfr-0000JK-I7 for qemu-devel@nongnu.org; Thu, 19 Dec 2024 03:14:24 -0500 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 00:14:22 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa001.fm.intel.com with ESMTP; 19 Dec 2024 00:14:18 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734596064; x=1766132064; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t15kUcDSUDGh6VCzQEjxGJih7PIkID2ut/arbO15P9k=; b=KIPQM9MC3WYQPgZ7e0beFNR7675tPWJVKp9IAfL8M9zLUPXvTBq9vOYk sMrv5myalIsGBObzkZrS4hW1OtZE5hCnUDhEk2EkMhF9c4TV09l6stzA2 i9J6pIMSGAr05I7VQqqJz//GmuHjEKOR5FxAsHzuhHtqTIUbZqdwQ14ec MRhMgCWRAltWjgJmCwgq/TJIHvYjQKJG2s+OSJxZZ4j85pDvIGIZqX3S/ B3ophRZ8jHphORgJic/5J1G4lQT0Ey0choxRVE5zJXARno/apNWxGU5sc 5/nplR6Z5sYPOgi+IeyeM0l5TlKaIOZ6HU5/WhSOjDRJ/yRB+X8GQVTZn g==; X-CSE-ConnectionGUID: I1ralDoyTduv945aTUNc7Q== X-CSE-MsgGUID: FN9PDRu1SDyABOzCVYI9tA== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34378636" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34378636" X-CSE-ConnectionGUID: ZMs8fyShQJ+JrGGTIbhtqw== X-CSE-MsgGUID: i0VdozjBRWeb+soBYWCkFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="129097528" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v6 2/4] i386/cpu: Update cache topology with machine's configuration Date: Thu, 19 Dec 2024 16:32:35 +0800 Message-Id: <20241219083237.265419-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219083237.265419-1-zhao1.liu@intel.com> References: <20241219083237.265419-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1734596084039116600 Content-Type: text/plain; charset="utf-8" User will configure smp cache topology via -machine smp-cache. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Reviewed-by from previous review). --- Changes since Patch v3: * Updated MachineState.smp_cache to consume "default" level and did a check to ensure topological hierarchical relationships are correct. --- target/i386/cpu.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 87ffb9840cc1..bd5620dcc086 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7757,6 +7757,64 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] =3D 0; } =20 +#ifndef CONFIG_USER_ONLY +static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, + Error **errp) +{ + CPUX86State *env =3D &cpu->env; + CpuTopologyLevel level; + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level =3D level; + env->cache_info_amd.l1d_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_cpuid4.l1d_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, + env->cache_info_amd.l1d_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level =3D level; + env->cache_info_amd.l1i_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_cpuid4.l1i_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, + env->cache_info_amd.l1i_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level =3D level; + env->cache_info_amd.l2_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_cpuid4.l2_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, + env->cache_info_amd.l2_cache->share_level); + } + + level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); + if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level =3D level; + env->cache_info_amd.l3_cache->share_level =3D level; + } else { + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_cpuid4.l3_cache->share_level); + machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, + env->cache_info_amd.l3_cache->share_level); + } + + if (!machine_check_smp_cache(ms, errp)) { + return false; + } + return true; +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -7981,6 +8039,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates + * if user didn't set smp_cache. + */ + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); =20 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { --=20 2.34.1 From nobody Mon Dec 23 22:59:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1734596080; cv=none; d=zohomail.com; s=zohoarc; b=SapAlbUDktU47IFLs2/3y5uD7cN2WaNSLFe396qmIq31wzCg+qRLajKWisSkQe7qfthvyguQj3Vlh2BLmtU8EuY6heH8UIGoLhRti5GN1WJdVfoLsKkr4pNl7bICyKE10FJaLLL4TVtZM9petsOSdoXdn/dIMvtnhy6WUK+Jukw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1734596080; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: +l/PRFMoQTW8pRq+CoYOvQ== X-CSE-MsgGUID: zqhz3F6iQd2UlFGyMmojQQ== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34378656" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34378656" X-CSE-ConnectionGUID: e19KNwlHRdS/CObwwXSWzA== X-CSE-MsgGUID: 4TUEQGL0TmS/GCoIpGNGdg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="129097549" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Yongwei Ma Subject: [PATCH v6 3/4] i386/pc: Support cache topology in -machine for PC machine Date: Thu, 19 Dec 2024 16:32:36 +0800 Message-Id: <20241219083237.265419-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219083237.265419-1-zhao1.liu@intel.com> References: <20241219083237.265419-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1734596082384116600 Content-Type: text/plain; charset="utf-8" Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Additionally, add the document of "-machine smp-cache" in qemu-options.hx. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Cameron Reviewed-by from previous review). --- Changes since Patch v3: * Described the omitting cache will use "default" level and described the default cache topology model of i386 PC machine. (Daniel) --- hw/i386/pc.c | 4 ++++ qemu-options.hx | 31 ++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 92047ce8c9df..7804991229f1 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1797,6 +1797,10 @@ static void pc_machine_class_init(ObjectClass *oc, v= oid *data) mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; mc->smp_props.modules_supported =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] =3D true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] =3D true; mc->default_ram_id =3D "pc.ram"; pcmc->default_smbios_ep_type =3D SMBIOS_ENTRY_POINT_TYPE_AUTO; =20 diff --git a/qemu-options.hx b/qemu-options.hx index cc694d3b890c..257563437c05 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " memory-encryption=3D@var{} memory encryption object t= o use (default=3Dnone)\n" " hmat=3Don|off controls ACPI HMAT support (default=3Do= ff)\n" " memory-backend=3D'backend-id' specifies explicitly pr= ovided backend for main RAM (default=3Dnone)\n" - " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n", + " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n" + " smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3D= topologylevel\n", QEMU_ARCH_ALL) SRST ``-machine [type=3D]name[,prop=3Dvalue[,...]]`` @@ -159,6 +160,34 @@ SRST :: =20 -machine cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl= .1,cxl-fmw.0.size=3D128G,cxl-fmw.0.interleave-granularity=3D512 + + ``smp-cache.0.cache=3Dcachename,smp-cache.0.topology=3Dtopologylevel`` + Define cache properties for SMP system. + + ``cache=3Dcachename`` specifies the cache that the properties will= be + applied on. This field is the combination of cache level and cache + type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction + cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache). + + ``topology=3Dtopologylevel`` sets the cache topology level. It acc= epts + CPU topology levels including ``thread``, ``core``, ``module``, + ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a speci= al + value ``default``. If ``default`` is set, then the cache topology = will + follow the architecture's default cache topology model. If another + topology level is set, the cache will be shared at corresponding C= PU + topology level. For example, ``topology=3Dcore`` makes the cache s= hared + by all threads within a core. The omitting cache will default to u= sing + the ``default`` level. + + The default cache topology model for an i386 PC machine is as foll= ows: + ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``= l3`` + cache is per ``die``. + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dcore,s= mp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dcore ERST =20 DEF("M", HAS_ARG, QEMU_OPTION_M, --=20 2.34.1 From nobody Mon Dec 23 22:59:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1734596100; cv=none; d=zohomail.com; s=zohoarc; b=a371jJFckilS7gRymhP3x9TpKltvK7FYThJFUWjK6PmDRtIrI0kk8ShFSSsZKNUXB/nSO5NQ5LWM5/CuNquB9kJIuNxScaftzOY501qMo9XW0AXaYUvJHreqa4VUsma7hJRJmvT1rURXmFfXiTMWhqHfzROSrH5zEAgtjmrJ2mQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1734596100; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ySW3HOYo4R0jpgJSVRJoSUOoQ6sksAjDeMlwP8B0wJ0=; b=hnIS2X37B5sjgFyD2MWsa/FW3REYn0rEnIXfWwusQFw0Ofnuynh+d1XXqfxGlvO3HYgutxUn8UcooabwLAL+Shw9q8xpuGbObbFKiX3ohGz2ahkE5c63lqSbyEMHc0e9p1P0F+0AAwgDdRFSIC83MYoZ10yCTwX790bPyuEfVfQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1734596100316264.71203762509185; Thu, 19 Dec 2024 00:15:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tOBgH-0005wX-7m; Thu, 19 Dec 2024 03:14:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOBgF-0005nM-33 for qemu-devel@nongnu.org; Thu, 19 Dec 2024 03:14:47 -0500 Received: from mgamail.intel.com ([192.198.163.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tOBgD-0000Kl-8P for qemu-devel@nongnu.org; Thu, 19 Dec 2024 03:14:46 -0500 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2024 00:14:29 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa001.fm.intel.com with ESMTP; 19 Dec 2024 00:14:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734596085; x=1766132085; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HyQNL2QRST3bzAofC6NdSneNk+dJQgGE9UE8ka+3X3M=; b=bFObPyP/42X7hgOEHVtaSX83maSx9ppMIQejSEWnOoFb0g5HkrShqR8U 5ye71wVYUtAWLFZYscryg7jLVrP9cA56IHpr08dV8W4y3Aug3OHikkC1A O3J2el2XswgibO57hQPtpaS197odVARFtkxr9CowJCTsODIuItsQxBO49 ZPMw5qE7dAkajwo/Bl7ZSF3SMQeZk6HB5KCMJXv1bAXSDNYn1Old01xD2 MVpVrEVC0/0koaTP5VJjq/DncpeQOUHsEJcwXEcI83O0f7dfeh+GQsaEy JYyQMCrlKNB/I1Ud89+Nm1WJMAB3ExjJTT8CXivRij2IRK6rJnia3An9W w==; X-CSE-ConnectionGUID: RdvtOebYSZqXDQ33SVV2bg== X-CSE-MsgGUID: AC8qWGOkQ6CusS2tIgz3vQ== X-IronPort-AV: E=McAfee;i="6700,10204,11290"; a="34378675" X-IronPort-AV: E=Sophos;i="6.12,247,1728975600"; d="scan'208";a="34378675" X-CSE-ConnectionGUID: 6Zn6Kp97QoubQDBwujTxcw== X-CSE-MsgGUID: 3p7A14JdQe+SIqaC6tm+xg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="129097570" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Jonathan Cameron , Alireza Sanaee , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH v6 4/4] i386/cpu: add has_caches flag to check smp_cache configuration Date: Thu, 19 Dec 2024 16:32:37 +0800 Message-Id: <20241219083237.265419-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241219083237.265419-1-zhao1.liu@intel.com> References: <20241219083237.265419-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1734596102596116600 Content-Type: text/plain; charset="utf-8" From: Alireza Sanaee Add has_caches flag to SMPCompatProps, which helps in avoiding extra checks for every single layer of caches in x86 (and ARM in future). Signed-off-by: Alireza Sanaee Signed-off-by: Zhao Liu Reviewed-by: Jonathan Cameron Reviewed-by from previous review). --- Note: Picked from Alireza's series with the changes: * Moved the flag to SMPCompatProps with a new name "has_caches". This way, it remains consistent with the function and style of "has_clusters" in SMPCompatProps. * Dropped my previous TODO with the new flag. --- Changes since Patch v2: * Picked a new patch frome Alireza's ARM smp-cache series. --- hw/core/machine-smp.c | 2 ++ include/hw/boards.h | 3 +++ target/i386/cpu.c | 11 +++++------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index b954eb849027..fe66961341fe 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -325,6 +325,8 @@ bool machine_parse_smp_cache(MachineState *ms, return false; } } + + mc->smp_props.has_caches =3D true; return true; } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index 5723ee76bdea..c647e507d1a9 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -156,6 +156,8 @@ typedef struct { * @modules_supported - whether modules are supported by the machine * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are * supported by the machine + * @has_caches - whether cache properties are explicitly specified in the + * user provided smp-cache configuration */ typedef struct { bool prefer_sockets; @@ -166,6 +168,7 @@ typedef struct { bool drawers_supported; bool modules_supported; bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX]; + bool has_caches; } SMPCompatProps; =20 /** diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bd5620dcc086..a9700fba991f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8039,13 +8039,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); =20 - /* - * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates - * if user didn't set smp_cache. - */ - if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { - return; + if (mc->smp_props.has_caches) { + if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { + return; + } } =20 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); --=20 2.34.1