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Thu, 19 Dec 2024 00:33:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IGJTxGPQXyWfsoNvpTggTdyX7K8DAvvijr2gt16sCgoGWG/brNtkf9fEokzDOh0TlRipa9iSg== X-Received: by 2002:a05:600c:4586:b0:434:f586:753c with SMTP id 5b1f17b1804b1-43655341348mr47632395e9.7.1734597225026; Thu, 19 Dec 2024 00:33:45 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu Subject: [PULL 35/41] rust: pl011: fix declaration of LineControl bits Date: Thu, 19 Dec 2024 09:32:22 +0100 Message-ID: <20241219083228.363430-36-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241219083228.363430-1-pbonzini@redhat.com> References: <20241219083228.363430-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.116, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1734597455940116600 The bits in the LineControl struct were backwards. :( Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/lib.rs | 82 +++++++++++++++++------------------ 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index 4dc0e8f345f..d5089f78854 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -319,32 +319,21 @@ fn default() -> Self { /// Line Control Register, `UARTLCR_H` #[doc(alias =3D "UARTLCR_H")] pub struct LineControl { - /// 15:8 - Reserved, do not modify, read as zero. - _reserved_zero_no_modify: u8, - /// 7 SPS Stick parity select. - /// 0 =3D stick parity is disabled - /// 1 =3D either: - /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked - /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is - /// transmitted and checked as a 0. This bit has no effect when - /// the PEN bit disables parity checking and generation. See Table= 3-11 - /// on page 3-14 for the parity truth table. - pub sticky_parity: bool, - /// WLEN Word length. These bits indicate the number of data bits - /// transmitted or received in a frame as follows: b11 =3D 8 bits - /// b10 =3D 7 bits - /// b01 =3D 6 bits - /// b00 =3D 5 bits. - pub word_length: WordLength, - /// FEN Enable FIFOs: - /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome - /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO - /// buffers are enabled (FIFO mode). - pub fifos_enabled: Mode, - /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits - /// are transmitted at the end of the frame. The receive - /// logic does not check for two stop bits being received. - pub two_stops_bits: bool, + /// BRK Send break. + /// + /// If this bit is set to `1`, a low-level is continually output o= n the + /// `UARTTXD` output, after completing transmission of the + /// current character. For the proper execution of the break comma= nd, + /// the software must set this bit for at least two complete + /// frames. For normal use, this bit must be cleared to `0`. + pub send_break: bool, + /// 1 PEN Parity enable: + /// + /// - 0 =3D parity is disabled and no parity bit added to the data= frame + /// - 1 =3D parity checking and generation is enabled. + /// + /// See Table 3-11 on page 3-14 for the parity truth table. + pub parity_enabled: bool, /// EPS Even parity select. Controls the type of parity the UART u= ses /// during transmission and reception: /// - 0 =3D odd parity. The UART generates or checks for an odd nu= mber of @@ -355,21 +344,32 @@ pub struct LineControl { /// and generation. See Table 3-11 on page 3-14 for the parity /// truth table. pub parity: Parity, - /// 1 PEN Parity enable: - /// - /// - 0 =3D parity is disabled and no parity bit added to the data= frame - /// - 1 =3D parity checking and generation is enabled. - /// - /// See Table 3-11 on page 3-14 for the parity truth table. - pub parity_enabled: bool, - /// BRK Send break. - /// - /// If this bit is set to `1`, a low-level is continually output o= n the - /// `UARTTXD` output, after completing transmission of the - /// current character. For the proper execution of the break comma= nd, - /// the software must set this bit for at least two complete - /// frames. For normal use, this bit must be cleared to `0`. - pub send_break: bool, + /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop= bits + /// are transmitted at the end of the frame. The receive + /// logic does not check for two stop bits being received. + pub two_stops_bits: bool, + /// FEN Enable FIFOs: + /// 0 =3D FIFOs are disabled (character mode) that is, the FIFOs b= ecome + /// 1-byte-deep holding registers 1 =3D transmit and receive FIFO + /// buffers are enabled (FIFO mode). + pub fifos_enabled: Mode, + /// WLEN Word length. These bits indicate the number of data bits + /// transmitted or received in a frame as follows: b11 =3D 8 bits + /// b10 =3D 7 bits + /// b01 =3D 6 bits + /// b00 =3D 5 bits. + pub word_length: WordLength, + /// 7 SPS Stick parity select. + /// 0 =3D stick parity is disabled + /// 1 =3D either: + /// =E2=80=A2 if the EPS bit is 0 then the parity bit is transmitt= ed and checked + /// as a 1 =E2=80=A2 if the EPS bit is 1 then the parity bit is + /// transmitted and checked as a 0. This bit has no effect when + /// the PEN bit disables parity checking and generation. See Table= 3-11 + /// on page 3-14 for the parity truth table. + pub sticky_parity: bool, + /// 15:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u8, } =20 impl LineControl { --=20 2.47.1