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Thu, 19 Dec 2024 00:33:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IE0ft6AoK4qyt2SBK+6eKmzZNwLB9YgQsLbUYr6S07T6byM2bmBH/OaV/q8xYBdLj04E3VOEw== X-Received: by 2002:a05:600c:5107:b0:434:ff9d:a370 with SMTP id 5b1f17b1804b1-4365c7415f9mr22208245e9.0.1734597188680; Thu, 19 Dec 2024 00:33:08 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 19/41] target/riscv: Do not abuse DEFINE_PROP_END_OF_LIST Date: Thu, 19 Dec 2024 09:32:06 +0100 Message-ID: <20241219083228.363430-20-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241219083228.363430-1-pbonzini@redhat.com> References: <20241219083228.363430-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.116, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1734597229075116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson These are not arrays of Property and had no business using DEFINE_PROP_END_OF_LIST. Use plain { } instead. Signed-off-by: Richard Henderson Link: https://lore.kernel.org/r/20241216035109.3486070-20-richard.henderson= @linaro.org Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4329015076d..a5aa3a8670a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -213,7 +213,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), =20 - DEFINE_PROP_END_OF_LIST(), + { }, }; =20 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) @@ -1575,7 +1575,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false), MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false), =20 - DEFINE_PROP_END_OF_LIST(), + { }, }; =20 const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { @@ -1592,12 +1592,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[= ] =3D { MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), =20 - DEFINE_PROP_END_OF_LIST(), + { }, }; =20 /* These are experimental so mark with 'x-' */ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { - DEFINE_PROP_END_OF_LIST(), + { }, }; =20 /* @@ -1610,7 +1610,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), =20 - DEFINE_PROP_END_OF_LIST(), + { }, }; =20 /* Deprecated entries marked for future removal */ @@ -1627,7 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_ext= s[] =3D { MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false), =20 - DEFINE_PROP_END_OF_LIST(), + { }, }; =20 static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, @@ -2699,7 +2699,6 @@ static const Property riscv_cpu_properties[] =3D { * it with -x and default to 'false'. */ DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), - DEFINE_PROP_END_OF_LIST(), }; =20 #if defined(TARGET_RISCV64) --=20 2.47.1