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From: Alistair Francis <alistair23@gmail.com>
X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, MollyChen <xiaoou@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU
Date: Thu, 19 Dec 2024 08:30:09 +1000
Message-ID: <20241218223010.1931245-40-alistair.francis@wdc.com>
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From: MollyChen <xiaoou@iscas.ac.cn>
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen <xiaoou@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241205073622.46052-1-xiaoou@iscas.ac.cn>
[ Changes by AF
- Fixup code formatting
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 6547642287..d56b067bf2 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -50,6 +50,7 @@
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
+#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nan=
hu")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
=20
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d7b830d489..58bb5196a8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,34 @@ static void rv64_tt_ascalon_cpu_init(Object *obj)
#endif
}
=20
+static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
+{
+ CPURISCVState *env =3D &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu =3D RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
+ env->priv_ver =3D PRIV_VERSION_1_12_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.ext_zbc =3D true;
+ cpu->cfg.ext_zbkb =3D true;
+ cpu->cfg.ext_zbkc =3D true;
+ cpu->cfg.ext_zbkx =3D true;
+ cpu->cfg.ext_zknd =3D true;
+ cpu->cfg.ext_zkne =3D true;
+ cpu->cfg.ext_zknh =3D true;
+ cpu->cfg.ext_zksed =3D true;
+ cpu->cfg.ext_zksh =3D true;
+ cpu->cfg.ext_svinval =3D true;
+
+ cpu->cfg.mmu =3D true;
+ cpu->cfg.pmp =3D true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -3056,6 +3084,8 @@ static const TypeInfo riscv_cpu_type_infos[] =3D {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90=
6_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo=
n_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1=
_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
+ MXL_RV64, rv64_xiangshan_=
nanhu_cpu_init),
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu=
_init),
#endif /* CONFIG_TCG */
--=20
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