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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PULL 38/39] target/riscv: add ssstateen
Date: Thu, 19 Dec 2024 08:30:08 +1000
Message-ID: <20241218223010.1931245-39-alistair.francis@wdc.com>
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
ssstateen is defined in RVA22 as:
"Supervisor-mode view of the state-enable extension. The supervisor-mode
(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
must be provided."
Add ssstateen as a named feature that is available if we also have
smstateen.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20241113171755.978109-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 2 ++
target/riscv/tcg/tcg-cpu.c | 9 ++++++++-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index d8771ca641..a1457ab4f4 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -140,6 +140,7 @@ struct RISCVCPUConfig {
/* Named features */
bool ext_svade;
bool ext_zic64b;
+ bool ext_ssstateen;
=20
/*
* Always 'true' booleans for named features
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 18f4d94b6e..d7b830d489 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D {
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
@@ -1677,6 +1678,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e=
xts[] =3D {
*/
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D {
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
+ MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
=20
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 48a55ba1d8..cbf2cf1963 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -204,10 +204,15 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu=
, uint32_t feat_offset)
* All other named features are already enabled
* in riscv_tcg_cpu_instance_init().
*/
- if (feat_offset =3D=3D CPU_CFG_OFFSET(ext_zic64b)) {
+ switch (feat_offset) {
+ case CPU_CFG_OFFSET(ext_zic64b):
cpu->cfg.cbom_blocksize =3D 64;
cpu->cfg.cbop_blocksize =3D 64;
cpu->cfg.cboz_blocksize =3D 64;
+ break;
+ case CPU_CFG_OFFSET(ext_ssstateen):
+ cpu->cfg.ext_smstateen =3D true;
+ break;
}
}
=20
@@ -343,6 +348,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *c=
pu)
cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 &&
cpu->cfg.cbop_blocksize =3D=3D 64 &&
cpu->cfg.cboz_blocksize =3D=3D 64;
+
+ cpu->cfg.ext_ssstateen =3D cpu->cfg.ext_smstateen;
}
=20
static void riscv_cpu_validate_g(RISCVCPU *cpu)
--=20
2.47.1